JPH0138376B2 - - Google Patents
Info
- Publication number
- JPH0138376B2 JPH0138376B2 JP14493182A JP14493182A JPH0138376B2 JP H0138376 B2 JPH0138376 B2 JP H0138376B2 JP 14493182 A JP14493182 A JP 14493182A JP 14493182 A JP14493182 A JP 14493182A JP H0138376 B2 JPH0138376 B2 JP H0138376B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- island
- etching
- large number
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 2
- 239000010408 film Substances 0.000 description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- AMWRITDGCCNYAT-UHFFFAOYSA-L hydroxy(oxo)manganese;manganese Chemical compound [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 208000002193 Pain Diseases 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- -1 gold and aluminum Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000036407 pain Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は、単位投影面積当りの静電容量を増加
させるためになされ、ICに適合した基板に凹凸
をつける方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming irregularities on a substrate suitable for an IC in order to increase the capacitance per unit projected area.
従来、単位投影面積当りの静電容量を増加する
ために電極に凹凸をつける方法は、電解コンデン
サ等で実用されている。この方法は、例えば、ア
ルミニウム電解コンデンサの場合、アルミニウム
電極を塩酸等によつて表面を腐食させ、結果とし
て、電子顕微鏡レベルまで拡大しても、スポンジ
状に見える凹凸をつけ、しかる後、コンデンサ用
の陽極酸化膜を形成し、一方の電極はもちろん、
上記のアルミニウム電極とし、他の一方の電極
は、液体型の場合は電解液とし、固体型の場合は
例えばマンガン酸化物として、小型で大容量の電
解コンデンサを実現している。 Conventionally, a method of forming irregularities on electrodes in order to increase capacitance per unit projected area has been put to practical use in electrolytic capacitors and the like. For example, in the case of an aluminum electrolytic capacitor, this method corrodes the surface of the aluminum electrode with hydrochloric acid, etc., resulting in unevenness that looks spongy even when magnified to the level of an electron microscope. Forms an anodic oxide film on one electrode,
A small, large-capacity electrolytic capacitor is realized by using the above-mentioned aluminum electrode and using an electrolyte for the other electrode in the case of a liquid type, or, for example, manganese oxide in the case of a solid type.
このような技術をICのコンデンサの製造に適
用すると、ICの製造工程で薬品にさらしたのち
高温炉に投入することはよくあるが、上記の如
き、スポンジ状の電極構造ではスポンジ状の凹部
に残存する薬品類が上記の炉を汚染する欠点があ
つた。その他に、スポンジ状の穴に残存する薬品
が完成品の信頼性を低下させたり、また折角、凹
凸をつけ面積を稼いでも、対向電極材料に選択の
余地がなく、その面積の極く一部した利用できな
いなどの欠点があつた。 When this kind of technology is applied to the manufacture of IC capacitors, the IC is often exposed to chemicals in the manufacturing process and then placed in a high-temperature furnace. There was a drawback that the remaining chemicals contaminated the above-mentioned furnace. In addition, chemicals remaining in the sponge-like holes reduce the reliability of the finished product, and even if you take the pains to create unevenness to increase the area, there is no choice in the counter electrode material, and only a small portion of that area There were drawbacks such as the inability to use the service.
また、従来の写真食刻法を用いても凹凸をつけ
ることは可能であるが、凹凸の繰り返しの寸法
は、写真食刻の最小寸法より小さくできないこと
より、以下二つの欠点が生じる。すなわち、凹凸
によつて面積を増加させる場合、穴の幅に対して
その深さは、同程度かさらに大きくないと、面倒
な工程を採用するのに見合つた面積増加は望めな
い。穴の幅は現在の実用レベルの最小値で約2μ
ｍであるから、深さは2μｍ以上となる。このよ
うな深い凹凸上に、後工程で電極材料に2μｍほ
どと言つた微細なパターン形成ができないことが
第１の欠点であり、もう一つの欠点は、IC中の
コンデンサの縦横のサイズが上記の写真食刻の最
小寸法とほぼ同じ大きさとなり事実上適用できな
いことであつた。 Furthermore, although it is possible to create irregularities using conventional photo-etching methods, the following two drawbacks occur because the repeating dimension of the irregularities cannot be smaller than the minimum dimension of photo-etching. In other words, when increasing the area by forming irregularities, unless the depth is equal to or larger than the width of the hole, it is not possible to expect an increase in area commensurate with the use of a troublesome process. The width of the hole is approximately 2μ at the current practical level.
m, the depth is 2 μm or more. The first drawback is that it is not possible to form a fine pattern of about 2 μm on the electrode material in the subsequent process on such deep unevenness.Another drawback is that the vertical and horizontal sizes of the capacitors in the IC are The size was almost the same as the minimum dimension of a photographic engraving, making it virtually impossible to apply.
本発明は、上記の如き従来のものの欠点を除去
するためになされたもので、非常に薄いために多
数の島状構造に形成された薄膜をマスクにして食
刻することにより、基板に形状・寸法は不規則で
あるが、極めて微細で極めて浅い凹凸を形成し充
分な電極面積の増加をもたらす方法を提供するこ
とを目的としている。 The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional methods.The present invention is made to eliminate the drawbacks of the conventional methods. Although the dimensions are irregular, the purpose is to provide a method of forming extremely fine and extremely shallow irregularities to sufficiently increase the electrode area.
以下、本発明の一実施例を図面によつて説明す
る。第１図〜第４図は本発明の一実施例の主要工
程における状態を示す断面図である。 An embodiment of the present invention will be described below with reference to the drawings. 1 to 4 are cross-sectional views showing the main steps of an embodiment of the present invention.
第１図はシリコン基板１を酸化し数100Åの熱
酸化膜２を形成し、さらに非常に薄いために多数
の島状構造に形成されるポリシリコン膜３を成長
させたものである。このポリシリコン膜３の島状
構造の粒径は、膜厚、成長温度等で制御でき、数
100〜数1000Åの範囲にすることは可能である。 In FIG. 1, a silicon substrate 1 is oxidized to form a thermal oxide film 2 with a thickness of several hundred Å, and a polysilicon film 3, which is extremely thin and is formed into many island-like structures, is further grown. The grain size of the island-like structure of this polysilicon film 3 can be controlled by film thickness, growth temperature, etc.
It is possible to range from 100 to several thousand Å.
第２図はポリシリコン膜３をマスクに熱酸化膜
２をエツチングした状態を示す。このとき、実際
には、後の電極面積増加が最大になるように、ポ
リシリコン膜３の下の熱酸化膜２に、適当なアン
ダー・カツテイング（undercutting）を行い、こ
の熱酸化膜２の抜き残しの比を制御することはい
うまでもない。 FIG. 2 shows a state in which the thermal oxide film 2 is etched using the polysilicon film 3 as a mask. At this time, in order to maximize the subsequent increase in electrode area, appropriate undercutting is performed on the thermal oxide film 2 under the polysilicon film 3, and this thermal oxide film 2 is removed. Needless to say, it is necessary to control the remaining ratio.
第３図は第２図の熱酸化膜２をマスクしてシリ
コン基板１を数100〜数1000Åエツチングした状
態を示す。このとき、いわゆる異方性エツチング
を行うのが面積増加を図る上で有利で、その場合
には、前もつて、第２図におけるポリシリコン膜
３のヒサシ部分〔熱酸化膜２のアンダー・カツト
のある場合〕を等方性エツチングにより除去する
のが望ましい。 FIG. 3 shows a state in which the silicon substrate 1 has been etched by several hundred to several thousand angstroms using the thermal oxide film 2 of FIG. 2 as a mask. At this time, it is advantageous to perform so-called anisotropic etching in order to increase the area. It is desirable to remove it by isotropic etching.
第４図は第３図の熱酸化膜３を除去した状態を
示し、シリコン基板１に溝の幅・深さが数100〜
数1000Åの微細かつ極めて浅い凹凸をつけること
ができることを示している。 FIG. 4 shows a state in which the thermal oxide film 3 shown in FIG.
This shows that it is possible to form fine and extremely shallow irregularities of several thousand angstroms.
第５図は、第４図に示すような極めて微細な凹
凸のついたシリコン基板１の表面に薄い一様な厚
さの熱酸化膜４を形成したのち、ポリシリコン膜
５を堆積させることにより、シリコン基板１とポ
リシリコン膜５とを電極として単位投影面積当り
の容量が増加したコンデンサを得ることを示した
図である。 In FIG. 5, a thin, uniformly thick thermal oxide film 4 is formed on the surface of a silicon substrate 1 having extremely fine irregularities as shown in FIG. 4, and then a polysilicon film 5 is deposited. , is a diagram showing that a capacitor with increased capacitance per unit projected area is obtained by using a silicon substrate 1 and a polysilicon film 5 as electrodes.
以上の説明では、簡単なため省略したが、実際
のICでは、以下の如き工程を経るのが普通であ
る。すなわち、凹凸を付ける必要のない部分に
は、例えば第１図の状態のときに、写真製版法で
フオト・レジストで覆う工程を入れることや、ま
た、シリコン基板１の表面にこのシリコン基板１
と同じ伝導型または反対の伝導型の拡散層、エピ
タキシヤル層等を第４図の状態のとき、また第１
図の熱酸化膜２を付着させる前に、形成する工程
を入れることや、第５図のポリシリコン膜５に不
純物を拡散したシート抵抗させる工程を入れるこ
と等はいうまでもない。 Although omitted in the above explanation for simplicity, actual ICs usually go through the following steps. That is, for example, in the case where there is no need to create irregularities, a step of covering the surface with a photoresist using a photolithography method may be added to the surface of the silicon substrate 1 in the state shown in FIG.
When the diffusion layer, epitaxial layer, etc. of the same conductivity type or the opposite conductivity type are in the state shown in Figure 4, and
It goes without saying that before the thermal oxide film 2 shown in the figure is deposited, a step of forming it and a step of forming a sheet resistor by diffusing impurities into the polysilicon film 5 shown in FIG. 5 are added.
以上は基板と同じ材質の薄い島状構造の薄膜を
マスクとする場合について述べたが、異なる材
質、例えば金、アルミニウム等の金属や、他の半
導体材料、絶縁材料等を用いても同様のことが実
現できることはいうまでもない。また、島状構造
の薄膜の形状を写しとるための膜としては熱酸化
膜以外にも、数100Å程度の薄さでも一様な厚み
を保証するものでシリコンに対してマスク効果の
あるものであれば良く、例えば熱窒化膜であつて
もよい。 The above describes the case where a thin island-shaped thin film made of the same material as the substrate is used as a mask, but the same effect can be obtained using a different material, such as metals such as gold and aluminum, other semiconductor materials, insulating materials, etc. It goes without saying that this can be achieved. In addition to thermal oxide films, there are also films that can be used to copy the shape of thin films with island-like structures, which guarantee a uniform thickness even at a thickness of several hundred angstroms and have a masking effect on silicon. For example, it may be a thermal nitride film.
また、上記の島状構造の薄膜が、シリコンに対
してマスクとなる材質の場合、島状構造の薄膜を
シリコン基板に直接に付着させ、そのままシリコ
ン基板をエツチングすることでも、この方法によ
つても、ほぼ第４図の構造を実現できる。しか
し、この場合には、実施例で述べたアンダー・カ
ツテイングにより抜き残しの比率を制御すること
ができないので、効率の良い面積増加は望めな
い。 In addition, if the thin film with the island-like structure described above is a material that acts as a mask for silicon, this method can also be used by directly attaching the thin film with the island-like structure to the silicon substrate and etching the silicon substrate as it is. Also, almost the structure shown in FIG. 4 can be realized. However, in this case, it is not possible to control the ratio of uncut parts due to the under-cutting described in the embodiment, and therefore an efficient increase in area cannot be expected.
以上のように、本発明によればマスクに島状構
造の薄膜を利用するので、不規則ではあるが平均
的な凹部の幅間隔を数100〜数1000Åといつた短
い長さにすることができ、凹部の深さも数100〜
数1000Å程度であるから、凹凸による充分な面積
増加を図ることができる効果がある。 As described above, according to the present invention, since a thin film with an island-like structure is used in the mask, the average width interval of the recesses can be made short, although irregular, from several hundred to several thousand angstroms. The depth of the recess is several 100~
Since the thickness is approximately several thousand angstroms, it has the effect of sufficiently increasing the area due to the unevenness.
第１〜４図は本発明の一実施例の主要工程を示
す断面図、第５図は本発明の方法を用いたコンデ
ンサの断面図である。
図において、１はシリコン基板、２は熱酸化
膜、３は島状構造のポリシリコン膜、４は熱酸化
膜、５はポリシリコン膜である。なお、図中同一
符号はそれぞれ同一または相当部分を示す。
1 to 4 are cross-sectional views showing the main steps of an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a capacitor using the method of the present invention. In the figure, 1 is a silicon substrate, 2 is a thermal oxide film, 3 is an island-like polysilicon film, 4 is a thermal oxide film, and 5 is a polysilicon film. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
薄膜を基板上に付着させる工程、および島状構造
の上記薄膜をマスクにして上記基板を食刻しその
表面部に多数の微細な凹凸を形成する工程を備え
たことを特徴とする半導体集積回路装置の製造方
法。 ２ 基板上にほぼ一様な厚さの第１の薄膜を形成
する工程、多数の微細な島状構造を形成する程度
に薄い第２の薄膜を上記第１の薄膜の表面上に付
着させる工程、島状構造の上記第２の薄膜をマス
クにして上記第１の薄膜を食刻し多数の微細な開
口部を形成する工程、および上記開口部が形成さ
れた上記第１の薄膜をマスクにして上記基板を食
刻しその表面部に多数の微細な凹凸を形成する工
程を備えたことを特徴とする半導体集積回路装置
の製造方法。[Claims] 1. A step of depositing a thin film on a substrate so thin as to form a large number of fine island-like structures, and etching the substrate using the thin film of the island-like structure as a mask to etching the surface portion thereof. 1. A method of manufacturing a semiconductor integrated circuit device, comprising a step of forming a large number of fine irregularities on a semiconductor integrated circuit device. 2. Forming a first thin film with a substantially uniform thickness on the substrate, and depositing a second thin film thin enough to form a large number of fine island-like structures on the surface of the first thin film. , etching the first thin film using the second thin film having an island-like structure as a mask to form a large number of minute openings; and using the first thin film in which the openings are formed as a mask. A method for manufacturing a semiconductor integrated circuit device, comprising the step of etching the substrate to form a large number of fine irregularities on the surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14493182A JPS5934652A (en) | 1982-08-20 | 1982-08-20 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14493182A JPS5934652A (en) | 1982-08-20 | 1982-08-20 | Manufacture of semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5934652A JPS5934652A (en) | 1984-02-25 |
| JPH0138376B2 true JPH0138376B2 (en) | 1989-08-14 |
Family
ID=15373527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14493182A Granted JPS5934652A (en) | 1982-08-20 | 1982-08-20 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5934652A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100588737B1 (en) | 2004-12-30 | 2006-06-12 | 매그나칩 반도체 유한회사 | Semiconductor device and method for fabricating the same |
-
1982
- 1982-08-20 JP JP14493182A patent/JPS5934652A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5934652A (en) | 1984-02-25 |
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