JPH01321716A - Active filter - Google Patents

Abstract

PURPOSE:To obtain the function of a multi-input active filter without specially preparing an adder and an inverter by connecting plural input terminals to resistance elements respectively and adding voltages of input signals supplied to respective input terminals after weighting them. CONSTITUTION:This active filter consists of plural resistance elements r1 and r2 connected between plural input terminals and a common node, an operational amplifier A1 which has a prescribed gain and has the negative phase input terminal connected to a reference voltage end, a capacity element C1 connected between the positive phase input terminal of the operational amplifier A1 and the common node, a resistance element R2 connected between the common node and the output of the operational amplifier A1, and a capacity element C2 and a resistance element R3 which are connected between the positive phase input terminal of the operational amplifier A1 and the reference voltage end and are connected in parallel. When r1=r2=R2=R3=R and K=4 are true, input signals V1 and V2 are simply added, and 0dB transmission in the band is possible.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は能動フィルタに関し、特に複数の入力端子をも
ち帯域通過特性を備えた能動フィルタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active filter, and more particularly to an active filter having a plurality of input terminals and having bandpass characteristics.

〔従来の技術〕[Conventional technology]

従来、帯域通過特性を有する能動フィルタとしては、第
３図に示されているシャーレン・キー・フィルタが知ら
れている。図において、■１は入力端子、ｖｏは出力端
子、Ｒ１、凡２　、Ｒ３は抵抗素子％　０１　１　Ｃ２
は容ｆｒ素子、Ａ菫は利得にの演算増幅器をそれぞれ示
している。このフィルタは唯一の入力端子に供給される
入力信号Ｖｉに対し、久の式で示される伝達特性に従う
九出力信号ｖｏが得られる。Conventionally, a Schalen-Key filter shown in FIG. 3 has been known as an active filter having bandpass characteristics. In the figure, ■1 is an input terminal, vo is an output terminal, R1, 2, and R3 are resistive elements % 01 1 C2
1A and 2B respectively indicate an FR element and an operational amplifier for gain. With respect to an input signal Vi supplied to only one input terminal of this filter, nine output signals vo are obtained in accordance with the transfer characteristic expressed by the following equation.

ここで、Ｒ１＝几２＝几３＝ＪＫ＝ｌとすればｅ”１ｓ
ａｏは次式のようになる。Here, if R1=几2=几3=JK=l, then e"1s
ao is expressed as follows.

これは、ａｏｓａｌによシ極を作シ、更に分子が定数で
あるので、有限な伝送零点を有しない帯域通過フィルタ
となる。This creates a polarity due to the aosal, and since the numerator is a constant, it becomes a bandpass filter with no finite transmission zero.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の能動フィルタでは、入力端子が１個に限
られていたので１例えば２人力ｔ−加算した後に能動フ
ィルタを通したい場合には、別途加算器を準備しなけれ
ばならなかった。この加算器としては、第４図で示され
ている構成となっている０図において、ｖｌ、ｖ２は第
１及び第２の入力端子、ｒｌ、ｒ２．几４は抵抗素子、
Ａ２は演算増幅器、■ｏは出力信号をそれぞれ示してい
る。In the conventional active filter described above, the number of input terminals is limited to one, so if it is desired to pass through the active filter after 1, for example, 2 manual t-additions, a separate adder must be prepared. This adder has the configuration shown in FIG. 4, in which vl, v2 are first and second input terminals, rl, r2 .几4 is a resistance element,
A2 represents an operational amplifier, and ■o represents an output signal.

この演算増幅器Ａ２の負荷駆動能力を低下させる九めに
抵抗素子の抵抗値を大きく設定すると、集積化するとき
に広いチップ面積を必要とする。If the resistance value of the resistor element is set to a large value, which reduces the load driving ability of the operational amplifier A2, a large chip area is required for integration.

更に、第４図の加算器は加算結果の符号が反転と演算増
幅器Ａ３とで構成される。これらの加算器２反転器とと
もに能動フィルタを集積化すると、チップ面積が広大に
なシ、集積化が困難になるという問題点があった。Further, the adder shown in FIG. 4 is constructed by inverting the sign of the addition result and by an operational amplifier A3. When an active filter is integrated with these adders and two inverters, there is a problem that the chip area becomes large and integration becomes difficult.

本発明の目的は、これらの問題を解決し、複数入力端子
を有しながら集積化に適した能動フィルタを提供するこ
とにある。An object of the present invention is to solve these problems and provide an active filter that has multiple input terminals and is suitable for integration.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の構成は、複数の入力端子と共通ノードとの間に
それぞれ接続された複数の抵抗素子と、所定の利得を有
し逆相入力端が基準電圧端に接続され比演算増幅器と、
この演算力’ＭＡ　Ｄの正相入力端と前記共通ノードと
の間に接続された容量素子と、前記共通ノードとの前記
演算増幅器の出力との間に接続された抵抗素子と、前記
演算増幅器の正相入力端と前記基準電圧端との間に接続
され並列接続された容量素子および抵抗素子とを備えた
ことｔ−特徴とする。The configuration of the present invention includes a plurality of resistive elements each connected between a plurality of input terminals and a common node, a ratio operational amplifier having a predetermined gain and having a negative phase input terminal connected to a reference voltage terminal;
a capacitive element connected between the positive phase input terminal of this operational power 'MAD and the common node; a resistive element connected between the common node and the output of the operational amplifier; It is characterized by comprising a capacitive element and a resistive element connected in parallel between the positive phase input terminal of the terminal and the reference voltage terminal.

〔実施例〕〔Example〕

以下９本発明の実施例を図面を参照して説明する。 Hereinafter, nine embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例の構成を示す回路図であ
る。図中、ｖｌ　、■雪は第１及び第２の入力端子に供
給される入力信号、■ｏは出力信号、ｒｌ　　＊ｒ！　
　、ａ、ｔ”３は抵抗素子ｅ　”１　　＊　Ｃ２は容量
素子、Ａは演算増幅器をそれぞれ示している。FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention. In the figure, vl, ■Snow is the input signal supplied to the first and second input terminals, ■o is the output signal, rl *r!
, a, t"3 are resistive elements, e"1*C2 are capacitive elements, and A is an operational amplifier, respectively.

本実施例の伝達特性は次式で示される。The transfer characteristic of this embodiment is expressed by the following equation.

特に、ｒｌ　＝ｒ、　＝ａ、　＝）ｉ３＝几、に＝４と
すればｅａｌｅａｏは次式のようになる。In particular, if rl=r, =a, =)i3=几, and ni=4, ealeao becomes as follows.

−３ｃ１Ｂ、　＋　５ｃ１Ｒ２ ａ　ｌ　　＝　　　　　　　　　　　　　　　　　　ａ
　Ｑ　＝Ｃ１Ｃ２ＲｅｌＣ，几２ この時、入力信号Ｖ、、Ｖ、とは単純加算となシ、帯域
内でのＱｄＢ伝送が可能になる。-3c1B, +5c1R2 a l = a
Q = C1C2RelC, 几2 At this time, the input signals V, , V are simply added, and QdB transmission within the band becomes possible.

第２図は本発明の第２の実施例の構成を示す回路図で、
３入力端子の能動フィルタを示し、ＶｌｅＶ、、Ｖ３は
第１．第２及び第３の入力端子に供給される入力端子で
ある。’１　　ｅ　ｒ２１　’ｓ　　ｅ”Ｑ　ｅＲ３は
抵抗素子、Ｃ１、Ｃ，は容量素子、Ａ１は演算増幅器を
それぞれ示している。この場合は、第１の実施例に対し
、第３の入力端子Ｖ９とその人力抵抗素子ｒ３が付加さ
れた以外は第１の実施例と同じである。FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention.
It shows an active filter with 3 input terminals, where VleV, , V3 are the first . It is an input terminal that is supplied to the second and third input terminals. '1 e r21 'se'Q eR3 indicates a resistive element, C1, C, and capacitive elements, and A1 indicates an operational amplifier.In this case, in contrast to the first embodiment, the third input terminal V9 This embodiment is the same as the first embodiment except that the human resistance element r3 is added.

〔発明の効果〕〔Effect of the invention〕

以上説明して春たよりに７本発明によれば、複数の入力
端子に抵抗素子をそれぞれ接続しておシ、各入力端子に
供給される人力信号の電圧に重み付けを与えた上で加算
することができる。従って加算器２反転器を別途用意し
なくとも、多入力の能動フィルタとして機能させること
ができ、集積化時にチップ面積を減少させることができ
るという効果が得られる。According to the present invention, resistance elements are connected to each of a plurality of input terminals, and the voltages of human input signals supplied to each input terminal are weighted and then added. I can do it. Therefore, it is possible to function as a multi-input active filter without separately preparing an adder 2 inverter, and it is possible to achieve the effect that the chip area can be reduced during integration.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図は本発明の第１および第２の実施例の構
成を示す回路図、第３図は従来の能動フィルタの構成を
示す回路図、第４図、第５図は従来の加算器および反転
器の構成を示す回路図である。 Ａ！〜Ａ、・・・・・・演算増幅器、（’１　　＊　Ｃ
２・・・・・・容量素子、ｒｌ　　、　ｒ２　　、　ｒ
ｌ　、　Ｒ１ｘＲ６−・−抵抗素子、■１〜Ｖ３・・・
・・・入力端子、■ｏ・・・・・・出力端子。 代理人　弁理士　　内　原　　　晋 第１図 第Ｚ図1 and 2 are circuit diagrams showing the configurations of the first and second embodiments of the present invention, FIG. 3 is a circuit diagram showing the configuration of a conventional active filter, and FIGS. 4 and 5 are circuit diagrams showing the configuration of a conventional active filter. FIG. 2 is a circuit diagram showing the configuration of an adder and an inverter. A! ~A, ...... operational amplifier, ('1 * C
2...Capacitive element, rl, r2, r
l, R1xR6--resistance element, ■1~V3...
...Input terminal, ■o...Output terminal. Agent: Susumu Uchihara, Patent Attorney Figure 1, Figure Z

Claims (1)

【特許請求の範囲】[Claims] 複数の入力端子と共通ノードとの間にそれぞれ接続され
た複数の抵抗素子と、所定の利得を有し逆相入力端が基
準電圧端に接続された演算増幅器と、この演算増幅器の
正相入力端と前記共通ノードとの間に接続された容量素
子と、前記共通ノードと前記演算増幅器の出力との間に
接続された抵抗素子と、前記演算増幅器の正相入力端と
前記基準電圧端との間に接続され並列接続された容量素
子および抵抗素子とを備えたことを特徴とする能動フィ
ルタ。A plurality of resistive elements each connected between a plurality of input terminals and a common node, an operational amplifier having a predetermined gain and whose negative phase input terminal is connected to a reference voltage terminal, and a positive phase input of this operational amplifier. a capacitive element connected between the terminal and the common node; a resistive element connected between the common node and the output of the operational amplifier; and a positive-phase input terminal of the operational amplifier and the reference voltage terminal. What is claimed is: 1. An active filter comprising: a capacitive element and a resistive element connected in parallel;