JPH01309380A - Insulated-gate type semiconductor device - Google Patents
Insulated-gate type semiconductor deviceInfo
- Publication number
- JPH01309380A JPH01309380A JP63139264A JP13926488A JPH01309380A JP H01309380 A JPH01309380 A JP H01309380A JP 63139264 A JP63139264 A JP 63139264A JP 13926488 A JP13926488 A JP 13926488A JP H01309380 A JPH01309380 A JP H01309380A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulated gate
- gate insulating
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 15
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- -1 neobium oxide Chemical compound 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 239000002131 composite material Substances 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電力用絶縁ゲート形半導体装置に係り特に低損
失でかつ高信頼性を得るのに好適な絶縁ゲート形半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate type semiconductor device for power use, and particularly to an insulated gate type semiconductor device suitable for achieving low loss and high reliability.
一般にＭＯＳＦＥＴのゲート絶縁膜材料としては、シリ
コン酸化膜が用いられている。縦形構造を有する電力用
（以下パワーと称する） ＭＯＳＦＥＴの場合にも、特
公昭６０−４１８７６号に記載のように、ゲート絶縁膜
にはシリコン酸化膜が用いられていた。−方、特願昭６
１−２６９６５９号に記載のように、半導体装置のキャ
パシタ用絶縁膜として高誘電体膜たとえば酸化タンタル
膜が使用れていた。また、特開昭５３−１１３４８号に
記載のように、横形構造の微細ＭＯ８ＦＥＴに酸化タン
タル膜が用いられた例がある。Generally, a silicon oxide film is used as a gate insulating film material of a MOSFET. Even in the case of a power MOSFET having a vertical structure (hereinafter referred to as "power"), a silicon oxide film has been used as the gate insulating film, as described in Japanese Patent Publication No. 41876/1983. - way, special request 6th year
As described in No. 1-269659, a high dielectric constant film such as a tantalum oxide film has been used as an insulating film for a capacitor of a semiconductor device. Furthermore, as described in JP-A-53-11348, there is an example in which a tantalum oxide film is used in a fine MO8FET having a horizontal structure.
上記従来技術は、縦形パワーＭＯ５ＦＥＴのゲート絶縁
膜材料として、キャパシタ用として高信頼性を有する酸
化タンタルのような高誘電体膜を用いる点について配慮
されておらず、特にゲート面積の大きな場合、ゲート耐
圧の歩留り及び信頼性が低下するという問題があった。The above conventional technology does not consider the use of a high dielectric constant film such as tantalum oxide, which has high reliability for capacitors, as the gate insulating film material of the vertical power MO5FET. There was a problem in that the yield and reliability of withstand voltage decreased.
なお、横形構造の微細ＭＯ３ＦＥＴに酸化タンタル膜が
用いられた例はあるが、この構造ではゲート面積が小さ
く、ゲート耐圧の歩留り及び信頼性に関して配慮されて
いなかった。Although there is an example of using a tantalum oxide film in a horizontally structured fine MO3FET, this structure has a small gate area and no consideration has been given to the yield and reliability of the gate breakdown voltage.
本発明の目的は、縦形パワーＭＯ３ＦＥＴのゲート耐圧
歩留り及び信頼性を向上することにある。An object of the present invention is to improve the gate breakdown voltage yield and reliability of a vertical power MO3FET.
上記目的は、縦形パワーＭＯ５ＦＥＴのゲート絶縁膜と
して、例えば酸化タンタル膜とシリコン酸化膜との複合
膜のような誘電率の異なる複合膜を用いることにより達
成される。The above object is achieved by using a composite film having different dielectric constants, such as a composite film of a tantalum oxide film and a silicon oxide film, as the gate insulating film of the vertical power MO5FET.
縦形パワーＭＯ３ＦＥＴのゲート面積が大きいので、ゲ
ート絶縁膜の欠陥が、ゲート耐圧歩留り及び信頼性に対
して大きな影響を及ぼす。Since the gate area of the vertical power MO3FET is large, defects in the gate insulating film have a large effect on the gate breakdown voltage yield and reliability.
ゲート絶縁膜として用いた酸化タンタル膜とシリコン酸
化膜との複合膜は、従来のシリコン酸化膜の単層膜に比
べて、等測的に誘電率が高くとれるので、電気的時性を
低下させないで厚膜化でき、欠陥の発生確率の低減に著
しい効果を有する。それによって、ゲート耐圧歩留り及
び信頼性が著しく向上する。The composite film of tantalum oxide and silicon oxide used as the gate insulating film has an isometrically higher dielectric constant than the conventional single-layer silicon oxide film, so it does not reduce the electrical time characteristic. The film can be made thicker, and has a remarkable effect on reducing the probability of defect occurrence. This significantly improves gate breakdown voltage yield and reliability.
以下、本発明の一実施例を第１図により説明する。第１
図は、縦形パワーＭＯ５ＦＥＴの主要部セル部の断面構
造図である。１は抵抗率が０．０１Ω・■のｎ形高濃度
半墓体基板、２は抵抗率が、０．８Ω・国、厚さが１０
μｍのｎ形エピタキシャル層からなるドレイン領域、３
はシート抵抗が５００Ω／口、深さが２．５μｍのｐ形
ベース領域、４は、シート抵抗が２０Ω／口、深さが０
．５μｍのｎ形高濃度ソース領域、５は厚さが２５Ωｍ
のシリコン酸化膜、６は厚さが３５Ωｍの酸化タンタル
膜、７は厚さが５Ωｍの窒化シリコン膜、８は厚さが０
．３μｍの多結晶シリコンからなるゲート電極、９は厚
さが０．６μｍのリンガラスからなる安定化保護膜、１
０は厚さが３μｍのアルミニウム膜、１１は樹脂系絶縁
膜、そして１２は厚さが２μｍの金Ｊ７ｆｔ膜からなる
ドレイン電極である。本構造の特徴は、ゲート絶縁膜が
、シリコン酸化膜、酸化タンタル膜および窒化シリコン
膜から成る複合膜で構成されていることであり、またそ
のゲート絶縁膜の下に低濃度ドレイン領域を有すること
である。An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a cross-sectional structural diagram of the main cell part of a vertical power MO5FET. 1 is an n-type high-concentration semicircular substrate with a resistivity of 0.01Ω・■, 2 is a resistivity of 0.8Ω・2, and a thickness of 10
Drain region consisting of an n-type epitaxial layer of μm, 3
4 has a p-type base region with a sheet resistance of 500 Ω/hole and a depth of 2.5 μm, and 4 has a sheet resistance of 20 Ω/hole and a depth of 0.
．． 5μm n-type high concentration source region, 5 has a thickness of 25Ωm
6 is a tantalum oxide film with a thickness of 35 Ωm, 7 is a silicon nitride film with a thickness of 5 Ωm, 8 is a thickness of 0
．． A gate electrode made of polycrystalline silicon with a thickness of 3 μm, 9 a stabilizing protective film made of phosphorus glass with a thickness of 0.6 μm, 1
0 is a drain electrode made of an aluminum film with a thickness of 3 μm, 11 is a resin-based insulating film, and 12 is a gold J7ft film with a thickness of 2 μm. The feature of this structure is that the gate insulating film is composed of a composite film consisting of a silicon oxide film, a tantalum oxide film, and a silicon nitride film, and that it has a low concentration drain region under the gate insulating film. It is.
本実施例によれば、３．５ｍ角チップパワーＭＯ３ＦＥ
Ｔにおいて、ドレイン耐圧６０Ｖ、オン抵抗３０ｍΩ、
ゲート耐圧３０Ｖが得られた。このデバイスは、従来の
厚さ３５Ωｍのシリコン酸化膜からなるゲート絶ｇ膜を
有するパワーＭＯ８ＦＥＴに比べてゲート耐圧の歩留り
が約２０％向上でき、また、ゲート電界加速試験におい
ても不良発生率が格段に減少した。According to this embodiment, the 3.5m square chip power MO3FE
At T, drain breakdown voltage 60V, on resistance 30mΩ,
A gate breakdown voltage of 30V was obtained. This device can improve the gate breakdown voltage yield by about 20% compared to the conventional power MO8FET with a gate isolation film made of a silicon oxide film with a thickness of 35 Ωm, and also has a significantly lower failure rate in gate electric field acceleration tests. decreased to
次に、本発明の他の実施例を第２図により説明する。第
２図は、Ｕ溝を有する縦形パワーＭＯ３ＦＥＴの主要部
の断面構造図である。本構造では、ｐ形ベース領域３お
よびｎ形ベース領域４を形成後に、ゲート絶縁膜５，６
．７を形成している。従って、ゲート絶縁膜形成後に、
例えばベース拡散などの高温熱処理工程を入れる必要が
ない。また、図に示したように、ゲート領域がＵ溝をし
ている場合には、ゲート絶縁膜を均一な厚さに保つこと
は難しく、その絶′Ｒ膜が薄い場合には、ピンホールな
どを生じやすいので、その面からも膜厚を大とする必要
がある６本構造ではシリコン酸化膜５の厚さを１５ｎｍ
、酸化タンタル膜６の厚さを３５ｎｍ、窒化シリコン膜
７の厚さを５ｎｍとした。またＵ溝の幅を３μｍとした
。他のパラメータは、第１図とほぼ同一の条件に設定し
た。Next, another embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional structural diagram of the main part of a vertical power MO3FET having a U-groove. In this structure, after forming the p-type base region 3 and the n-type base region 4, the gate insulating films 5 and 6 are
．． 7 is formed. Therefore, after forming the gate insulating film,
For example, there is no need to include a high temperature heat treatment process such as base diffusion. In addition, as shown in the figure, if the gate region has a U-groove, it is difficult to maintain a uniform thickness of the gate insulating film, and if the insulating film is thin, pinholes may occur. In the six-layer structure, the thickness of the silicon oxide film 5 is set to 15 nm.
The thickness of the tantalum oxide film 6 was 35 nm, and the thickness of the silicon nitride film 7 was 5 nm. Further, the width of the U groove was set to 3 μm. Other parameters were set to almost the same conditions as in FIG.
本実施例によれば、３．５ｍｍ角チツプのパワーＭＯ５
ＦＥＴにおいて、ドレイン耐圧４５Ｖ、オン抵抗２０ｍ
Ω、ゲート耐圧２５Ｖが得られた。このデバイスは、従
来の厚さ３０ｎｍのシリコン酸化膜とゲート絶縁膜とす
るパワーＭＯ３ＦＥＴに比べて、ゲート耐圧歩留りが３
０％も向上できた。According to this embodiment, the power MO5 of the 3.5 mm square chip is
In FET, drain breakdown voltage 45V, on resistance 20m
Ω, and a gate breakdown voltage of 25V was obtained. This device has a gate breakdown voltage yield of 3% compared to a conventional power MO3FET that uses a 30 nm thick silicon oxide film and a gate insulating film.
I was able to improve by 0%.
次に、本発明の他の実施例を第３図および第４図により
説明する。第３図は、パワーＩＣの平面配置図、第４図
はそのＩＣの主要部の断面構造図である。ここで、１０
１はパワーＭＯ８ＦＩＥＴが配置されている領域、１０
２，１０３は、ＭＯＳＦＥＴや抵抗やキャパシタから成
るドライブＩＣ，論理ＩＣが配置されている領域である
。さらに、ドライブＩＣ１０２には、過電圧、低電圧、
過電流及び温度上昇に対する保護回路が含まれている。Next, another embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan layout diagram of the power IC, and FIG. 4 is a sectional structural diagram of the main parts of the IC. Here, 10
1 is the area where the power MO8FIET is placed, 10
Reference numeral 2 and 103 are areas in which drive ICs and logic ICs made up of MOSFETs, resistors, and capacitors are arranged. Furthermore, the drive IC 102 has overvoltage, undervoltage,
Contains protection circuits against overcurrent and temperature rise.
本構造の特徴は、パワーＭＯ３ＦＥＴ部とＭＯＳＦＥＴ
部のゲート絶縁膜及びキャパシタの絶縁膜が５のシリコ
ン酸化膜、６の酸化タンタル膜、７の窒化シリコン膜よ
り成っていることである。これにより、ＭＯＳＦＥＴの
ゲート絶縁膜とキャパシタの絶、Ｉ？１′膜とを別々に
製作する従来の構造に比べて工程の簡略化が図れる。The features of this structure are the power MO3FET section and MOSFET
The gate insulating film of the part and the insulating film of the capacitor are made of a silicon oxide film (5), a tantalum oxide film (6), and a silicon nitride film (7). As a result, the gate insulating film of the MOSFET and the capacitor are disconnected, I? Compared to the conventional structure in which the 1' film and the 1' film are manufactured separately, the process can be simplified.
以上の実施例では、ゲート電極として、多結晶シリコン
について述べたが、他の材料、例えば、アルミニウム、
アルミニウム合金、タングステン。In the above embodiments, polycrystalline silicon was used as the gate electrode, but other materials such as aluminum,
Aluminum alloy, tungsten.
モリブデン、タングステン・トリサイド、モリブデン・
シリサイドおよびチタン・シリサイドでも同様な効果が
認められた。molybdenum, tungsten triside, molybdenum
Similar effects were observed with silicide and titanium silicide.
さらに、高誘電体膜として、酸化タンタルの実施例を示
したが、他の材料である酸化チタン、酸化ハフニウム、
酸化ネオビウムおよび酸化ジルコニウムでも本発明の思
想を逸脱しない限りにおいて変更可能である。Furthermore, although an example of tantalum oxide was shown as a high dielectric film, other materials such as titanium oxide, hafnium oxide,
Changes can also be made to neobium oxide and zirconium oxide without departing from the spirit of the present invention.
第１図は本発明の一実施例の縦形パワーＭＯ３ＦＥＴの
主要部の縦断面図、第２図は本発明の他の実施例の溝碑
造縦形パワーＭＯ５ＦＥＴの主要部の縦断面図。
第３図は本発明の他の実施例のパワーＭＯ３ＩＣの＼Ｖ
面配置図、第４図は第３図の主要部の縦断面図である。
１・・・高濃度半導体基板、２・・・ｎ形ドレイン領域
。
３・・・ｐ形ベース領域、４・・・ｎ形ソース領域、５
・・・シリコン酸化膜、６・・・酸化タンタル膜、７・
・・窒化シリコン膜、８・・・ゲート電極、１ｏ・・・
ソース電極。
ＡＯ７−
Ｉ７・・ヤヤｌずシタｔ′弔νFIG. 1 is a longitudinal sectional view of the main part of a vertical power MO3FET according to an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of the main part of a groove-shaped vertical power MO5FET according to another embodiment of the invention. Figure 3 shows \V of a power MO3IC according to another embodiment of the present invention.
4 is a vertical sectional view of the main part of FIG. 3. 1... High concentration semiconductor substrate, 2... N-type drain region. 3...p-type base region, 4...n-type source region, 5
... silicon oxide film, 6... tantalum oxide film, 7.
...Silicon nitride film, 8...Gate electrode, 1o...
source electrode. AO7- I7... Yayalzu Shitat'condolenceν
Claims (1)
、それを含む集積回路装置において、上記絶縁ゲート膜
の材料が、シリコン酸化膜よりも誘電率の大きな高誘電
体膜とシリコン酸化膜とを含むことを特徴とする絶縁ゲ
ート形半導体装置。 ２、特許請求の範囲第１項において、電力用絶縁ゲート
形電界効果トランジスタの構造が、低濃度ドレイン領域
を表面に有する縦形であることを特徴とする絶縁ゲート
形半導体装置。 ３、特許請求の範囲第１項において、電力用絶縁ゲート
形電界効果トランジスタのチャネル部が溝領域内に形成
されていることを特徴とする絶縁ゲート形半導体装置。 ４、特許請求の範囲第１項において、絶縁ゲート膜とキ
ャパシタ膜とが同一の断面組成をしていることを特徴と
する絶縁ゲート形半導体装置。 ５、特許請求の範囲第１項において、ゲート電極が多結
晶シリコン、アルミニウム、アルミニウム合金、タング
ステン、モリブデン、タングステン・シリサイド、モリ
ブデン・シリサイドおよびチタン・トリサイドなる群か
ら選ばれた材料の膜であることを特徴とする絶縁ゲート
形半導体装置。 ６、特許請求の範囲第１項において、高誘電体膜が酸化
タンタル、酸化チタン、酸化ハフニウム、酸化ネオビウ
ムおよび酸化ジルコニウムからなる群から選ばれた材料
の膜であることを特徴とする絶縁ゲート形半導体装置。[Claims] 1. In an insulated gate field effect transistor for power use or an integrated circuit device including the same, the material of the insulated gate film is a high dielectric constant film having a higher dielectric constant than a silicon oxide film, and a silicon oxide film. An insulated gate type semiconductor device comprising a film. 2. An insulated gate semiconductor device according to claim 1, wherein the power insulated gate field effect transistor has a vertical structure having a lightly doped drain region on its surface. 3. An insulated gate type semiconductor device according to claim 1, wherein a channel portion of a power insulated gate field effect transistor is formed within a trench region. 4. The insulated gate type semiconductor device according to claim 1, wherein the insulated gate film and the capacitor film have the same cross-sectional composition. 5. In claim 1, the gate electrode is a film of a material selected from the group consisting of polycrystalline silicon, aluminum, aluminum alloy, tungsten, molybdenum, tungsten silicide, molybdenum silicide, and titanium tricide. An insulated gate semiconductor device characterized by: 6. The insulated gate type according to claim 1, characterized in that the high dielectric film is a film made of a material selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, neobium oxide, and zirconium oxide. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63139264A JPH01309380A (en) | 1988-06-08 | 1988-06-08 | Insulated-gate type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63139264A JPH01309380A (en) | 1988-06-08 | 1988-06-08 | Insulated-gate type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01309380A true JPH01309380A (en) | 1989-12-13 |
Family
ID=15241235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63139264A Pending JPH01309380A (en) | 1988-06-08 | 1988-06-08 | Insulated-gate type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01309380A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0594177A1 (en) * | 1992-10-22 | 1994-04-27 | Kabushiki Kaisha Toshiba | Vertical MOSFET having trench covered with multilayer gate film |
| KR100304717B1 (en) * | 1998-08-18 | 2001-11-15 | 김덕중 | Semiconductor device having a trench type gate and method for fabricating therefor |
| JP2008187147A (en) * | 2007-01-31 | 2008-08-14 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method of the same |
| US8383490B2 (en) | 2011-07-27 | 2013-02-26 | International Business Machines Corporation | Borderless contact for ultra-thin body devices |
| JP2013055349A (en) * | 2012-11-12 | 2013-03-21 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN106033776A (en) * | 2015-03-18 | 2016-10-19 | 北大方正集团有限公司 | Manufacturing method of VDMOS device and the VDMOS device |
-
1988
- 1988-06-08 JP JP63139264A patent/JPH01309380A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0594177A1 (en) * | 1992-10-22 | 1994-04-27 | Kabushiki Kaisha Toshiba | Vertical MOSFET having trench covered with multilayer gate film |
| CN1035142C (en) * | 1992-10-22 | 1997-06-11 | 株式会社东芝 | Semiconductor unit |
| KR100304717B1 (en) * | 1998-08-18 | 2001-11-15 | 김덕중 | Semiconductor device having a trench type gate and method for fabricating therefor |
| JP2008187147A (en) * | 2007-01-31 | 2008-08-14 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method of the same |
| US8383490B2 (en) | 2011-07-27 | 2013-02-26 | International Business Machines Corporation | Borderless contact for ultra-thin body devices |
| US9024389B2 (en) | 2011-07-27 | 2015-05-05 | International Business Machines Corporation | Borderless contact for ultra-thin body devices |
| JP2013055349A (en) * | 2012-11-12 | 2013-03-21 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN106033776A (en) * | 2015-03-18 | 2016-10-19 | 北大方正集团有限公司 | Manufacturing method of VDMOS device and the VDMOS device |
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