JPH01304779A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPH01304779A JPH01304779A JP63135971A JP13597188A JPH01304779A JP H01304779 A JPH01304779 A JP H01304779A JP 63135971 A JP63135971 A JP 63135971A JP 13597188 A JP13597188 A JP 13597188A JP H01304779 A JPH01304779 A JP H01304779A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- trench
- isolation region
- trench isolation
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はＭＯＳ型半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a MOS type semiconductor device.
［従来の技術］
従来、ＭＯＳ型半導体装置の製造方法として溝掘り型素
子分離すなわち、トレンチ分離による素子分離を行なう
事や、溝掘り型ゲートすなわちトレンチ・ゲートを形成
する事等は各々独立に提案はされていた。[Prior Art] Conventionally, methods for manufacturing MOS semiconductor devices, such as performing element isolation by trench isolation, forming trench gates, etc., have been independently proposed. It had been worn.
［発明が解決しようとする課題１
しかし、上記従来技術によると、とりわけトレンチ・ゲ
ート構成のＭＯＳ型トランジスタを構成する場合に、ゲ
ート長方向の構成にはとりたてた課題はないが、ゲート
中方向の構成に、素子分離部との関係が不確かとなり、
ゲート中が定まらない等の課題があった。[Problem to be Solved by the Invention 1] However, according to the above-mentioned prior art, especially when configuring a MOS transistor with a trench gate configuration, there is no particular problem with the configuration in the gate length direction, but there is no problem with the configuration in the gate mid-direction. The relationship with the element isolation part becomes uncertain in the configuration.
There were issues such as not being able to determine the middle of the gate.
本発明は、かかる従来技術の課題を解決し、トレンチ・
ゲートを用いたＭＯＳ型半導体装置のゲート中を確かな
ものとする製造方法を提供する事を目的とする。The present invention solves the problems of the prior art and
It is an object of the present invention to provide a manufacturing method for making sure the inside of a gate of a MOS type semiconductor device using a gate.
〔課題を解決するための手段］
上記課題を解決するために、本発明は、ＭＯＳ型半導体
装置の製造方法に関し、半導体基板にトレンチ分離領域
を設け、該トレンチ分離領域に接して、トレンチ・ゲー
トを設ける手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a method for manufacturing a MOS type semiconductor device, in which a trench isolation region is provided in a semiconductor substrate, and a trench gate is provided in contact with the trench isolation region. Take measures to establish
〔実 施 例］
第１図は本発明の一実施例を示すトレンチ分離とトレン
チ・ゲートから成るＭＯＳ型ＦＥＴ（１ａ界効果トラン
ジスタ）の（ａ）平面図及び（ｂ）ゲート長方向断面図
、（ｃ）ゲート中方向断面図等の構造図である。すなわ
ち、Ｓｉ基板ｌの表面には、トレンチ分離領域としてト
レンチ分離Ｓ１０□２が形成され、該トレンチ分離領域
内に、トレンチ・ゲートのゲートＳｉ０ｇ膜３が形成さ
れると共に、該トレンチ・ゲート内を埋めた、Ｓｉゲー
ト電極４がフィールドＳｉ Ｏ２膜５の上まで形成され
て成り、該トレンチ・ゲートをゲート長方向（Ａ−Ａ′
）にはさんでソース及びドレインとなる拡散層６と、該
拡散層６からの引出し電極形成用のコンタクト穴７が形
成されて成る訳であるが、前記トレンチ・ゲートのＳｉ
ゲート電極４はゲート巾方向（Ｂ−Ｂ’ ）ではトレン
チ分離Ｓ１０ ｔに接して形成されて成る。[Embodiment] FIG. 1 shows (a) a plan view and (b) a sectional view in the gate length direction of a MOS type FET (1a field effect transistor) consisting of trench isolation and a trench gate, showing an embodiment of the present invention. (c) A structural diagram such as a sectional view in the direction of the gate. That is, a trench isolation S10□2 is formed as a trench isolation region on the surface of the Si substrate 1, and a gate Si0g film 3 of the trench gate is formed in the trench isolation region, and a gate Si0g film 3 of the trench gate is formed inside the trench gate. A buried Si gate electrode 4 is formed up to the top of the field SiO2 film 5, and the trench gate is aligned in the gate length direction (A-A'
), a diffusion layer 6 serving as a source and a drain, and a contact hole 7 for forming an extraction electrode from the diffusion layer 6 are formed.
The gate electrode 4 is formed in contact with the trench isolation S10t in the gate width direction (BB').
［発明の効果］
本発明の如（、トレンチ・ゲート型のＭＯＳＦＥＴをト
レンチ・分離と併合して形成する事により、ゲート中方
向の寸法が確かなものとなり、ＭＯ８型ＦＥＴの設計及
び製造が容易となる効果がある。[Effects of the Invention] By forming a trench-gate MOSFET by combining trench-isolation with the present invention, the dimension in the direction of the gate can be ensured, and the design and manufacture of MO8-type FETs are facilitated. This has the effect of
第１図（ａ）〜（ｃ）は本発明の一実施例を示す、トレ
ンチ分離・トレンチ・ゲートＭＯＳＦＥＴの構造図であ
る。
１・・・Ｓｉ基板
２・・・トレンチ分離Ｓｉｎ。
３・・・ゲートＳｉＯ□膜
４・・・Ｓｉゲート電極
５・・・フィールドＳ ｉ Ｏ２膜
６・・・拡散層
７・・・コンタクト穴
以上
出願人 セイコーエプソン株式会社FIGS. 1(a) to 1(c) are structural diagrams of a trench isolation/trench gate MOSFET showing one embodiment of the present invention. 1...Si substrate 2...Trench isolation Sin. 3...Gate SiO□ film 4...Si gate electrode 5...Field SiO2 film 6...Diffusion layer 7...Contact hole and above Applicant: Seiko Epson Corporation
Claims (1)
ンチ分離領域に接して、トレンチ・ゲートが設けられて
成る事を特徴とするＭＯＳ型半導体装置の製造方法。1. A method of manufacturing a MOS type semiconductor device, comprising: providing a trench isolation region in a semiconductor substrate; and providing a trench gate in contact with the trench isolation region.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63135971A JPH01304779A (en) | 1988-06-02 | 1988-06-02 | Manufacture of mos semiconductor device |
| KR1019890007221A KR0173111B1 (en) | 1988-06-02 | 1989-05-30 | Trench gate metal oxide semiconductor field effect transistor |
| US07/360,486 US5142640A (en) | 1988-06-02 | 1989-06-02 | Trench gate metal oxide semiconductor field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63135971A JPH01304779A (en) | 1988-06-02 | 1988-06-02 | Manufacture of mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01304779A true JPH01304779A (en) | 1989-12-08 |
Family
ID=15164145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63135971A Pending JPH01304779A (en) | 1988-06-02 | 1988-06-02 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01304779A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100468771B1 (en) * | 2002-10-10 | 2005-01-29 | 삼성전자주식회사 | Method for manufacturing MOS transistor |
| JP2008523611A (en) * | 2004-12-10 | 2008-07-03 | キョンブック ナショナル ユニバーシティ インダストリイ−アカデミック コーポレーション ファンデーション | Saddle type flash memory device and manufacturing method thereof |
| JP2008523610A (en) * | 2004-12-11 | 2008-07-03 | キョンブック ナショナル ユニバーシティ インダストリイ−アカデミック コーポレーション ファンデーション | Saddle type MOS element |
-
1988
- 1988-06-02 JP JP63135971A patent/JPH01304779A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100468771B1 (en) * | 2002-10-10 | 2005-01-29 | 삼성전자주식회사 | Method for manufacturing MOS transistor |
| JP2008523611A (en) * | 2004-12-10 | 2008-07-03 | キョンブック ナショナル ユニバーシティ インダストリイ−アカデミック コーポレーション ファンデーション | Saddle type flash memory device and manufacturing method thereof |
| JP2008523610A (en) * | 2004-12-11 | 2008-07-03 | キョンブック ナショナル ユニバーシティ インダストリイ−アカデミック コーポレーション ファンデーション | Saddle type MOS element |
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