JPH01303727A - Impurity gettering process - Google Patents
Impurity gettering processInfo
- Publication number
- JPH01303727A JPH01303727A JP13494188A JP13494188A JPH01303727A JP H01303727 A JPH01303727 A JP H01303727A JP 13494188 A JP13494188 A JP 13494188A JP 13494188 A JP13494188 A JP 13494188A JP H01303727 A JPH01303727 A JP H01303727A
- Authority
- JP
- Japan
- Prior art keywords
- gettering
- regions
- ion
- source
- insulating films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000005247 gettering Methods 0.000 title claims abstract description 24
- 239000012535 impurity Substances 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- -1 silicon ions Chemical class 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板の不純物ゲッタリングに関し、特
に、イオン注入を用いたゲッタリング法に関している。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to impurity gettering of a semiconductor substrate, and particularly to a gettering method using ion implantation.
従来、半導体基板のゲッタリング方法としては、サンド
ブラスト、レーザ光照射、イオン注入等による半導体基
板裏面への歪層の形成や、ＣＺシリコン単結晶中に含ま
れた過飽和の酸素が熱処理により内部欠陥としてシリコ
ン基板中に発生することを利用したイントリンシック・
ゲッタリング法がある。Conventional gettering methods for semiconductor substrates include forming a strained layer on the back surface of the semiconductor substrate by sandblasting, laser beam irradiation, ion implantation, etc., and removing supersaturated oxygen contained in the CZ silicon single crystal as internal defects through heat treatment. Intrinsic technology that utilizes the phenomenon that occurs in silicon substrates
There is a gettering method.
上述した従来のゲッタリング法は、素子形成前に、ゲッ
タリング処理を施すのが一般的である。In the conventional gettering method described above, gettering processing is generally performed before element formation.
その理由は、■裏面歪層ゲッタリング法においては、裏
面処理中に、素子部が形成される表面に損傷を与えなく
行うことが困難であることおよび■イントリンシックゲ
ッタリングにおいては、内部欠陥発生のために長時間（
１０〜２０時間）の熱処理が必要であり、素子形成プロ
セス中にこの処理を行うことは不可能であるという２点
である。The reason for this is: ■ In the backside strain layer gettering method, it is difficult to perform backside processing without damaging the surface on which the element part is formed, and ■ In the intrinsic gettering method, internal defects occur. for a long time (
Two points are that a heat treatment (10 to 20 hours) is required, and that it is impossible to perform this treatment during the element formation process.
このことは、不純物ゲッタリングにおいて太きな問題と
なりゲッタリング歪層形成後に素子形成するため素子形
成の熱処理により歪層が回復し、ゲッター効果が消失す
るという欠点がある。This becomes a major problem in impurity gettering, and since the device is formed after the formation of the gettering strained layer, the strained layer is recovered by the heat treatment for device formation and the getter effect disappears.
本発明のゲッタリング法は、半導体素子部以外の半導体
基板面および内部にＡｒ、Ｓｉ、Ｐ。The gettering method of the present invention uses Ar, Si, and P on the surface and inside of the semiconductor substrate other than the semiconductor element portion.
Ｂ、Ａｓ等の不純物イオンをＩ Ｘ １０ ”ａＡ以上
のドーズ量でかつ５０ＫｅＶ〜１０ＭｅＶのエネルギー
でイオン注入を行う工程を有している。The method includes a step of implanting impurity ions such as B and As at a dose of I x 10''aA or more and an energy of 50 KeV to 10 MeV.
次に、本発明を図面を用いてより詳細に説明する。実施
例としてＭＯＳ）ランジスタ作製プロセスの途中でシリ
コン基板表面の素子形成以外の表面領域にシリコンをイ
オン注入し、ゲッタリング処理を行なう場合について説
明する。Next, the present invention will be explained in more detail using the drawings. As an example, a case will be described in which silicon ions are implanted into a surface region of a silicon substrate other than where elements are formed during the process of manufacturing a MOS transistor and a gettering process is performed.
第１図（ａ）〜（ｄ）は、本発明の一実施例の断面図で
ある。第１図に於いて１はシリコン基板、２はフィール
ド酸化膜、３はゲート絶縁膜、４はゲート電極、５はソ
ース・ドレイン領域、６は素子形成以外の領域、７はイ
オン注入のマスク、８は歪層、９は絶縁膜、１０はアル
ミニウム配線である。ＭＯＳ）ランジスタを形成する手
順としては、まず選択酸化法により所望の領域にフィー
ルド酸化膜２を形成した後にゲート絶縁膜３を形成する
。次にゲート電極４を形成しイオン注入でソース・ドレ
イン領域５を形成した後にトランジスタ領域にマスク７
を形成し、素子形成以外の領域６にシリコンの５０Ｋｅ
Ｖイオン注入を行ない、歪層８を形成しマスク７を取り
除く。次に、ソース・ドレイン領域５形成のアニールを
行うと同時に、ゲッタリング処理を行う。次に、絶縁膜
９を形成し、ソース・ドレイン領域の表面の一部の絶縁
膜を除去した後にアルミニウム配線１ｏを形成しＭＯＳ
）ランジスタが完成する。FIGS. 1(a) to 1(d) are cross-sectional views of one embodiment of the present invention. In FIG. 1, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate insulating film, 4 is a gate electrode, 5 is a source/drain region, 6 is a region other than element formation, 7 is an ion implantation mask, 8 is a strained layer, 9 is an insulating film, and 10 is an aluminum wiring. The procedure for forming a MOS transistor is to first form a field oxide film 2 in a desired region by selective oxidation, and then form a gate insulating film 3. Next, a gate electrode 4 is formed, a source/drain region 5 is formed by ion implantation, and then a mask 7 is formed in the transistor region.
50Ke of silicon is formed in the region 6 other than the element formation.
V ion implantation is performed to form strained layer 8 and mask 7 is removed. Next, at the same time as annealing is performed to form the source/drain regions 5, a gettering process is performed. Next, an insulating film 9 is formed, and after removing a part of the insulating film on the surface of the source/drain region, an aluminum wiring 1o is formed and the MOS
) The transistor is completed.
実際の半導体装置に本実施例を適用する場合、チップの
周辺部、スクライブ線上にシリコン、リン２砒素等をイ
オン注入するのが有効である。When this embodiment is applied to an actual semiconductor device, it is effective to ion-implant silicon, phosphorus 2 arsenic, or the like into the periphery of the chip and onto the scribe lines.
次に本発明をＭＯＳ）ランジスタ作製プロセスの途中で
シリコン基板内部の素子形成以外の領域にシリコンをイ
オン注入し、ゲッタリング処理を行なう場合について説
明する。Next, a case will be described in which the present invention is carried out by implanting silicon ions into a region of a silicon substrate other than where elements are to be formed during the process of manufacturing a MOS transistor and performing a gettering process.
第２図（ａ）〜（ｃ）は、この場合の実施例の断面図で
ある。第２図に於いて、第１図と同じ参照数字は、同一
物質を示す。ＭＯＳ）ランジスタを形成する手順として
選択酸化法によりフィールド酸化膜２を形成した後に３
Ｍ ｅ Ｖの高エネルギーでシリコンイオン注入を行
い、トランジスタ形成領域の基板内部に歪層８を形成す
る。次にゲート絶縁膜３、ゲート電極４を形成した後に
ソース・ドレイン領域を形成し、絶縁膜９を形成し、ソ
ース・ドレイン領域の表面の一部の絶縁膜を除去した後
にアルミ配線７を形成し、Ｍｏｓトランジスタが完成す
る。FIGS. 2(a) to 2(c) are cross-sectional views of the embodiment in this case. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same materials. As a procedure for forming transistors (MOS), after forming field oxide film 2 by selective oxidation method, 3
Silicon ions are implanted at high energy of M e V to form a strained layer 8 inside the substrate in the transistor formation region. Next, after forming a gate insulating film 3 and a gate electrode 4, a source/drain region is formed, an insulating film 9 is formed, and after removing a part of the insulating film on the surface of the source/drain region, an aluminum wiring 7 is formed. Then, a Mos transistor is completed.
以上説明したように、本発明は半導体基板のゲッタリン
グ方法として素子形成領域以外の半導体基板表面および
内部にイオン注入で歪層を形成することにより不純物ゲ
ッタリングを行うため、半導体装置の製造の途中で必要
に応じゲッタリング処理を容易に行うことができ、半導
体装置の電気特性の変動を低減し、信頼性の高い半導体
装置を実現することができる効果がある。As explained above, the present invention performs impurity gettering by forming a strained layer by ion implantation on the surface and inside of the semiconductor substrate other than the element formation region as a gettering method for a semiconductor substrate, so that impurity gettering is performed during the manufacturing of a semiconductor device. The gettering process can be easily performed as needed, and there is an effect that fluctuations in the electrical characteristics of the semiconductor device can be reduced and a highly reliable semiconductor device can be realized.
第１図（ａ）〜（ｄ）は本発明の一実施例を工程順に説
明する断面図、第２図（ａ）〜（＄）は他の実施例を工
程順に説明する断面図である。
１・・・・・・シリコン基板、２・・・・・・フィール
ド酸化膜、３・・・・・・ゲート絶縁膜、４・・・・・
・ゲート電極、５・・・・・・ソース・ドレイン領域、
６・・・・・・素子形成以外の領域、７・・・・・・イ
オン注入のマスク、８・・・・・・歪層、９・・・・・
・絶縁膜、１０・・・・・・アルミニウム配線代理人
弁理士 内 原 晋
ｒの
ｒｄ＞
第１０FIGS. 1(a)-(d) are sectional views explaining one embodiment of the present invention in the order of steps, and FIGS. 2(a)-($) are sectional views explaining another embodiment in the order of steps. 1...Silicon substrate, 2...Field oxide film, 3...Gate insulating film, 4...
・Gate electrode, 5...source/drain region,
6...Region other than element formation, 7...Ion implantation mask, 8...Strained layer, 9...
・Insulating film, 10... Aluminum wiring agent
Patent Attorney Susumu Uchihara's rd> No. 10
Claims (1)
オン注入により歪層を形成することを特徴とする不純物
ゲッタリング方法 ２）特許請求の範囲第１項記載のイオン注入ドーズ量が
１×１０＾１＾５ｃｍ＾−＾２以上であることを特徴と
する不純物ゲッタリング方法 ３）特許請求の範囲第１項記載のイオン注入エネルギー
が５０ＫｅＶ〜１０ＭｅＶであることを特徴とする不純
物ゲッタリング方法[Claims] 1) An impurity gettering method characterized by forming a strained layer on the surface and inside of a semiconductor substrate other than a semiconductor element portion by ion implantation. 2) An ion implantation dose according to claim 1. 3) An impurity gettering method characterized in that the amount is 1×10^1^5 cm^-^2 or more; 3) An ion implantation energy as described in claim 1 is 50 KeV to 10 MeV. Impurity gettering method
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13494188A JPH01303727A (en) | 1988-05-31 | 1988-05-31 | Impurity gettering process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13494188A JPH01303727A (en) | 1988-05-31 | 1988-05-31 | Impurity gettering process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01303727A true JPH01303727A (en) | 1989-12-07 |
Family
ID=15140136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13494188A Pending JPH01303727A (en) | 1988-05-31 | 1988-05-31 | Impurity gettering process |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01303727A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129607A (en) * | 1991-10-31 | 1993-05-25 | Sharp Corp | Manufacture of semiconductor device |
| US6355377B1 (en) | 2000-03-07 | 2002-03-12 | Samsung Sdi Co., Ltd. | Negative active material for rechargeable lithium battery and method of preparing same |
| US6395427B1 (en) | 1999-11-04 | 2002-05-28 | Samsung Sdi Co., Ltd. | Negative active material for rechargeable lithium battery and method of preparing same |
| JP2013157454A (en) * | 2012-01-30 | 2013-08-15 | Hamamatsu Photonics Kk | Laser processing method, semiconductor device manufacturing method and laser processing device |
| JP2013201275A (en) * | 2012-03-23 | 2013-10-03 | Toshiba Corp | Semiconductor device, manufacturing method of the same and substrate |
-
1988
- 1988-05-31 JP JP13494188A patent/JPH01303727A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129607A (en) * | 1991-10-31 | 1993-05-25 | Sharp Corp | Manufacture of semiconductor device |
| US6395427B1 (en) | 1999-11-04 | 2002-05-28 | Samsung Sdi Co., Ltd. | Negative active material for rechargeable lithium battery and method of preparing same |
| US6355377B1 (en) | 2000-03-07 | 2002-03-12 | Samsung Sdi Co., Ltd. | Negative active material for rechargeable lithium battery and method of preparing same |
| JP2013157454A (en) * | 2012-01-30 | 2013-08-15 | Hamamatsu Photonics Kk | Laser processing method, semiconductor device manufacturing method and laser processing device |
| JP2013201275A (en) * | 2012-03-23 | 2013-10-03 | Toshiba Corp | Semiconductor device, manufacturing method of the same and substrate |
| US9136125B2 (en) | 2012-03-23 | 2015-09-15 | Kabushiki Kaisha Toshiba | Substrate of semiconductor device, for gettering metallic impurity |
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