JPH01300617A - Gate driving circuit - Google Patents
Gate driving circuitInfo
- Publication number
- JPH01300617A JPH01300617A JP63130142A JP13014288A JPH01300617A JP H01300617 A JPH01300617 A JP H01300617A JP 63130142 A JP63130142 A JP 63130142A JP 13014288 A JP13014288 A JP 13014288A JP H01300617 A JPH01300617 A JP H01300617A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- gate
- source
- semiconductor switch
- pulse transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 238000007599 discharging Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000004804 winding Methods 0.000 description 19
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
- H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、制御回路のオン・オフ信号をパルストラン
スによシ絶縁変換してＭＯＳＦＥＴ（Ｍｅｔａｌ ０ｘ
ｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅ
ｆｆｅｃｔＴｒａｎｓｉｓｔｏｒ ）のゲート・ソース
間に供給するゲート駆動回路に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention converts the on/off signals of a control circuit into insulation using a pulse transformer to convert MOSFET (Metal 0x
ide Sem1conductor Field E
The present invention relates to a gate drive circuit that supplies data between the gate and source of the FXTransistor.
この種のゲート駆動回路としては、例えば第６図に示す
回路構成のものが従来良く知られている。As this type of gate drive circuit, for example, a circuit configuration shown in FIG. 6 is well known.
こ＼に、パルストランス３の１次巻線の一方の端子は電
源Ｖ。０に、他方の端子はスイッチ１に、また１次端子
間にはパルストランスリセット回路２が接続されており
、パルストランス乙の２次巻惑にゲート駆動用電圧を発
生させる。パルストランス３０２次巻線の一方の端子と
ＭＯＳＦＥＴ７のゲート間にはダイオード５．ダイオー
ド１０゜及びゲート抵抗６の直列回路が、ダイオード５
と並列に抵抗４が、ダイオード５とダイオード１０の接
続点には抵抗１１とトランジスタ１２のペースが、ダイ
オード１０とゲート抵抗乙の接続点にはトランジスタ１
２のエミッタが、パルストランス３の２次巻線の他方の
端子には抵抗１１．トランジスタ１２のコレクタ及びＭ
ＯＳＦＥＴ７のソースが各々接続されている。Here, one terminal of the primary winding of the pulse transformer 3 is connected to the power supply V. 0, the other terminal is connected to the switch 1, and a pulse transformer reset circuit 2 is connected between the primary terminals to generate a gate driving voltage in the secondary winding of the pulse transformer B. A diode 5. is connected between one terminal of the secondary winding of the pulse transformer 30 and the gate of the MOSFET 7. A series circuit of a diode 10° and a gate resistor 6 is connected to a diode 5
A resistor 4 is connected in parallel with the resistor 4, a resistor 11 and a transistor 12 are connected at the connection point between the diode 5 and the diode 10, and a transistor 1 is connected at the connection point between the diode 10 and the gate resistor B.
The emitter of 11.2 is connected to the other terminal of the secondary winding of the pulse transformer 3. The collector of transistor 12 and M
The sources of OSFET 7 are connected to each other.
このような構成において、いまスイッチ１をオンさせる
と、パルストランス３の２次巻線に電圧が誘起されてダ
イオード５．ダイオード１０及びゲート抵抗６を通して
ＭＯＳＦＥＴ７のゲート・ソース間容量９が光電され、
ＭＯＳＦＥＴ７がオンとなる。次に、スイッチ１がオフ
になるとパルストランス３の２次巻線にはオン時とは逆
の極性のリセット電圧が発生する。この時、ＭＯＳＦＥ
Ｔ７のゲート・ソース間各社９に蓄積されている電荷に
より、トランジスタ１２のエミッタ、ベースを通って抵
抗１１を通る経路と、抵抗４及びパルストランス３を通
る経路に電流が流れトランジスタ１２はオンとなる。こ
の結果、ＭＯＳＦＥＴ７のゲート・ソース間容量９に蓄
積されている電荷はゲート抵抗６．トランジスタ１２の
コレクタ。In such a configuration, when the switch 1 is turned on now, a voltage is induced in the secondary winding of the pulse transformer 3 and the diode 5. The gate-source capacitance 9 of the MOSFET 7 is photoelectrically charged through the diode 10 and the gate resistor 6.
MOSFET 7 is turned on. Next, when the switch 1 is turned off, a reset voltage with a polarity opposite to that when it is on is generated in the secondary winding of the pulse transformer 3. At this time, the MOSFE
Due to the charge accumulated in the gate-source circuit 9 of T7, current flows through the emitter and base of the transistor 12, through the resistor 11, and through the resistor 4 and pulse transformer 3, turning the transistor 12 on. Become. As a result, the charge accumulated in the gate-source capacitance 9 of the MOSFET 7 is transferred to the gate resistance 6. Collector of transistor 12.
エミッタの経路で放電されＭＯＳＦＥＴ７はオフとなる
。MOSFET 7 is turned off due to discharge in the emitter path.
ところが、このような構成では、ＭＯＳＦＥＴ７がオフ
した後、パルストランス３のリセットエネルギーがなく
なると、トランジスタ１２はオフとなる。このような状
態でＭＯＳＦＥＴのドレイン・ソース間に急峻な電圧変
化が生じると、ドレイン・ゲート間容量８を通して急峻
な変化のある電流がゲートに流れ込み、ゲート・ソース
間容量９を光電する。この時、トランジスタ１２はオフ
状態であり、このＭＯＳＦＥＴ７のゲート・ソー間電圧
に反応してオンするまでにオン遅れ時間が存在する。そ
のだめ、このゲート・ソース間電圧がしきい値を越えて
ＭＯＳＦＥＴが誤オンし、発生損失が増大したり過電流
により破壊されるなどの問題が生じる。However, in such a configuration, after the MOSFET 7 is turned off and the reset energy of the pulse transformer 3 is exhausted, the transistor 12 is turned off. When a sharp voltage change occurs between the drain and source of the MOSFET in such a state, a current with a sharp change flows into the gate through the drain-gate capacitance 8 and photoelectrically charges the gate-source capacitance 9. At this time, the transistor 12 is in an off state, and there is a turn-on delay time until it turns on in response to the voltage between the gate and the source of the MOSFET 7. As a result, this gate-source voltage exceeds a threshold value, causing the MOSFET to turn on erroneously, resulting in problems such as increased loss and destruction due to overcurrent.
したがって、この発明はＭＯＳＦＥＴのオフ時に、その
ドレイン・ソース間に急峻に変化する電圧が印加された
場合でも誤オン動作をしないゲート駆動回路を提供する
ことを目的とする。Therefore, it is an object of the present invention to provide a gate drive circuit that does not turn on erroneously even if a rapidly changing voltage is applied between the drain and source of a MOSFET when the MOSFET is off.
制御回路からのオン、オフ信号をパルストランスにより
絶縁変換してＭＯＳＦＥＴのゲート・ソース間に伝達す
るゲート１駆動回路において、前記ＭＯＳＦＥＴをその
ゲート・ソース間容量に蓄積された電荷を放電させてオ
フするためのノーマリオン型半導体スイッチを設けると
−もに、前記オン信号によシ該ノーマリオン型半導体ス
イッチを逆バイアスしてオフさせる逆バイアス回路を設
ける。In the gate 1 drive circuit, which converts the on/off signal from the control circuit into isolation using a pulse transformer and transmits it between the gate and source of the MOSFET, the MOSFET is turned off by discharging the charge accumulated in the capacitance between the gate and source. A normally-on type semiconductor switch is provided to turn the normally-on type semiconductor switch off, and a reverse bias circuit is provided for reverse biasing the normally-on type semiconductor switch to turn it off in response to the on signal.
また、前記ＭＯＳＦＥＴをそのゲート・ソース問答ｔに
蓄積された電荷を放電させてオフするための絶縁ゲート
構造の電圧駆動型半導体スイッチを設けると−もに、前
記オフ信号期間中は該半導体スイッチのゲート・ソース
間容量の光電状態を該
保持する保持回路と、前記オン信号によルζ導体スイッ
チのゲート・ソース間容量の電荷を放電させる放電回路
とを設けるようにしても良い。Further, a voltage-driven semiconductor switch having an insulated gate structure is provided to turn off the MOSFET by discharging the charges accumulated in its gate and source, and during the off signal period, the semiconductor switch is turned off. A holding circuit that maintains the photoelectric state of the gate-source capacitance and a discharge circuit that discharges the charge of the gate-source capacitance of the ζ conductor switch in response to the on signal may be provided.
パルストランスを用いたゲート駆動回路のＭＯＳＦＥＴ
をオフさせる手段として、このＭＯＳＦＥＴのゲート・
ソース間に蓄積された電荷を放電させるためのノーマリ
オン型半導体スイッチを設け、上記ＭＯＳＦＥＴのオフ
期間中は常に上記ノーマリオン型半導体スイッチをオン
状態とし、上記ＭＯＳＦＥＴのオフ状態を安定にしよう
とするものである。さらに、上記ノーマリオン型半導体
スイッチを前記ＭＯＳＦＥＴへの制御回路からのオン信
号によりオフさせる手段を設けることで、このオン信号
により前記ＭＯＳＦＥＴをオン出来る状態にしようとす
るものである。MOSFET of gate drive circuit using pulse transformer
As a means to turn off the MOSFET, the gate
A normally-on semiconductor switch is provided for discharging the charge accumulated between the sources, and the normally-on semiconductor switch is always turned on during the off period of the MOSFET to stabilize the off state of the MOSFET. It is something. Further, by providing means for turning off the normally-on type semiconductor switch by an on signal from a control circuit to the MOSFET, the MOSFET can be turned on by this on signal.
同様にＭＯＳＦＥＴをオフさせる手段として、ＭＯＳＦ
ＥＴのゲート・ソース間に蓄積された電荷を放電させる
だめの絶縁ゲート構造の電圧屡勤形半導体スイッチを設
けると〜もに、この電圧駆動形半導体スイッチのゲート
・ソース間に蓄積された電荷を維持するだめの保持回路
を設けることで、前記ＭＯＳＦＥＴのオフ期間中は前記
電圧駆動形半導体スイッチをオンさせるための信号がな
くても、常にこの電圧駆動形半導体スイッチのオン状態
を保持し、前記ＭＯ３ＦＥＴのオフ状態を安定にしよう
とするものである。さらに、前記電圧駆動形半導体スイ
ッチのゲート・ソース間に蓄積された電荷を前記ＭＯＳ
ＦＥＴへのオン信号によシ放電させる放電回路を設ける
ことで、このＭＯＳＦＥＴへのオン信号で前記電圧駆動
形半導体スイッチをオフし、このＭＯＳＦＥＴのゲート
・ソース間に電荷を光電出来る状態にしようとするもの
である。Similarly, as a means to turn off the MOSFET, MOSFET
A voltage-current semiconductor switch with an insulated gate structure is provided to discharge the charge accumulated between the gate and source of the ET, and the charge accumulated between the gate and source of this voltage-driven semiconductor switch is By providing a holding circuit to maintain the voltage-driven semiconductor switch, the on-state of the voltage-driven semiconductor switch is always maintained even if there is no signal to turn on the voltage-driven semiconductor switch during the off-period of the MOSFET. This is intended to stabilize the off state of the MO3FET. Furthermore, the charge accumulated between the gate and source of the voltage-driven semiconductor switch is transferred to the MOS.
By providing a discharge circuit that discharges in response to an on signal to the FET, the voltage-driven semiconductor switch is turned off by the on signal to this MOSFET, and the electric charge can be photoelectrically generated between the gate and source of this MOSFET. It is something to do.
第１図はこの発明の実施例を示すもので、パルストラン
ス１３の１次巻線の一方の端子は電源ＶＣｃに、他方の
端子はスイッチ１に、また１次端子間にはパルストラン
スリセット回路２が接続されておυ、制御信号によりス
イッチ１をオン・オフさせることにより、パルストラン
ス３の２次巻線にゲート駆動用電圧を発生させる。パル
ストランス３の２次巻線の■端子とＭＯＳＦＥＴ７のゲ
ートの間にはダイオード５及びゲート抵抗乙の直列回路
が、ダイオード５とゲート抵抗乙の接続点には抵抗１５
と静電誘導型トランジスタ（以下、ＳｉＴと示す）１６
のドレインが、ＳｉＴ １６のゲートとパルストランス
１３０２次巻線の（′ｉ０端子との間にはダイオード１
４が、ダイオード１４と５ＩＴ１６のゲートの接続点に
は抵抗１５が、パルストランス１３０２次巻線の■端子
にはＭＯＳＦＥＴ７のソース及びＳｉＴ １６のソース
が各々接続されている。FIG. 1 shows an embodiment of the present invention, in which one terminal of the primary winding of a pulse transformer 13 is connected to the power supply VCc, the other terminal is connected to the switch 1, and a pulse transformer reset circuit is connected between the primary terminals. When the switch 1 is turned on and off by a control signal, a gate driving voltage is generated in the secondary winding of the pulse transformer 3. A series circuit of a diode 5 and a gate resistor B is connected between the ■terminal of the secondary winding of the pulse transformer 3 and the gate of the MOSFET 7, and a resistor 15 is connected to the connection point between the diode 5 and the gate resistor B.
and a static induction transistor (hereinafter referred to as SiT) 16
A diode 1 is connected between the gate of the SiT 16 and the ('i0 terminal) of the secondary winding of the pulse transformer 130.
4, a resistor 15 is connected to the connection point between the diode 14 and the gate of 5IT16, and the source of MOSFET 7 and the source of SiT 16 are connected to the terminal (2) of the secondary winding of the pulse transformer 130, respectively.
このような構成において、いまスイッチ１をオンさせる
と、パルストランス１３の２次巻線には、■端子を基準
とすると■端子、■端子には各々正と負の電圧が誘起さ
れる。この時、パルストランス１３の２次巻線の■端子
からダイオード１４を通して５ｉＴ１６のゲート・ソー
ス間が逆バイアスされてＳＡＴ １６はオフとなる一方
、■端子からダイオード５及びゲート抵抗６全通してＭ
ＯＳＦＥＴ７のゲート・ソース間容量９が充電され、Ｍ
ＯＳＦＥＴ７がオンとなる。In such a configuration, when the switch 1 is turned on, positive and negative voltages are induced in the secondary winding of the pulse transformer 13 at the ■ terminal and ■ terminal, respectively, with the ■ terminal as a reference. At this time, the gate and source of the 5iT16 are reverse biased from the ■ terminal of the secondary winding of the pulse transformer 13 through the diode 14, and the SAT 16 is turned off, while the M
The gate-source capacitance 9 of OSFET 7 is charged, and M
OSFET7 is turned on.
次に１スイツチ１がオフになると、パルストランス１３
の２次巻線にはオン時とは逆の極性のリセット電圧が発
生する。このため、ＳｉＴ １６のゲート・ソース間に
印加されていた逆バイアスがなくなると〜もに、ＭＯＳ
ＦＥＴ７のゲート・ソース間容量９に蓄積されていた電
荷が、ゲート抵抗６及び抵抗１５を通ってＳｉＴ １６
のゲート・ソース間を順バイアスするため、５ｉＴ１６
はオンとなる。この結果、ＭＯＳＦＥＴ７のゲート・ソ
ース間容量９に蓄積されていた電荷がゲート抵抗６及び
５ｉＴ１６のドレイン、ソースの経路で急速に放電され
、ＭＯＳＦＥＴ７はオフとなる。Next, when switch 1 is turned off, pulse transformer 13
A reset voltage with a polarity opposite to that when the switch is on is generated in the secondary winding of the switch. Therefore, when the reverse bias applied between the gate and source of the SiT 16 is removed, the MOS
The charge accumulated in the gate-source capacitance 9 of the FET 7 passes through the gate resistor 6 and the resistor 15 to the SiT 16
In order to forward bias between the gate and source of 5iT16
is turned on. As a result, the charge accumulated in the gate-source capacitance 9 of the MOSFET 7 is rapidly discharged through the gate resistor 6 and the drain-source path of the 5iT16, and the MOSFET 7 is turned off.
ＭＯＳＦＥＴ７が、ｒ）した後は、ＳｉＴ １６のゲー
ト・ソース間に印加されるバイアス電圧がなくなっても
、５ｉＴｆ６はノーマリオン型の素子（ゲート電圧０で
オン状態になっている）であるため、次にスイッチ１が
オンするまで５ｉＴ１６はオン状態を保持する。After MOSFET 7 performs r), even if the bias voltage applied between the gate and source of SiT 16 disappears, 5iTf6 is a normally-on type element (it is in the on state with gate voltage 0), so The 5iT16 remains on until the switch 1 is turned on next time.
第２図はこの発明の他の実施例を示すもので、パルスト
ランス３の１次巻線の一方の端子は電源ＶＣＣに、他方
の端子はスイッチ１に、また１次端子間にはパルストラ
ンスリセット回路２が接続されておシ、制御信号により
スイッチ１をオン・オフさせることにより、パルストラ
ンス３の２次巻線にゲート駆動用電圧を発生させる。パ
ルストランス３の２次巻線の一方の端子とＭＯＳＦＥＴ
７のゲートの間には、ダイオード５．ダイオード点とト
ランジスタ２１のベースの間には抵抗２０が、抵抗１８
と抵抗乙の接続点にはダイオード１９のアノードとＭＯ
ＳＦＥＴを含む電圧駆動型半導体素子２４のドレインが
、ダイオード１９のカソードとトランジスタ２１のコレ
クタの間には抵抗２２が、抵抗２２とトランジスタ２１
のコレクタの接続点にはＭＯＳＦＥＴ２４のゲートが、
ダイオード１９のカソードと抵抗２２の接続点にはコン
デンサ２３が、パルストランス３の他方の端子にはトラ
ンジスタ２１のエミッタ、コンデンサ２３、ＭＯＳＦＥ
Ｔ２４のソース及びＭＯＳＦＥＴ７のソースが各々接続
されている。FIG. 2 shows another embodiment of the present invention, in which one terminal of the primary winding of the pulse transformer 3 is connected to the power supply VCC, the other terminal is connected to the switch 1, and the pulse transformer is connected between the primary terminals. A reset circuit 2 is connected, and by turning the switch 1 on and off in response to a control signal, a gate driving voltage is generated in the secondary winding of the pulse transformer 3. One terminal of the secondary winding of pulse transformer 3 and MOSFET
Between the gates of 5 and 7, there is a diode 5. A resistor 20 is connected between the diode point and the base of the transistor 21, and a resistor 18 is connected between the diode point and the base of the transistor 21.
The anode of the diode 19 and the MO
A resistor 22 is connected between the drain of a voltage-driven semiconductor element 24 including an SFET, a cathode of a diode 19 and a collector of a transistor 21, and a resistor 22 is connected between the resistor 22 and the transistor 21.
The gate of MOSFET24 is at the connection point of the collector of
A capacitor 23 is connected to the connection point between the cathode of the diode 19 and the resistor 22, and the emitter of the transistor 21, the capacitor 23, and the MOSFE are connected to the other terminal of the pulse transformer 3.
The source of T24 and the source of MOSFET7 are connected to each other.
この様な構成において、スイッチ１をオンさせると、パ
ルストランス３の２次巻線に電圧が誘起され、ダイオー
ド５．抵抗６を通してトランジスタ２１０ペース、エミ
ッタに電流が流れてトランジスタ２１はオンし、これに
よりＭＯＳＦＥＴ２４のゲート・ソース間が短絡されＭ
ＯＳＦＥＴ２４はオフする。ＭＯＳＦＥＴ２４がオフし
ていれば、パルストランス乙の２次電圧により、ダイオ
ード５．ダイオード１７．抵抗１８及び抵抗６を通して
ＭＯＳＦＥＴ７のゲート・ソース間容量９が光電されて
ＭＯＳＦＥＴ７がオンとなる。さらにこの時、ダイオー
ド５．ダイオード１７．抵抗１８、ダイオード１９を通
してコンデンサ２３を光電する。In such a configuration, when switch 1 is turned on, a voltage is induced in the secondary winding of pulse transformer 3, and diode 5. Current flows through the resistor 6 to the emitter of the transistor 210, turning on the transistor 21, which short-circuits the gate and source of the MOSFET 24.
OSFET 24 is turned off. If MOSFET 24 is off, the secondary voltage of pulse transformer B causes diode 5. Diode 17. The gate-source capacitance 9 of the MOSFET 7 is photoelectrically charged through the resistor 18 and the resistor 6, and the MOSFET 7 is turned on. Furthermore, at this time, diode 5. Diode 17. A capacitor 23 is photoelectrically connected through a resistor 18 and a diode 19.
次に、スイッチ１がオフになると、パルストランス３の
２次巻線には、オン時とは逆のリセット電圧が発生する
。このリセット電圧によυ、抵抗４、抵抗２０を通して
、トランジスタ２１のペース、エミッタ間が逆バイアス
され、トランジスタ２１はオフする。トランジスタ２１
がオフすると、コンデンサ２３に蓄えられていた電荷に
より、抵抗２２を通してＭＯＳＦＥＴ２４のゲート・ソ
ース間を光電し、ＭＯＳＦＥＴ２４がオンする。この結
果、ＭＯＳＦＥＴ７のゲート・ソース間容反９に蓄積さ
れている電荷が放電され、ＭＯＳＦＥＴ７はオフとなる
。この時、ＭＯＳＦＥＴ２４のゲート・ソース間に蓄え
られている電荷は、ダイオード１９により、放電経路が
阻止されているため、次にスイッチ１がオンしてトラン
ジスタ２１がオンするまでＭＯＳＦＥＴ２４のオン状態
は、保持される。Next, when the switch 1 is turned off, a reset voltage opposite to that when it is on is generated in the secondary winding of the pulse transformer 3. This reset voltage reverse biases between the base and emitter of the transistor 21 through υ, the resistor 4, and the resistor 20, and the transistor 21 is turned off. transistor 21
When the MOSFET 24 is turned off, the electric charge stored in the capacitor 23 causes a photoelectric current to flow between the gate and source of the MOSFET 24 through the resistor 22, and the MOSFET 24 is turned on. As a result, the charge accumulated in the gate-source capacitance 9 of MOSFET 7 is discharged, and MOSFET 7 is turned off. At this time, the discharge path of the charge stored between the gate and source of the MOSFET 24 is blocked by the diode 19, so the ON state of the MOSFET 24 is as follows until the next switch 1 is turned on and the transistor 21 is turned on. Retained.
なお、上記ではスイッチ２４としてＭＯＳＦＥＴを使用
したが、これと同様の機能をもつ絶縁ゲート構造の電圧
駆動型半導体スイッチを用いることができる。Although a MOSFET is used as the switch 24 in the above example, a voltage-driven semiconductor switch having an insulated gate structure and having the same function as the MOSFET can also be used.
この発明によればＭＯＳＦＥＴをオフさせる手段として
、このＭＯＳＦＥＴのゲート・ソース間容量に蓄積され
た電荷を放電させるだめのノーマリオン型半導体スイッ
チを備えることで、制御回路から上記ＭＯＳＦＥＴにオ
ン信号がある時以外は、常に上記ノーマリオン型半導体
スイッチをオン状態に保持する。その結果、上記ＭＯＳ
ＦＥＴのオフ期間中の状態を安定にし、そのドレイン・
ソース間に急峻に変化する電圧が印加された場合でも誤
オンをなくすことができる。According to the present invention, as a means for turning off the MOSFET, a normally-on type semiconductor switch is provided to discharge the charge accumulated in the capacitance between the gate and source of the MOSFET, so that an on signal is sent to the MOSFET from the control circuit. The normally-on semiconductor switch is always kept in the on state at all times other than the above. As a result, the above MOS
Stabilizes the state of the FET during its off period and protects its drain.
Erroneous turn-on can be eliminated even when a rapidly changing voltage is applied between the sources.
また、ＭＯＳＦＥＴをオフさせる手段として、このＭＯ
ＳＦＥＴのゲート・ソース間に蓄積された電荷を放電さ
せるための絶縁形ゲートを有する電圧駆動形半導体スイ
ッチを設けると−もに、電圧駆動形半導体スイッチの絶
縁形ゲートに蓄積された電荷を維持するための保持回路
を設けることにより、上記ＭＯＳＦＥＴのオフ期間中は
、上記電圧駆動形半導体スイッチをオンさせるだめの信
号がなくても、常にこの電圧駆動形半導体スイッチのオ
ン状態を保持できる結果、上記ＭＯＳＦＥＴのオフ状態
を安定にし、ドレイン・ソース間に急峻に変化する電圧
が印加された場合でも誤オンをなくすことができる。Also, this MOSFET can be used as a means to turn off the MOSFET.
A voltage-driven semiconductor switch having an insulated gate for discharging the charge accumulated between the gate and source of the SFET is provided, and the charge accumulated in the insulated gate of the voltage-driven semiconductor switch is maintained. By providing a holding circuit for this purpose, the on state of the voltage driven semiconductor switch can be maintained at all times during the off period of the MOSFET, even if there is no signal to turn on the voltage driven semiconductor switch. It is possible to stabilize the off-state of the MOSFET and eliminate erroneous on-states even when a rapidly changing voltage is applied between the drain and source.
第１図はこの発明の実施例を示す回路図、第２図はこの
発明の他の実施例を示す回路図、第３図はゲート駆動回
路の従来例を示す回路図である。
符号説明
１・・・・・・スイッチ、２・・・・・・パルストラン
スリセラ）回路、３．１３・・・・・・パルストランス
、４．６゜１１．１５．１８，２０．２２・・・・・・
抵抗、５，１０．１４，１７．１９・・・・・・ダイオ
ード、７，２４・・・・・・ＭＯＳＦＥＴ、８・・・・
・・ドレイン・ゲート間容量、９・・・・・・ゲート・
ソース間容量、１２．２１・・・・・・トランジスタ、
１６・・・・・・静電誘導型トランジスタ（ＳｉＴ）、
２３・・・・・・コンデンサ。
代理人 弁理士 並 木 昭 夫
代理人 弁理士 松 崎 清
１１ 図
頁 ２ 図
第３ ！ＪFIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional example of a gate drive circuit. Description of symbols 1...Switch, 2...Pulse transformer reseller) circuit, 3.13...Pulse transformer, 4.6゜11.15.18, 20.22.・・・・・・
Resistor, 5, 10.14, 17.19... Diode, 7, 24... MOSFET, 8...
...Drain-gate capacitance, 9...Gate...
Source-to-source capacitance, 12.21...transistor,
16... Static induction transistor (SiT),
23... Capacitor. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki 11 Figure Page 2 Figure 3! J
Claims (1)
より絶縁変換してＭＯＳＦＥＴのゲート・ソース間に伝
達するゲート駆動回路において、前記ＭＯＳＦＥＴをそ
のゲート・ソース間容量に蓄積された電荷を放電させて
オフするためのノーマリオン型半導体スイッチを設ける
とゝもに、前記オン信号により該ノーマリオン型半導体
素子を逆バイアスしてオフさせる逆バイアス回路を設け
たことを特徴とするゲート駆動回路。 ２）制御回路からのオン、オフ信号をパルストランスに
より絶縁変換してＭＯＳＦＥＴのゲート・ソース間に伝
達するゲート駆動回路において、前記ＭＯＳＦＥＴをそ
のゲート・ソース間容量に蓄積された電荷を放電させて
オフするための絶縁ゲート構造の電圧駆動型半導体スイ
ッチを設けるとゝもに、 前記オフ信号期間中は該半導体スイッチのゲート・ソー
ス間容量の充電状態を保持する保持回路と、 前記オン信号により該半導体スイッチのゲート・ソース
間容量の電荷を放電させる放電回路と、を設けたことを
特徴とするゲート駆動回路。[Claims] 1) In a gate drive circuit that insulates and converts on and off signals from a control circuit using a pulse transformer and transmits them between the gate and source of a MOSFET, The device is characterized in that it is provided with a normally-on type semiconductor switch for discharging the accumulated charge and turning it off, and a reverse bias circuit that reversely biases the normally-on type semiconductor element and turns it off in response to the on signal. Gate drive circuit. 2) In a gate drive circuit that insulates and converts ON and OFF signals from a control circuit using a pulse transformer and transmits them between the gate and source of a MOSFET, the MOSFET discharges the charge accumulated in its gate-source capacitance. A voltage-driven semiconductor switch with an insulated gate structure for turning off is provided, and a holding circuit is provided to maintain the charge state of the gate-source capacitance of the semiconductor switch during the period of the off signal, 1. A gate drive circuit comprising: a discharge circuit that discharges charge in a gate-source capacitance of a semiconductor switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63130142A JPH01300617A (en) | 1988-05-30 | 1988-05-30 | Gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63130142A JPH01300617A (en) | 1988-05-30 | 1988-05-30 | Gate driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01300617A true JPH01300617A (en) | 1989-12-05 |
Family
ID=15026974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63130142A Pending JPH01300617A (en) | 1988-05-30 | 1988-05-30 | Gate driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01300617A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273828U (en) * | 1988-11-25 | 1990-06-06 | ||
| WO1993012581A1 (en) * | 1991-12-11 | 1993-06-24 | Vlt Corporation | High efficiency floating gate driver circuit using leakage-inductance transformer |
| JP2009081962A (en) * | 2007-09-26 | 2009-04-16 | Sharp Corp | Switching circuit, circuit, and circuit including switching circuit and driving pulse generation circuit |
| WO2010021082A1 (en) * | 2008-08-21 | 2010-02-25 | 三菱電機株式会社 | Driving circuit for power semiconductor element |
| JP2012034079A (en) * | 2010-07-29 | 2012-02-16 | Fuji Electric Co Ltd | Driving circuit for insulated gate type device |
| JP2014112925A (en) * | 2014-02-07 | 2014-06-19 | Fuji Electric Co Ltd | Drive circuit for insulated gate device |
| EP3029835A4 (en) * | 2013-07-31 | 2016-08-17 | Panasonic Ip Man Co Ltd | High-frequency reception circuit and insulated signal-transmission device |
-
1988
- 1988-05-30 JP JP63130142A patent/JPH01300617A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273828U (en) * | 1988-11-25 | 1990-06-06 | ||
| WO1993012581A1 (en) * | 1991-12-11 | 1993-06-24 | Vlt Corporation | High efficiency floating gate driver circuit using leakage-inductance transformer |
| US6107860A (en) * | 1991-12-11 | 2000-08-22 | Vlt Corporation | High efficiency floating gate driver circuit using leakage-inductance transformer |
| JP2009081962A (en) * | 2007-09-26 | 2009-04-16 | Sharp Corp | Switching circuit, circuit, and circuit including switching circuit and driving pulse generation circuit |
| WO2010021082A1 (en) * | 2008-08-21 | 2010-02-25 | 三菱電機株式会社 | Driving circuit for power semiconductor element |
| JP2013179828A (en) * | 2008-08-21 | 2013-09-09 | Mitsubishi Electric Corp | Power semiconductor device drive circuit |
| US9806593B2 (en) | 2008-08-21 | 2017-10-31 | Mitsubishi Electric Corporation | Drive circuit of power semiconductor device |
| JP2012034079A (en) * | 2010-07-29 | 2012-02-16 | Fuji Electric Co Ltd | Driving circuit for insulated gate type device |
| US8890581B2 (en) | 2010-07-29 | 2014-11-18 | Fuji Electric Co., Ltd. | Driving circuit of insulated gate device |
| EP3029835A4 (en) * | 2013-07-31 | 2016-08-17 | Panasonic Ip Man Co Ltd | High-frequency reception circuit and insulated signal-transmission device |
| JPWO2015015708A1 (en) * | 2013-07-31 | 2017-03-02 | パナソニックＩｐマネジメント株式会社 | High frequency receiver circuit and insulated signal transmission device |
| JP2014112925A (en) * | 2014-02-07 | 2014-06-19 | Fuji Electric Co Ltd | Drive circuit for insulated gate device |
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