JPH01293613A - Substrate for discrete devices and manufacture of the same - Google Patents
Substrate for discrete devices and manufacture of the sameInfo
- Publication number
- JPH01293613A JPH01293613A JP88126591A JP12659188A JPH01293613A JP H01293613 A JPH01293613 A JP H01293613A JP 88126591 A JP88126591 A JP 88126591A JP 12659188 A JP12659188 A JP 12659188A JP H01293613 A JPH01293613 A JP H01293613A
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- semiconductor wafer
- cut
- diffusion layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 title claims description 31
- 239000012535 impurity Substances 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 239000013078 crystal Substances 0.000 abstract description 15
- 239000002699 waste material Substances 0.000 abstract description 5
- 229910003460 diamond Inorganic materials 0.000 abstract description 3
- 239000010432 diamond Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000001993 wax Substances 0.000 description 3
- 235000013871 bee wax Nutrition 0.000 description 1
- 239000012166 beeswax Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ディスクリート素子用基板およびその製造方
法に関する。さらに詳しくは、シリコン（ＳＬ）単結晶
の円板形等からなる半導体ウェハからなるトランジスタ
、ダイオード等のディスクリート索子（個別素子）用基
板の製造面に係る改良と、そのディスクリート素子用基
板を製造するための方法とに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate for discrete elements and a method for manufacturing the same. More specifically, we will improve the manufacturing aspects of substrates for discrete elements (individual elements) such as transistors and diodes made of semiconductor wafers made of disk-shaped silicon (SL) single crystals, and manufacture substrates for such discrete elements. and a method for doing so.
［従来の技術］
従来、シリコン単結晶の円板形等からなる半導体ウェハ
からなるトランジスタ、ダイオード等のディスクリート
素子用基板の製造手段としては、例えば第６図〜第８図
に示すものが知られている。[Prior Art] Conventionally, as a means for manufacturing substrates for discrete elements such as transistors and diodes made of semiconductor wafers made of disk-shaped silicon single crystals, the methods shown in FIGS. 6 to 8, for example, are known. ing.
この従来のディスクリート素子用基″板の製造手段は、
棒状のシリコン単結晶からなるインゴット等からダイヤ
モンドカッタ等で一定厚み巾に半導体ウェハ１を切断成
形して、まず第６図に示すように半導体ウェハ１を拡散
炉に入れる等してその両面に不純物を拡散して不純物拡
散層２を形成し、その後第７図に示すように研削装置Ｇ
等により半導体ウェハ１の片面を研削して不純物の拡散
されていない不純物未拡散層３を形成するものである。This conventional manufacturing method for discrete element substrates is as follows:
Semiconductor wafer 1 is cut and formed from an ingot made of rod-shaped silicon single crystal to a certain thickness using a diamond cutter or the like. First, as shown in FIG. 6, semiconductor wafer 1 is placed in a diffusion furnace to remove impurities from both sides. is diffused to form an impurity diffusion layer 2, and then as shown in FIG.
One side of the semiconductor wafer 1 is ground by a method such as the above method to form an impurity-undiffused layer 3 in which impurities are not diffused.
そして、このディスクリート素子用基板は、さらに第８
図に示すように不純物未拡散層３に新たな不純物４、例
えばトランジスタではベース、エミッタ等を形成する新
たな不純物を拡散してからチップ化され実装されること
になる。This discrete element substrate further includes an eighth
As shown in the figure, a new impurity 4, for example, a new impurity forming the base, emitter, etc. of a transistor, is diffused into the undiffused impurity layer 3, and then chipped and mounted.
［発明が解決しようとする課題］
前述の従来のディスクリート素子用基板の製造手段では
、半導体ウェハ１の両面に不純物拡散層２と不純物未払
数Ｉｉ３とを備えなければならないという構造に対応す
るために、′第７図に示すような半導体ウェハ１の片面
の研削を行なうことから、高価なシリコン単結晶をキリ
コとして損失してしまい、また拡散工程によってわざわ
ざ形成した片面の不純物拡散層２がキリコとして除去さ
れてしまうという問題点を有している。[Problems to be Solved by the Invention] In order to cope with the structure in which the above-mentioned conventional means for manufacturing a discrete element substrate requires the impurity diffusion layer 2 and the unpaid impurity number Ii3 to be provided on both sides of the semiconductor wafer 1. In addition, since grinding is performed on one side of the semiconductor wafer 1 as shown in Fig. 7, expensive silicon single crystals are lost as chips, and the impurity diffusion layer 2 on one side, which was purposefully formed in the diffusion process, is lost as chips. This has the problem that it is removed as .
本発明はこのような問題点を解決するためになされたも
のであり、その目的は、シリコン単結晶。The present invention was made to solve these problems, and its purpose is to provide silicon single crystal.
不純物拡散層の損失、除去に伴う無駄を防止することの
できる構造を備えたディスクリート素子用基板と、これ
を製造するためのディスクリート索子用基板の製造方法
とを提供することにある。It is an object of the present invention to provide a substrate for a discrete element having a structure capable of preventing loss of an impurity diffusion layer and waste caused by removal, and a method for manufacturing a substrate for a discrete cable for manufacturing the same.
［１題を解決するための手段］
前述の目的を達成するため、本発明に係るディスクリー
ト素子用基板およびその製造方法は、次のような手段を
採用する。[Means for Solving a Problem] In order to achieve the above-mentioned object, a discrete element substrate and a manufacturing method thereof according to the present invention employ the following means.
即ち、請求項１はディスクリート索子用基板に係り、半
導体ウェハの一面に不純物が拡散された不純物拡散層を
有し、またその他面に新たな不純物を拡散するための不
純物未拡散層を有するディスクリート素子用基板におい
て、両面に不純物が拡散された不純物拡散層を有する半
導体ウェハを厚み巾の中心から二分割することで、二分
割の切断面側を不純物未拡散層としたことを特徴とする
基板である。That is, claim 1 relates to a substrate for a discrete cable, which has an impurity diffusion layer in which impurities are diffused on one surface of a semiconductor wafer, and an impurity non-diffusion layer for diffusing new impurities on the other surface. A substrate for an element, characterized in that a semiconductor wafer having impurity diffusion layers on both sides of which impurities are diffused is divided into two parts from the center of the thickness width, so that the cut plane side of the two divisions becomes an impurity-undiffused layer. It is.
また、請求項２はディスクリート素子用基板の製造方法
に係り、中央部に不純物未拡散層を有し、両面に不純物
が拡散された不純物拡散層を有する半導体ウェハを、厚
み巾の中心から切断して二分割し、二分割された各半導
体ウェハの夫々の切断面を新たな不純物を拡散するため
の不純物未拡散層としたことを特徴とする手段である。Further, claim 2 relates to a method for manufacturing a substrate for a discrete element, in which a semiconductor wafer having an impurity undiffused layer in the center and impurity diffused layers in which impurities are diffused on both sides is cut from the center of the thickness. This method is characterized in that the semiconductor wafer is divided into two parts, and each cut surface of each of the two parts is used as an impurity-undiffused layer for diffusing new impurities.
さらに、請求項３もディスクリート素子用基板の製造方
法に係り、中央部に不純物未拡散層を有し、両面に不純
物が拡散された不純物拡ｒ＆ｌｌを有する多数枚の半導
体ウェハを結合材を介して積層一体化し、各半導体ウェ
ハの厚み巾の中心から夫々切断して二分割すると共に結
合材を除去し、二分割された各半導体ウェハの夫々の切
１１ｉ面側を新たな不純物を拡散するための不純物未拡
散層としたことを特徴とする手段である。Furthermore, claim 3 also relates to a method for manufacturing a substrate for a discrete element, in which a large number of semiconductor wafers having an impurity undiffused layer in the center and impurity diffusion r&ll with impurities diffused on both sides are bonded together. The semiconductor wafers are laminated and integrated, and each semiconductor wafer is cut from the center of its thickness to be divided into two parts, and the binding material is removed. This means is characterized in that it is an impurity-undiffused layer.
［作 用］
前述の手段によると、両面に不純物拡散層を有する半導
体ウェハを二分割することにより、前述の従来の研削を
行なわずに不純物未拡散層を形成することができるため
、シリコン単結晶、不純物拡散層の損失、除去に伴う無
駄を防止するという目的を達成することができる。[Function] According to the above-mentioned means, by dividing a semiconductor wafer having impurity diffusion layers on both sides into two, it is possible to form an impurity-undiffused layer without performing the conventional grinding described above. Therefore, it is possible to achieve the purpose of preventing loss of the impurity diffusion layer and waste associated with removal.
［実施例］
以下、本発明に係るディスクリート素子用基板およびそ
の製造方法の実施例を第１図〜第５図に基いて説明する
。[Example] Hereinafter, an example of a discrete element substrate and a manufacturing method thereof according to the present invention will be described with reference to FIGS. 1 to 5.
このディスクリート素子用基板の実施例は、第１図（Ａ
）に示すような両面に不純物拡散層２を有する半導体ウ
ェハ１を、第１図（Ｂ）に示すように厚み巾の中心から
切断して二分割し、その切断面を不純物未拡散層３とし
てなるものである。An example of this discrete element substrate is shown in FIG.
) A semiconductor wafer 1 having impurity diffused layers 2 on both sides is cut into two parts by cutting from the center of the thickness width as shown in FIG. It is what it is.
このようなディスクリート素子用基板の実施例の製造実
施例としては、まずインゴットの切断等による半導体ウ
ェハ１の成形の際に、半導体装置ハ１の厚み巾を二分割
可能な厚み巾に成形しておき、次に半導体ウェハ１の厚
み巾の中心を検出して、インゴットからの半導体ウェハ
１の切断に用いられるダイヤモンドカッタ等でこの中心
から二分割に切断する。即ち、半導体ウェハ１の不純物
拡散ＷＪ２はそのまま利用され、−枚の半導体ウェハ１
から不純物未拡散層３を有する二枚のディスクリート素
子用基板が形成されることになる。なお、このような切
断によると、前記中心の検出が困難でありまた切断面が
粗雑となるため、寸法修正や研磨仕上等の表面修正式５
を予め前記成形の際に厚み巾に付加しておくとよい。As an example of manufacturing such a substrate for discrete elements, first, when forming the semiconductor wafer 1 by cutting an ingot or the like, the thickness of the semiconductor device C 1 is formed into a thickness width that can be divided into two. Next, the center of the thickness width of the semiconductor wafer 1 is detected, and the semiconductor wafer 1 is cut into two parts from this center using a diamond cutter or the like used for cutting the semiconductor wafer 1 from an ingot. That is, the impurity diffusion WJ2 of the semiconductor wafer 1 is used as is, and - semiconductor wafers 1
From this, two discrete element substrates having impurity undiffused layers 3 are formed. Note that with such cutting, it is difficult to detect the center and the cut surface becomes rough.
It is preferable to add this to the thickness and width in advance during the molding.
また、半導体ウェハ１が第２図（Ａ）に示すように比較
的薄い場合には、第２図（Ｂ）に示すようにワックス、
ガルバナワックス、ミツロウ、合成油脂等の結合材６を
半導体ウェハ１の両面に塗布し、結合材６を介して半導
体ウェハ１積層一体化して切断装置等に保持しやすくし
た後に、第３図（Ａ）に示すように半導体ウェハ１を一
枚のカッタ７を用いて、該カッタ又はウェハ積層体を移
動じ各ウェハ毎に切断した後、第３図（Ｂ）に示すよう
に結合材６を除去するとよい。なお、このように半導体
ウェハ１を１１１一体化した場合、例えばワイヤソー又
はマルチブレード等の複数枚のカッタを設けて複数枚の
半導体ウェハ１を同時に切断することもできる。Further, when the semiconductor wafer 1 is relatively thin as shown in FIG. 2(A), wax or wax as shown in FIG. 2(B) may be used.
After applying a binding material 6 such as galvana wax, beeswax, synthetic oil, etc. to both sides of the semiconductor wafer 1 and integrating the semiconductor wafers 1 through the binding material 6 to make them easier to hold in a cutting device, etc., After cutting the semiconductor wafer 1 into individual wafers using a single cutter 7 by moving the cutter or the wafer stack as shown in A), the bonding material 6 is applied as shown in FIG. 3(B). It is best to remove it. Note that when the semiconductor wafers 1 are integrated 111 in this way, a plurality of cutters such as a wire saw or a multi-blade may be provided to cut the plurality of semiconductor wafers 1 at the same time.
このような製造実施例によると、半導体ウェハ１の不純
物拡散層２はそのまま利用され除去されておらず、また
半導体ウェハ１を構成するシリコン単結晶も従来に比し
損失が低減されている。According to this manufacturing example, the impurity diffusion layer 2 of the semiconductor wafer 1 is used as is and is not removed, and the loss of the silicon single crystal constituting the semiconductor wafer 1 is also reduced compared to the conventional case.
即ち、第４図（従来例）、第５図（本発明）は、シリコ
ン単結晶の損失を対比するものである。That is, FIG. 4 (conventional example) and FIG. 5 (present invention) compare losses in silicon single crystals.
従来例では、第４図（Ａ）に示すようにインゴット８か
らカッティングのキリコａを消耗して厚み巾すの半導体
ウェハ１が切断成形され、第４図（Ｂ）に示すようにこ
の半導体ウェハ１に不純物拡散［１２が形成されその厚
み巾を変化なくｂとすると（研磨等の消耗は微りなため
無視する）、不純物未拡散ＪＩ３を形成するための研削
によってその厚み巾すの約半分１／２ｂがキリコとして
消耗され、第４図（Ｃ）に示すように厚み巾１／２ｂの
ディスクリート素子用基板が得られる。このため、１／
２ｂのディスクリート素子用基板の一枚の製造につき、
ａ＋１／２ｂｆｆｉのシリコン単結晶が消耗されること
になる。In the conventional example, as shown in FIG. 4(A), a semiconductor wafer 1 having a thick thickness is cut and formed from an ingot 8 by consuming the cutting chip a, and as shown in FIG. 4(B), this semiconductor wafer is If impurity diffusion [12] is formed in 1 and its thickness width remains constant b (the wear and tear caused by polishing etc. is negligible and therefore ignored), then the grinding to form impurity-undiffused JI3 will result in approximately half the thickness 1. /2b is consumed as a sliver, and a discrete element substrate having a thickness of 1/2b is obtained as shown in FIG. 4(C). For this reason, 1/
For manufacturing one piece of 2b discrete element substrate,
A+1/2 bffi of silicon single crystal will be consumed.
一方、本発明では、第５図（Ａ）に示すようにインゴッ
ト８からカッティングのキリコａを消耗して厚み巾Ｃの
半導体ウェハ１が切断成形されることになるが、ｃ＝１
／２ｂ＋１／２ｂ＋ｄ＋ｄ＋ａであり（ａは半導体ウェ
ハ１のキリコ代でありインゴット８からカッティングの
キリコと同社としてあり、またｄは前記表面修正式５で
ある）、最終的に第５図（Ｃ）に示すように厚み巾１／
２ｂのディスクリート素子用基板が二枚得られる。On the other hand, in the present invention, as shown in FIG. 5(A), the semiconductor wafer 1 having the thickness width C is cut and formed by consuming the cutting chirco a from the ingot 8, but c=1
/2b+1/2b+d+d+a (a is the cutting cost of semiconductor wafer 1, which is the cutting cost from ingot 8, and d is the surface modification formula 5), and finally, as shown in FIG. 5(C). Thickness width 1/ as shown
Two discrete element substrates 2b are obtained.
このため、１／２ｂのディスクリート素子用基板の一枚
の製造につき、１／２ （ａ＋ａ＋ｄ＋ｄ）＝ ａ ＋
ｄ 帛のシリコン単結晶が消耗されることになり、従
来の消耗ｆｆ１ａ＋１／２ｂとの対比において、ｄは微
量で足りｄ＜１／２ｂであるから、本発明ではシリコン
単結晶の消耗が低減されることになる。Therefore, for manufacturing one 1/2b discrete element substrate, 1/2 (a+a+d+d)=a +
d The silicon single crystal of the cloth is consumed, and in comparison with the conventional consumption ff1a+1/2b, a very small amount of d is sufficient and d<1/2b, so the present invention reduces the consumption of the silicon single crystal. That will happen.
［発明の効果］
以上のように本発明に係るディスクリート素子用基板お
よびその製造方法は、請求項１〜３共通として、半導体
ウェハの二分割によりその不純物拡散層をそのまま利用
しそのシリコン単結晶の消耗が低減されるため、シリコ
ン単結晶、不純物拡散層の損失、除去に伴う無駄が防止
される効果がある。また、この効果によって、ディスク
リート素子用基板の製造コストが低減される効果が生ず
る。[Effects of the Invention] As described above, the discrete element substrate and the manufacturing method thereof according to the present invention are common to claims 1 to 3, in which the semiconductor wafer is divided into two parts, the impurity diffusion layer is used as is, and the silicon single crystal is formed by dividing the semiconductor wafer into two parts. Since consumption is reduced, loss of the silicon single crystal and the impurity diffusion layer and waste due to removal can be prevented. Moreover, this effect brings about the effect that the manufacturing cost of the discrete element substrate is reduced.
さらに、請求項３の方法では、半導体ウェハが積層一体
化されるため、比較的薄い半導体ウェハからも製造する
ことができる効果がある。Furthermore, in the method of claim 3, since the semiconductor wafers are stacked and integrated, there is an advantage that even relatively thin semiconductor wafers can be manufactured.
第１図（Ａ）、（Ｂ）は本発明に係るディスクリート素
子用基板およびその製造方法の実施例を示す工程の断面
図、第２図（Ａ＞、（Ｂ）は第１図の他実施例を示す工
程の断面図、第３図（Ａ）。
（Ｂ）は第２図の次工程を示す断面図、第４図（Ａ）、
（Ｂ）、（Ｃ）はシリコン単結晶の消耗［１（従来例）
を示す断面図、第５図は（Ａ）。
（Ｂ）、（Ｃ）は第４図と対比される本発明の断面図、
第６図〜第８図は従来例の工程を示す断面図である。
１・・・半導体ウェハ ２・・・不純物拡散層３
・・・不純物未拡散層 ４・・・新たな不純物６・
・・結合材 ８・・・インゴット特 許
出 願 人 直江津電子工業株式会社第６図
第７図
第８図FIGS. 1(A) and (B) are cross-sectional views of steps showing an embodiment of the discrete element substrate and its manufacturing method according to the present invention, and FIGS. FIG. 3 (A) is a cross-sectional view of the process showing an example. (B) is a cross-sectional view showing the next step from FIG. 2, FIG.
(B) and (C) are consumption of silicon single crystal [1 (conventional example)
A sectional view showing FIG. 5 is (A). (B) and (C) are cross-sectional views of the present invention compared with FIG.
6 to 8 are cross-sectional views showing the steps of a conventional example. 1... Semiconductor wafer 2... Impurity diffusion layer 3
... Impurity undiffused layer 4... New impurity 6.
...Binding material 8...Ingot patent
Applicant: Naoetsu Electronics Industry Co., Ltd. Figure 6 Figure 7 Figure 8
Claims (1)
散層を有し、またその他面に新たな不純物を拡散するた
めの不純物未拡散層を有するディスクリート素子用基板
において、両面に不純物が拡散された不純物拡散層を有
する半導体ウェハを厚み巾の中心から二分割することで
、二分割の切断面を不純物未拡散層としたことを特徴と
するディスクリート素子用基板。 ２、中央部に不純物未拡散層を有し、両面に不純物が拡
散された不純物拡散層を有する半導体ウェハを、厚み巾
の中心から切断して二分割し、二分割された各半導体ウ
ェハの夫々の切断面側を新たな不純物を拡散するための
不純物未拡散層としたことを特徴とするディスクリート
素子用基板の製造方法。 ３、中央部に不純物未拡散層を有し、両面に不純物が拡
散された不純物拡散層を有する多数枚の半導体ウェハを
結合材を介して積層一体化し、各半導体ウェハの厚み巾
の中心から夫々切断して二分割すると共に結合材を除去
し、二分割された各半導体ウェハの夫々の切断面を新た
な不純物を拡散するための不純物拡散層としたことを特
徴とするディスクリート素子用基板の製造方法。[Claims] 1. A substrate for a discrete element having an impurity diffusion layer in which impurities are diffused on one surface of a semiconductor wafer and an impurity non-diffusion layer for diffusing new impurities on the other surface; A substrate for a discrete element, characterized in that a semiconductor wafer having an impurity diffusion layer in which impurities are diffused is divided into two from the center of the thickness width, and the cut plane of the two halves is made into an impurity-undiffused layer. 2. A semiconductor wafer having an undiffused impurity layer in the center and impurity diffused layers with impurities diffused on both sides is cut into two parts by cutting from the center of the thickness width, and each of the two semiconductor wafers is divided into two parts. A method for manufacturing a substrate for a discrete element, characterized in that the cut side of the substrate is used as an impurity undiffused layer for diffusing new impurities. 3. A large number of semiconductor wafers having an undiffused impurity layer in the center and impurity diffused layers with impurities diffused on both sides are stacked together via a bonding material, and each semiconductor wafer is separated from the center of its thickness. Manufacture of a substrate for a discrete element, characterized in that the semiconductor wafer is cut into two parts, the binding material is removed, and each cut surface of each of the two parts is used as an impurity diffusion layer for diffusing new impurities. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP88126591A JPH01293613A (en) | 1988-05-23 | 1988-05-23 | Substrate for discrete devices and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP88126591A JPH01293613A (en) | 1988-05-23 | 1988-05-23 | Substrate for discrete devices and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01293613A true JPH01293613A (en) | 1989-11-27 |
Family
ID=14938974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP88126591A Pending JPH01293613A (en) | 1988-05-23 | 1988-05-23 | Substrate for discrete devices and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01293613A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142756A (en) * | 1989-10-31 | 1992-09-01 | Naoetsu Electronics Company | Apparatus for loading and re-slicing semiconductor wafer |
| US5154873A (en) * | 1989-12-11 | 1992-10-13 | Naoetsu Electronics Company | Method and apparatus for mounting slice base on wafer of semiconductor |
| US5472909A (en) * | 1993-05-21 | 1995-12-05 | Naoetsu Electronics Company | Method for the preparation of discrete substrate plates of semiconductor silicon wafer |
| US5489555A (en) * | 1992-04-16 | 1996-02-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a photoelectric conversion device |
| US5758537A (en) * | 1992-03-10 | 1998-06-02 | Texas Instruments, Incorporated | Method and apparatus for mounting, inspecting and adjusting probe card needles |
| JP2004158526A (en) * | 2002-11-05 | 2004-06-03 | Toshiba Ceramics Co Ltd | Substrate for discrete element and its manufacturing method |
| JP2009130076A (en) * | 2007-11-22 | 2009-06-11 | Covalent Materials Corp | Method for manufacturing diffusion wafer and the diffusion wafer |
-
1988
- 1988-05-23 JP JP88126591A patent/JPH01293613A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142756A (en) * | 1989-10-31 | 1992-09-01 | Naoetsu Electronics Company | Apparatus for loading and re-slicing semiconductor wafer |
| US5154873A (en) * | 1989-12-11 | 1992-10-13 | Naoetsu Electronics Company | Method and apparatus for mounting slice base on wafer of semiconductor |
| US5758537A (en) * | 1992-03-10 | 1998-06-02 | Texas Instruments, Incorporated | Method and apparatus for mounting, inspecting and adjusting probe card needles |
| US5890390A (en) * | 1992-03-10 | 1999-04-06 | Silicon Systems, Inc. | Method and apparatus for mounting, inspecting and adjusting probe card needles |
| US5489555A (en) * | 1992-04-16 | 1996-02-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a photoelectric conversion device |
| US5472909A (en) * | 1993-05-21 | 1995-12-05 | Naoetsu Electronics Company | Method for the preparation of discrete substrate plates of semiconductor silicon wafer |
| EP0709878A1 (en) * | 1994-10-24 | 1996-05-01 | Naoetsu Electronics Company | Method for the preparation of discrete substrate plates of semiconductor silicon wafer |
| JP2004158526A (en) * | 2002-11-05 | 2004-06-03 | Toshiba Ceramics Co Ltd | Substrate for discrete element and its manufacturing method |
| JP2009130076A (en) * | 2007-11-22 | 2009-06-11 | Covalent Materials Corp | Method for manufacturing diffusion wafer and the diffusion wafer |
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