JPH01288783A - Test circuit - Google Patents

Test circuit

Info

Publication number
JPH01288783A
JPH01288783A JP63119046A JP11904688A JPH01288783A JP H01288783 A JPH01288783 A JP H01288783A JP 63119046 A JP63119046 A JP 63119046A JP 11904688 A JP11904688 A JP 11904688A JP H01288783 A JPH01288783 A JP H01288783A
Authority
JP
Japan
Prior art keywords
circuit
terminal
selector
signal
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63119046A
Other languages
Japanese (ja)
Inventor
Teruo Matsuba
松葉 輝生
Shigeaki Nagakubo
長久保 重明
Nobuhiro Yamashita
山下 信浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP63119046A priority Critical patent/JPH01288783A/en
Publication of JPH01288783A publication Critical patent/JPH01288783A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To enable the detection of a fault without increasing the number of terminals, by a method wherein an arbitrary number of output terminals connected to a gate to be tested of a semiconductor integrated circuit are switched over according to an external instruction to be connected selectively to an output terminal. CONSTITUTION:A clock input terminal 3 of a counter circuit 4 is connected to an arbitrary internal clock signal terminal, and based on the clock signal thereof, the circuit 4 is made to operate. Based on selector control signals 51-5n from this circuit 4, a selector circuit 2 switches over input terminals 11-1m thereof. Then, an output signal of an internal gate of a semiconductor integrated circuit connected to the switched input terminal is outputted sequentially to an external output terminal 6. A fault of the internal gate is detected from a signal of this terminal 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の試験回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a test circuit for semiconductor integrated circuits.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路において故障検出率を向上させる
ために、試験パターンでの向上のはカー、内部ゲートの
信号の変化が外部出力端子の信号の変化として現れない
場合は、その内部ゲートの出力を故障検出用の外部出力
端子と接続することにより故障検出率を向上させていた
Conventionally, in order to improve the failure detection rate in semiconductor integrated circuits, the test pattern has been improved using a test pattern, and if a change in the signal at an internal gate does not appear as a change in the signal at the external output terminal, the output of the internal gate is The failure detection rate was improved by connecting to an external output terminal for failure detection.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体集積回路における故障検出回路は
、内部ゲートの信号変化が外部出力端子の信号変化とし
て現れない内部ゲートが複数ある場合には、故障検出用
の外部出力端子が多数必要となり、集積回路全体の端子
数を増加させることとなり、又端子数制限により故障検
出のできない内部ゲートがでてくる可能性があった。
The fault detection circuit in the conventional semiconductor integrated circuit described above requires a large number of external output terminals for fault detection when there are multiple internal gates in which a signal change at an internal gate does not appear as a signal change at an external output terminal. This increases the number of terminals in the entire circuit, and due to the limited number of terminals, there is a possibility that some internal gates may become undetectable.

本発明の目的は前記課題を解消した試験回路を提供する
ことにある。
An object of the present invention is to provide a test circuit that solves the above problems.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため、本発明に係る試験回路におい
ては、半導体集積回路の被試験ゲートに接続される任意
の数の入力端子を外部指令に基いて切替えてこれを出力
端子に選択的に接続するセレクタ回路と、クロック信号
の入力により電気的なセレクタ制御信号を外部指令とし
て前記セレクタ回路に出力するカウンタとを有するもの
である。
In order to achieve the above object, the test circuit according to the present invention switches an arbitrary number of input terminals connected to the gate under test of a semiconductor integrated circuit based on an external command and selectively connects them to output terminals. and a counter that outputs an electrical selector control signal as an external command to the selector circuit in response to input of a clock signal.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

図において、2はセレクタ回路、4はカウンタ回路であ
る。
In the figure, 2 is a selector circuit, and 4 is a counter circuit.

セレクタ回路2の入力端子1.〜1.は、内部ゲート出
力信号の変化が外部出力端子信号の変化として現れない
半導体集積回路の被試験内部ゲートに接続され、セレク
タ回路2の出力端子6は故障検出用外部出力端子に接続
される。さらにセレクタ回路2は外部指令に基いて入力
端子11〜1、を切替えてこれを出力端子6に選択的に
接続する機能を有する。カウンタ回路4のクロック入力
端子3は任意の内部クロック信号端子に接続され、その
クロック信号に基いてセレクタ回路2の入力端子1、〜
1.を切替える外部指令としてのセレクタ制御信号5.
〜5.をセレクタ回路2に出力する。
Input terminal 1 of selector circuit 2. ~1. is connected to the internal gate under test of the semiconductor integrated circuit in which a change in the internal gate output signal does not appear as a change in the external output terminal signal, and the output terminal 6 of the selector circuit 2 is connected to an external output terminal for failure detection. Furthermore, the selector circuit 2 has a function of switching the input terminals 11 to 1 based on an external command and selectively connecting them to the output terminal 6. The clock input terminal 3 of the counter circuit 4 is connected to an arbitrary internal clock signal terminal, and based on the clock signal, the input terminals 1, .
1. Selector control signal as an external command to switch5.
~5. is output to the selector circuit 2.

実施例において、内部クロック信号により、カウンタ回
路4が動作すると、該カウンタ回路4からのセレクタ制
御信号5、〜5.に基いてセレクタ回路2はその入力端
子1、〜1.を切替えてその切替えた入力端子に接続さ
れている半導体集積回路の内部ゲートの出力信号を順次
外部出力端子6に出力する。この出力端子6からの信号
により、内部ゲートの故障検出を行う。
In the embodiment, when the counter circuit 4 operates according to the internal clock signal, the selector control signals 5, to 5 . Based on this, the selector circuit 2 selects its input terminals 1, -1 . is switched, and the output signals of the internal gates of the semiconductor integrated circuits connected to the switched input terminals are sequentially outputted to the external output terminal 6. The signal from this output terminal 6 is used to detect a failure in the internal gate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明を半導体集積回路に応用した
場合、出力端子数を1端子増加させるだけで故障検出率
を向上させることができる効果を有する。
As explained above, when the present invention is applied to a semiconductor integrated circuit, it is possible to improve the failure detection rate by simply increasing the number of output terminals by one terminal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図である。 11〜11・・・セレクタ回路の入力端子2・・・セレ
クタ回路   3・・・タロツク入力端子4・・・カウ
ンタ回路 5、〜5.・・・セレクタ制御信号 6・・・セレクタの出力端子 特許出願人  日本電気株式会社 日本電気エンジニアリング株式会社
FIG. 1 is a circuit diagram showing an embodiment of the present invention. 11-11...Input terminal of selector circuit 2...Selector circuit 3...Tarlock input terminal 4...Counter circuit 5, -5. ...Selector control signal 6...Selector output terminal Patent applicant: NEC Corporation NEC Corporation Engineering Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体集積回路の被試験ゲートに接続される任意
の数の入力端子を外部指令に基いて切替えてこれを出力
端子に選択的に接続するセレクタ回路と、クロック信号
の入力により電気的なセレクタ制御信号を外部指令とし
て前記セレクタ回路に出力するカウンタとを有すること
を特徴とする試験回路。
(1) A selector circuit that switches an arbitrary number of input terminals connected to the gate under test of a semiconductor integrated circuit based on an external command and selectively connects them to output terminals, and an electrical A test circuit comprising: a counter that outputs a selector control signal as an external command to the selector circuit.
JP63119046A 1988-05-16 1988-05-16 Test circuit Pending JPH01288783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63119046A JPH01288783A (en) 1988-05-16 1988-05-16 Test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63119046A JPH01288783A (en) 1988-05-16 1988-05-16 Test circuit

Publications (1)

Publication Number Publication Date
JPH01288783A true JPH01288783A (en) 1989-11-21

Family

ID=14751583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63119046A Pending JPH01288783A (en) 1988-05-16 1988-05-16 Test circuit

Country Status (1)

Country Link
JP (1) JPH01288783A (en)

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