JPH01288120A - Message receiver - Google Patents
Message receiverInfo
- Publication number
- JPH01288120A JPH01288120A JP63117089A JP11708988A JPH01288120A JP H01288120 A JPH01288120 A JP H01288120A JP 63117089 A JP63117089 A JP 63117089A JP 11708988 A JP11708988 A JP 11708988A JP H01288120 A JPH01288120 A JP H01288120A
- Authority
- JP
- Japan
- Prior art keywords
- address
- message
- ram
- order
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- 238000010586 diagram Methods 0.000 description 4
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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Landscapes
- Small-Scale Networks (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はアドレス信号とその後に続くメツセージ信号を
受信して表示するメツセージ受信機に関し、特に受信、
格納されたメツセージの表示方式の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a message receiver that receives and displays an address signal and a subsequent message signal, and particularly relates to a message receiver that receives and displays an address signal and a subsequent message signal.
Related to improving the display method of stored messages.
従来、この種のメツセージ受信機（表示機能付選択呼出
信号受信機を含む）においては、 ＲＡＭに格納された
メツセージを、格納されている順番または受信した時間
の逆順に表示する機能を有する。Conventionally, this type of message receiver (including a selective call signal receiver with a display function) has a function of displaying messages stored in a RAM in the order in which they were stored or in the reverse order of the time they were received.
第３図は従来のメツセージ受信機におけるメツセージ表
示順序の例を示す。FIG. 3 shows an example of message display order in a conventional message receiver.
上述した従来のメツセージ受信機（例えば。The conventional message receivers mentioned above (e.g.
ＮｚｃｆＲＲ３Ｄ４−７Ａ受信機）においては、ＲＡＭ
に格納されたメツセージは第３図のようにアドレスに関
係なく受信した時間の逆順に表示される。・複数の異な
るアドレスは通常、異なる種類の情報源に対応する。例
えば、アドレスＡは会社からの業務メツセージの送信に
使われ、アドレスＢは自宅からの私的メソセージ、アド
レスＣは相場２通貨レート等の情報、アドレスＤはスポ
ーツ試合の速報等に使う場合がある。In the NzcfRR3D4-7A receiver), the RAM
Messages stored in Messages are displayed in the reverse order of the time they were received, regardless of the address, as shown in Figure 3. - Different addresses typically correspond to different types of information sources. For example, address A may be used to send business messages from work, address B may be used for private messages from home, address C may be used for information such as the market rate of two currencies, and address D may be used for breaking news on sports matches, etc. .
このような使用例においては受信した順序ではなく、情
報源（すなわちアドレス）毎に分類してメツセージを読
み出したいという要求があるが、従来の受信機ではこの
ような要求を満足することはできない。In such use cases, there is a desire to read out messages by classifying them by information source (i.e., address) rather than by the order in which they were received, but conventional receivers cannot satisfy this requirement.
本発明のメツセージ受信機は、複数の異なるアドレスと
その後に続くメツセージ信号を受信する受信部と、受信
したアドレスとメツセージの対を格納するＲＡＭと、前
記アドレスとメツセージの対を表示する表示部と、前記
複数のアドレスの内の１つを選択する第１のスイッチと
。The message receiver of the present invention includes a receiving section that receives a plurality of different addresses and subsequent message signals, a RAM that stores the received address and message pairs, and a display section that displays the address and message pairs. , a first switch for selecting one of the plurality of addresses.
前記ＲＡＭに格納された複数のメツセージの内の１つを
選択する第２のスイッチと、前記各スイッチにより選択
されたアドレスとメツセー・ジの対を前記ＲＡＭより読
み出し前記表示部に表示させる制御部とを有する。a second switch that selects one of a plurality of messages stored in the RAM; and a control unit that reads out the address and message pair selected by each switch from the RAM and displays it on the display unit. and has.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のブロック図であり、受信部
１０１． ＲＡＭ１０２．表示部１０３．アドレス選択
用の第１のスイッチ１０４．メツセージ選択用の第２の
スイッチ１０５．及びＣＰＵによる制御部１０６を有す
る。受信部１０１は復調部１０７．デコーダ部１０８及
び複数のアドレスを格納したＩＤ−ＲＯＭ １０９から
成る。復調部１０７は受信した無線信号を復調してデー
タ信号Ｘ、を出力する。FIG. 1 is a block diagram of an embodiment of the present invention, in which a receiving section 101. RAM102. Display section 103. First switch 104 for address selection. Second switch 105 for message selection. and a control unit 106 using a CPU. The receiving section 101 includes a demodulating section 107. It consists of a decoder section 108 and an ID-ROM 109 storing a plurality of addresses. The demodulator 107 demodulates the received radio signal and outputs a data signal X.
デコーダ部１０８はデータ信号Ｘ、とＩＤ −ＲＯＭ
１０９より読み出した自己アドレスとを比較し、一致し
た時、そのアドレスとそれに続くメツセージデータｘ３
とを制御部１０６に送る。The decoder unit 108 receives the data signal X and the ID-ROM.
Compare the self address read from 109, and if they match, read that address and the following message data x3
and is sent to the control unit 106.
表示部１０３はＬＣＤドライバ１１０とＬＣＤ １１１
により構成される。The display unit 103 includes an LCD driver 110 and an LCD 111
Consisted of.
上述の各ブロックは９例えば次のようなＮＥＣ製ＬＳＩ
、富士連装ＬＳＩを使って実現できる。Each of the above blocks is 9, for example, the following NEC LSI
, can be realized using Fuji Renso LSI.
ＲＡＭ １０２ ： μＰＤ４４９ＧＩＤ−
ＲＯＭ１０９ ：ＭＢ８５４１ＰＬＣＤドライバ１
１０：μＰＤ７２２８Ｇ次に９本発明の動作について説
明する。RAM 102: μPD449GID-
ROM109: MB8541PLCD driver 1
10: μPD7228G Next, the operation of the present invention will be explained.
受信部１０１は受信した無線信号を復調し、その受信デ
ータ信号中に自分のアドレスを検出すると、そのアドレ
スおよびその後に続くメツセージデータを制御部１０６
に出力する。なお、データ信号は９例えばＣＣＩＲＲＰ
ＣＮＩＩの指定フォーマットに従っているものとする。The receiving unit 101 demodulates the received radio signal, and when it detects its own address in the received data signal, the receiving unit 101 transmits the address and subsequent message data to the control unit 106.
Output to. Note that the data signal is 9, for example CCIRRP.
It is assumed that the format specified by CNII is followed.
制御部１０６は受信したアドレスとメツセージの対を第
２図に示すように順番にＲＡＭ１０２に格納する。ここ
までは従来と同じである。The control unit 106 sequentially stores the received address and message pairs in the RAM 102 as shown in FIG. Everything up to this point is the same as before.
アドレスをＡ Ｉ Ｂ＋ ｃ ＋ ｎ （４種）とする
時、アドレス選択用の第１のスイッチ１０４が押される
と。When the address is A I B + c + n (4 types), the first switch 104 for address selection is pressed.
制御部１０６はＡ→Ｂ→Ｃ→Ｄ→Ａ→・・・の順にアド
レスを選択し、そのアドレスにおける最新のメツセージ
をＲＡＭ１０２よシ読み出して表示部１０３に表示する
。The control section 106 selects an address in the order of A→B→C→D→A→ .
一方、メツセージ選択用の第２のスイッチ１０５が押さ
れると、制御部１０６は選択されているアドレスの内で
最新のメソセージから順番にＲＡＭ１０２より読み出し
て表示部１０３に表示させる。On the other hand, when the second switch 105 for message selection is pressed, the control section 106 sequentially reads messages from the RAM 102 starting from the newest among the selected addresses and displays them on the display section 103.
第２図には第３図と同じ順序でメツセージを受信した場
合、アドレス選択用の第１のスイッチ１０４操作時のア
ドレス、メツセージ表示順序および、アドレスＡが選択
されている状態でメツセージ選択用の第２のスイッチ１
０５を操作した時のアドレス、メツセージ表示順序につ
いて示している。FIG. 2 shows the address and message display order when the first switch 104 for address selection is operated, and the message selection order when address A is selected when messages are received in the same order as in FIG. second switch 1
The address and message display order when operating 05 are shown.
以上説明したように本発明は、アドレス選択用のスイッ
チ操作により選択されたアドレスのメツセージの内最新
のメツセージを表示し、メツセージ選択用のスイッチ操
作により選択されているアドレスのメツセージを最新の
メツセージから順に表示することができるので、複数の
アドレス（すなわち情報源）毎に分類してメツセージを
表示し読み出すことができるという効果がある。As explained above, the present invention displays the latest message among the messages of the address selected by operating the switch for selecting an address, and displays the message of the address selected by operating the switch for message selection from the latest message. Since messages can be displayed in order, messages can be displayed and read out after being classified by a plurality of addresses (that is, information sources).
第１図は本発明の一実施例のブロック図、第２図は本発
明におけるアドレス、メツセージ対のＲＡＭ格納順序、
読み出し表示順序を説明するための図、第３図は従来例
におけるアドレス。
メツセージ対のＲＡＭ格納順序、読み出し表示順序を説
明するだめの図。
１０１・・・受信部、１０２・・・ＲＡＭ、１０３・・
・表示部。
１０４・・・アドレス選択用の第１のスイッチ、１０５
・・・メツセージ選択用の第２のスイッチ、１０６・・
・制御部＋ ”１・・・受信データ＋ ｘ２・・・自己
アドレス指定データ＋ｘ３・・・受信アドレス、メツセ
ージ。
Ｘ、・・・アドレス、メツセージ＋ ｘ５・・・表示デ
ータ。
第１図
ノ０２
俟
スツ
＋ｌか
ンダ
唸
巳−〜η寸Ｌｒ＞℃トＱ
第３図
ＲＡＭ内容FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows the RAM storage order of address and message pairs in the present invention.
A diagram for explaining the readout and display order, FIG. 3 is an address in a conventional example. FIG. 4 is a diagram for explaining the order of storing message pairs in RAM and the order of reading and displaying them. 101... Receiving section, 102... RAM, 103...
・Display section. 104... first switch for address selection, 105
...Second switch for message selection, 106...
・Control unit + "1... Received data + x2... Self-address specification data + x3... Received address, message. X,... Address, message + x5... Display data. Figure 1 No. 02 Stu+lKanda Umi-～ηDimensionLr＞℃toQ Figure 3 RAM contents
Claims (1)
ジ信号を受信する受信部と、受信したアドレスとメッセ
ージの対を格納するＲＡＭと、前記アドレスとメッセー
ジの対を表示する表示部と、前記複数のアドレスの内の
１つを選択する第１のスイッチと、前記ＲＡＭに格納さ
れた複数のメッセージの内の１つを選択する第２のスイ
ッチと、前記各スイッチにより選択されたアドレスとメ
ッセージの対を前記ＲＡＭより読み出し前記表示部に表
示させる制御部とを含むことを特徴とするメッセージ受
信機。1. A receiving unit that receives a plurality of different address signals and subsequent message signals, a RAM that stores received address and message pairs, a display unit that displays the address and message pairs, and the plurality of addresses. a first switch that selects one of the plurality of messages stored in the RAM, a second switch that selects one of the plurality of messages stored in the RAM, and a pair of address and message selected by each of the switches. A message receiver comprising: a control unit that reads data from the RAM and causes the message to be displayed on the display unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63117089A JP2591061B2 (en) | 1988-05-16 | 1988-05-16 | Message receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63117089A JP2591061B2 (en) | 1988-05-16 | 1988-05-16 | Message receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01288120A true JPH01288120A (en) | 1989-11-20 |
| JP2591061B2 JP2591061B2 (en) | 1997-03-19 |
Family
ID=14703124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63117089A Expired - Lifetime JP2591061B2 (en) | 1988-05-16 | 1988-05-16 | Message receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2591061B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03235435A (en) * | 1990-02-09 | 1991-10-21 | Nec Corp | Radio selective call signal receiver provided with display function |
| JPH04257127A (en) * | 1991-02-08 | 1992-09-11 | Nec Corp | Selective call receiver |
| EP0675467A1 (en) * | 1994-03-22 | 1995-10-04 | Nec Corporation | Selective calling receiver with message display function |
| EP0680024A1 (en) * | 1994-04-28 | 1995-11-02 | Nec Corporation | Radio selective calling receiver |
| US5936548A (en) * | 1996-09-13 | 1999-08-10 | Nec Corporation | Radio paging receiver capable of readily confirming a state of a non read message |
-
1988
- 1988-05-16 JP JP63117089A patent/JP2591061B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03235435A (en) * | 1990-02-09 | 1991-10-21 | Nec Corp | Radio selective call signal receiver provided with display function |
| JPH04257127A (en) * | 1991-02-08 | 1992-09-11 | Nec Corp | Selective call receiver |
| EP0675467A1 (en) * | 1994-03-22 | 1995-10-04 | Nec Corporation | Selective calling receiver with message display function |
| US5686900A (en) * | 1994-03-22 | 1997-11-11 | Nec Corporation | Selective calling receiver with message display function |
| EP0680024A1 (en) * | 1994-04-28 | 1995-11-02 | Nec Corporation | Radio selective calling receiver |
| JPH07298327A (en) * | 1994-04-28 | 1995-11-10 | Nec Shizuoka Ltd | Radio selective call receiver and its display method |
| US5629688A (en) * | 1994-04-28 | 1997-05-13 | Nec Corporation | Radio selective calling receiver storing messages based on sending-group names |
| CN1076569C (en) * | 1994-04-28 | 2001-12-19 | 日本电气株式会社 | Radio selective calling receiver |
| US5936548A (en) * | 1996-09-13 | 1999-08-10 | Nec Corporation | Radio paging receiver capable of readily confirming a state of a non read message |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2591061B2 (en) | 1997-03-19 |
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