JPH01286459A - Protecting device for semiconductor integrated circuit - Google Patents
Protecting device for semiconductor integrated circuitInfo
- Publication number
- JPH01286459A JPH01286459A JP11458488A JP11458488A JPH01286459A JP H01286459 A JPH01286459 A JP H01286459A JP 11458488 A JP11458488 A JP 11458488A JP 11458488 A JP11458488 A JP 11458488A JP H01286459 A JPH01286459 A JP H01286459A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- insulating film
- type
- substrate
- low concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 abstract description 23
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 6
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の保護装置に関し、特に入力回
路等に設けられる保護抵抗の構成に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a protection device for a semiconductor integrated circuit, and particularly to the configuration of a protection resistor provided in an input circuit or the like.
従来、この種の保護抵抗は、第３図のように、例えばＮ
型半導体基板ｌの表面の厚いフィールド絶縁膜３の上に
、ポリシリコン等からなる抵抗体５を形成し、これを被
覆する眉間絶縁膜４の窓を通してその一端を集積回路の
端子に繋がる配線６ａに接続し、他端を集積回路の保護
ダイオード及び内部回路に繋がる配線６ｂに接続してい
る。Conventionally, this type of protective resistor has been used, for example, as shown in FIG.
A resistor 5 made of polysilicon or the like is formed on the thick field insulating film 3 on the surface of the type semiconductor substrate l, and a wiring 6a is connected to one end of the resistor 5 through a window of the glabellar insulating film 4 to a terminal of the integrated circuit. The other end is connected to a wiring 6b connected to a protection diode of the integrated circuit and an internal circuit.
この構成では、端子に正の静電気が印加されると、その
電荷は配線６ａから抵抗体５に至り、この抵抗体５で減
衰され、かつ配線６ｂ及び保護ダイオード（図示せず）
を経由して基板１へと放電され、内部回路を保護するこ
とは言うまでもない。In this configuration, when positive static electricity is applied to the terminal, the electric charge reaches the resistor 5 from the wiring 6a, is attenuated by the resistor 5, and is connected to the wiring 6b and the protective diode (not shown).
Needless to say, it is discharged to the board 1 via the circuit board 1, thereby protecting the internal circuitry.
また、他の例としては、第４図のように、Ｎ型半導体基
板ｌと逆導電型のＰ型拡散層１０を形成し、この拡散抵
抗を保護抵抗として構成したものが提案されている。な
お、第３図と均等な部分には同一符号を付しである。ま
た、符号１１はＰ型ウェルである。As another example, as shown in FIG. 4, it has been proposed to form a P-type diffusion layer 10 of a conductivity type opposite to that of the N-type semiconductor substrate 1, and configure this diffused resistor as a protective resistor. Note that parts equivalent to those in FIG. 3 are given the same reference numerals. Further, reference numeral 11 is a P-type well.
〔発明が解決しようとする課題］
上述した従来の保護抵抗のうち、第３図のポリシリコン
を抵抗体として構成したものでは、抵抗体５の下側はフ
ィールド絶縁膜３を介してＮ型基板１となっているため
、正の電荷が抵抗体５に印加されると表面は蓄積状態と
なり、加わった電圧は全てフィールド絶縁膜３に印加さ
れる。通常、このフィールド絶縁膜３は、５０００〜１
００００人の膜厚で４００Ｖ〜５００■の耐圧であるた
め、この高電圧の印加によって絶縁破壊され、抵抗体５
が基板１と短絡する事故が生じるという問題がある。[Problems to be Solved by the Invention] Among the conventional protective resistors described above, in the one configured with polysilicon as a resistor as shown in FIG. 1, so when a positive charge is applied to the resistor 5, the surface becomes in an accumulation state, and all the applied voltage is applied to the field insulating film 3. Usually, this field insulating film 3 has a thickness of 5000 to 1
Since it has a withstand voltage of 400V to 500cm with a film thickness of 0,000 people, application of this high voltage causes dielectric breakdown and the resistor 5
There is a problem in that an accident may occur in which there is a short circuit with the substrate 1.
また、第４図の構成では、拡散抵抗としてのＰ型拡散層
１０自体がＮ型基板１とＰＮ接合を形成するため、放電
時の過大電流による熱的な接合破壊、及び放電時の抵抗
値の見積もりがＰＮダイオードと抵抗の分布定数回路と
なるため、煩雑となり、最適な設計が困難になるという
問題がある。In addition, in the configuration shown in FIG. 4, since the P-type diffusion layer 10 itself as a diffused resistor forms a PN junction with the N-type substrate 1, thermal junction breakdown due to excessive current during discharge and resistance value during discharge may occur. Since the estimation of is based on a distributed constant circuit of a PN diode and a resistor, it becomes complicated and there is a problem that it becomes difficult to design an optimal design.
本発明は抵抗値の設定が容易であるとともに、高電圧が
印加されても絶縁破壊が生じることのない″＋導体集積
回路の保護装置を提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a protection device for a conductor integrated circuit in which resistance values can be easily set and dielectric breakdown does not occur even when a high voltage is applied.
本発明の半導体集積回路の保護装置は、一導電型の半導
体基板表面の絶縁膜上に形成し、かつ−端を集積回路の
端子に接続した抵抗体の下側の基板に、抵抗体の一端側
から少なくとも抵抗体の１７２以上の領域にわたって逆
導電型の低濃度不純物層を形成し、かつこの低濃度不純
物層をフローティング電位に保持した構成としでいる。The protection device for a semiconductor integrated circuit of the present invention is formed on an insulating film on the surface of a semiconductor substrate of one conductivity type, and one end of the resistor is attached to a substrate below the resistor whose negative end is connected to a terminal of the integrated circuit. A low concentration impurity layer of the opposite conductivity type is formed over at least 172 or more regions of the resistor from the side, and this low concentration impurity layer is held at a floating potential.
上述した構成では、逆導電型の低濃度不純物層の表面に
形成される反転層と、この低濃度不純物層と基板とのＰ
Ｎ接合により、抵抗体と基板との間の絶縁膜に印加され
る電界を緩和し、絶縁膜の破壊電圧を向上させる。In the above configuration, an inversion layer is formed on the surface of the low concentration impurity layer of the opposite conductivity type, and a P between the low concentration impurity layer and the substrate.
The N-junction relieves the electric field applied to the insulating film between the resistor and the substrate and improves the breakdown voltage of the insulating film.
［実施例］ 次に、本発明を図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
図において、シリコン等のＮ型基板１の上には厚いフィ
ールド絶縁膜３を形成し、この上にポリシリコンを所要
パターンに形成して抵抗体５を構成している。そして、
この抵抗体５を被覆する層間絶縁膜４の窓を通して抵抗
体５の一端に配線６ａを、他端に配線６ｂを夫々接続し
ている。更に、前記Ｎ型基板１には、前記抵抗体５の領
域を全て包含する形で、低濃度（１０”〜］、０”ｃｍ
−’）にＰ型不純物を拡散させたＰ型ウェル２を形成し
、このＰ型ウェル２の電位は、どこからも供給されない
フローティング状態としている。In the figure, a thick field insulating film 3 is formed on an N-type substrate 1 made of silicon or the like, and a resistor 5 is constructed by forming polysilicon in a desired pattern on this film. and,
A wiring 6a is connected to one end of the resistor 5, and a wiring 6b is connected to the other end of the resistor 5 through a window in the interlayer insulating film 4 covering the resistor 5. Furthermore, the N-type substrate 1 is coated with a low concentration (10"~), 0"cm thick, covering the entire area of the resistor 5.
A P-type well 2 in which P-type impurities are diffused is formed in the P-type well 2 (-'), and the potential of this P-type well 2 is in a floating state where it is not supplied from anywhere.
なお、前記フィールド絶縁膜３の膜厚は、抵抗体５の下
側で５０００〜１ｏｏｏｏλ程度に設定している。The thickness of the field insulating film 3 below the resistor 5 is set to about 5000 to 100λ.
また、前記配線６ａは集積回路の端子へ接続し、配線６
ｂは保護ダイオード、及び内部回路へ接続している。Further, the wiring 6a is connected to a terminal of the integrated circuit, and the wiring 6a is connected to a terminal of the integrated circuit.
b is connected to a protection diode and internal circuit.
この構成によれば、抵抗体５の抵抗値はポリシリコンの
抵抗値やパターン形状を適宜設定することにより、容易
に設定することができる。また、端子に正の静電気が印
加されたときには、その電荷は配線６ａを通して抵抗体
５の一端に至り、この抵抗体５で減衰され、更に、抵抗
体５の他端から配線６ｂを通して図外の保護ダイオード
に至り、ここで基板へと放電されることは言うまでもな
い。According to this configuration, the resistance value of the resistor 5 can be easily set by appropriately setting the resistance value and pattern shape of the polysilicon. Further, when positive static electricity is applied to the terminal, the electric charge reaches one end of the resistor 5 through the wiring 6a, is attenuated by the resistor 5, and then passes through the wiring 6b from the other end of the resistor 5 to the other end of the resistor 5. Needless to say, it reaches the protection diode, where it is discharged to the substrate.
そしてこの時、この実施例では、保護抵抗５の下にＰ型
ウェル２が形成されているので、抵抗体５に正の電荷が
印加されたときに、Ｐ型ウェル２の表面は容易に反転層
を形成する。また、Ｐ型ウェル２はＮ型基板１との間に
ＰＮ接合を形成している。このため、印加された電圧は
フィールド絶縁膜３１反転層、ＰＮ接合部に分圧され、
結果と゛してフィールド絶縁膜３の電界が緩和され、フ
ィールド絶縁膜３の破壊電圧を向上することができる。At this time, in this embodiment, the P-type well 2 is formed under the protective resistor 5, so when a positive charge is applied to the resistor 5, the surface of the P-type well 2 is easily reversed. form a layer. Further, the P-type well 2 forms a PN junction with the N-type substrate 1. Therefore, the applied voltage is divided into the inversion layer of the field insulating film 31 and the PN junction,
As a result, the electric field in the field insulating film 3 is relaxed, and the breakdown voltage of the field insulating film 3 can be improved.
なお、Ｐ型ウェル２はフローティング状態にあるため、
仮にフィールド絶縁膜３が破壊した場合でも短絡不良が
生じることはない。Note that since the P-type well 2 is in a floating state,
Even if the field insulating film 3 were to break down, no short-circuit failure would occur.
なお、第１図では、Ｐ型ウェル２を抵抗体５を全て含む
領域に形成しているが、静電気放電時には抵抗体５に電
位勾配をもつため、必ずしも全領域に設ける必要はなく
、抵抗体５の一端側から１７２以上の領域にあれば十分
である。In FIG. 1, the P-type well 2 is formed in the area that includes the entire resistor 5, but since the resistor 5 has a potential gradient during electrostatic discharge, it is not necessarily necessary to provide it in the entire area, and the resistor 5 It is sufficient if the area is 172 or more from one end side of 5.
第２図は本発明の第２実施例の断面図であり、この実施
例はバイポーラ集積回路等のように、エピタキシャル層
を用いる半導体集積回路に本発明を適用した例である。FIG. 2 is a sectional view of a second embodiment of the present invention, and this embodiment is an example in which the present invention is applied to a semiconductor integrated circuit using an epitaxial layer, such as a bipolar integrated circuit.
図において、第１図と同一部分には同一符号を付しであ
る。In the figure, the same parts as in FIG. 1 are given the same reference numerals.
この実施例では、シリコン等のＰ型基板７の表面にＰ塑
成いはＮ型エピタキシャル層を成長させ、ここに各種素
子を形成しているが、フィールド絶縁膜３上に形成した
抵抗体５の下側には、絶縁用Ｐ型拡散層９によって画成
されたＮ型エピタキシャル層８を形成している。In this embodiment, a P plastic or N type epitaxial layer is grown on the surface of a P type substrate 7 made of silicon, etc., and various elements are formed there. An N-type epitaxial layer 8 defined by an insulating P-type diffusion layer 9 is formed below.
したがって、このＮ型エピタキシャル層８は第１実施例
のＰ型ウェル２と等価な働きをし、フィールド絶縁膜３
の破壊電圧を向上する。Therefore, this N-type epitaxial layer 8 functions equivalently to the P-type well 2 of the first embodiment, and the field insulating film 3
Improves breakdown voltage.
以上説明したように本発明は、絶縁膜上に形成した抵抗
体の下側の基板に、所要領域にわたって逆導電型の低濃
度不純物層を形成し、かつこの低濃度不純物層をフロー
ティング電位に保持しているので、この低濃度不純物層
の表面に形成される反転層と、この低濃度不純物層と基
板とのＰＮ接合により、抵抗体と基板との間の絶縁膜に
印加される電界を緩和し、絶縁膜の破壊電圧を向上させ
て静電破壊強度の高い保護抵抗を供給できる。As explained above, the present invention forms a low concentration impurity layer of the opposite conductivity type over a required region on the substrate below the resistor formed on the insulating film, and maintains this low concentration impurity layer at a floating potential. Therefore, the electric field applied to the insulating film between the resistor and the substrate is alleviated by the inversion layer formed on the surface of this low concentration impurity layer and the PN junction between this low concentration impurity layer and the substrate. However, it is possible to improve the breakdown voltage of the insulating film and provide a protective resistor with high electrostatic breakdown strength.
第１図は本発明の第１実施例の要部の縦断面図、第２図
は本発明の第２実施例の縦断面図、第３図は従来の保護
装置の一例の縦断面図、第４図は従来の保護装置の他の
例の縦断面図である。
１・・・Ｎ型基板、２・・・Ｐ型ウェル、３・・・フィ
ールド絶縁膜、４・・・層間絶縁膜、５・・・抵抗体、
６ａ。
６ｂ・・・配線、７・・・Ｐ型基板、８・・・Ｎ型エピ
タキシャル層、９・・・絶縁用Ｐ型拡散層、１０・・・
Ｐ型拡散層（拡散抵抗）、１１・・・Ｐ型ウェル。
第１図
第２図
第３図
第４図FIG. 1 is a vertical cross-sectional view of the main part of the first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of the second embodiment of the present invention, and FIG. 3 is a vertical cross-sectional view of an example of a conventional protection device. FIG. 4 is a longitudinal sectional view of another example of a conventional protection device. DESCRIPTION OF SYMBOLS 1... N-type substrate, 2... P-type well, 3... Field insulating film, 4... Interlayer insulating film, 5... Resistor,
6a. 6b... Wiring, 7... P type substrate, 8... N type epitaxial layer, 9... P type diffusion layer for insulation, 10...
P-type diffusion layer (diffusion resistance), 11...P-type well. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
しての抵抗体を形成し、この抵抗体の一端を集積回路の
端子に接続し、他端を内部回路に接続した保護装置にお
いて、前記抵抗体の下側の基板には、抵抗体の一端側か
ら少なくとも抵抗体の１／２以上の領域にわたって逆導
電型の低濃度不純物層を形成し、かつこの低濃度不純物
層をフローティング電位に保持したことを特徴とする半
導体集積回路の保護装置。1. In a protection device in which a resistor as a protective resistor is formed on an insulating film on the surface of a semiconductor substrate of one conductivity type, one end of this resistor is connected to a terminal of an integrated circuit, and the other end is connected to an internal circuit, A low concentration impurity layer of the opposite conductivity type is formed on the substrate below the resistor over at least 1/2 or more of the resistor from one end side of the resistor, and this low concentration impurity layer is set to a floating potential. A protection device for a semiconductor integrated circuit, which is characterized by holding a semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11458488A JPH01286459A (en) | 1988-05-13 | 1988-05-13 | Protecting device for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11458488A JPH01286459A (en) | 1988-05-13 | 1988-05-13 | Protecting device for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01286459A true JPH01286459A (en) | 1989-11-17 |
Family
ID=14641508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11458488A Pending JPH01286459A (en) | 1988-05-13 | 1988-05-13 | Protecting device for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01286459A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600176A (en) * | 1992-05-26 | 1997-02-04 | Texas Instruments Deustchland Gmbh | Integrated voltage divider |
| US8269312B2 (en) * | 2008-06-05 | 2012-09-18 | Rohm Co., Ltd. | Semiconductor device with resistive element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144454A (en) * | 1984-08-09 | 1986-03-04 | Fujitsu Ltd | Semiconductor device |
| JPS62155548A (en) * | 1985-12-27 | 1987-07-10 | Nec Corp | Electrostatic protective circuit element for semiconductor integrated circuit |
-
1988
- 1988-05-13 JP JP11458488A patent/JPH01286459A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144454A (en) * | 1984-08-09 | 1986-03-04 | Fujitsu Ltd | Semiconductor device |
| JPS62155548A (en) * | 1985-12-27 | 1987-07-10 | Nec Corp | Electrostatic protective circuit element for semiconductor integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600176A (en) * | 1992-05-26 | 1997-02-04 | Texas Instruments Deustchland Gmbh | Integrated voltage divider |
| US8269312B2 (en) * | 2008-06-05 | 2012-09-18 | Rohm Co., Ltd. | Semiconductor device with resistive element |
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