JPH0128543B2 - - Google Patents
Info
- Publication number
- JPH0128543B2 JPH0128543B2 JP56051477A JP5147781A JPH0128543B2 JP H0128543 B2 JPH0128543 B2 JP H0128543B2 JP 56051477 A JP56051477 A JP 56051477A JP 5147781 A JP5147781 A JP 5147781A JP H0128543 B2 JPH0128543 B2 JP H0128543B2
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- voltage
- electronic circuit
- signal
- circuit according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】
本発明は、バスラインのようなデイジタル電圧
信号を伝送する信号線の負荷容量に帰因する信号
伝搬の遅延を減少させて、信号伝搬速度を速くす
る電子回路であり、特に、デイジタル集積回路中
の信号線に適用すれば極めて大きな効果のある電
子回路を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is an electronic circuit that increases the signal propagation speed by reducing the delay in signal propagation caused by the load capacitance of a signal line such as a bus line that transmits a digital voltage signal. In particular, the present invention provides an electronic circuit that is extremely effective when applied to signal lines in digital integrated circuits.
デイジタル電圧信号をのせて、離れた場所にあ
る受信ゲートにまで運ぶ信号線は少なからず配線
抵抗、容量を有し、信号の伝搬は遅れる。特に、
マイクロコンピユータのバスラインのような
MOS集積回路中の信号線は、寄生容量とゲート
入力容量が多いのと、信号線をドライブする
MOSトランジスタのインピーダンスが比較的大
きいため、信号伝搬の遅延が著しい。 A signal line that carries a digital voltage signal and carries it to a receiving gate located at a remote location has considerable wiring resistance and capacitance, which delays signal propagation. especially,
Like the bus line of a microcomputer
Signal lines in MOS integrated circuits have a large amount of parasitic capacitance and gate input capacitance, as well as the amount of power required to drive the signal lines.
Since the impedance of the MOS transistor is relatively large, the delay in signal propagation is significant.
第１図は、CMOS集積回路中の信号線の電圧
の変化を示す。時刻t1で、信号線をドライブする
ゲートの１つが低レベルから高レベルに遷移する
と、信号線の負荷容量とドライブ・ゲートの出力
インピーダンスの大きさでほぼ決まるカーブで破
線の如く、受信ゲートの入力に現われる。
CMOSゲートの閾電圧は通常、電源電圧VDDの半
分の値でこれをVTHとすると、破線のカーブが
VTHに達する時刻tBで、受信ゲートが“０”→
“１”を受けとる。即ち、信号線での伝搬遅延は
tB−t1である。 FIG. 1 shows changes in voltage on signal lines in a CMOS integrated circuit. At time t 1 , when one of the gates driving the signal line transitions from low level to high level, the receiving gate changes as shown by the broken line with a curve approximately determined by the load capacitance of the signal line and the output impedance of the drive gate. Appears in the input.
The threshold voltage of a CMOS gate is normally half the power supply voltage V DD , and if this is V TH , then the dashed curve is
At time t B when V TH is reached, the reception gate becomes “0” →
Receive “1”. In other words, the propagation delay in the signal line is
t B −t 1 .
今、電圧VLとVHとの間の電圧範囲でのみ、信
号線の電圧を急速に上昇させる機能をもつ回路が
作動したとすれば、時刻t2以後は実線のようにな
り、信号線の伝搬遅延はtA−t1にまで、即ち、tB
−tAの時間短縮される。このとき、信号線の容量
をＣ、ドライブ・ゲートの出力抵抗をＲとして、
電圧がVLからVHまでの間に、電源VDDから等価抵
抗ｒで上記容量Ｃを充電したものとすれば、t1か
らt2までと、t3以後はCRの時定数をもつ曲線であ
り、t2からt3まではＣ（Ｒｒ）の時定数をもつ
曲線となる。ただし、は並列抵抗値を示す。ｒ
をＲに比し十分に小さくとることで、この効果が
大きくなる。信号線の電圧がVLからVHの間は電
圧を急速に上昇させればよいから、上記Ｃを充電
する機能を有するものなら何でもよい。本発明の
実施例では、第２図の７に示すＰチヤネルMOS
トランジスタで電流を流し込み容量Ｃを充電して
いる。 Now, if a circuit that has the function of rapidly increasing the voltage of the signal line is activated only in the voltage range between voltages V L and V H , then after time t 2 it will look like a solid line, and the signal line will increase. The propagation delay of is up to t A −t 1 , i.e. t B
−t The time of A is reduced. At this time, the capacitance of the signal line is C, the output resistance of the drive gate is R,
Assuming that the above capacitor C is charged with the equivalent resistance r from the power supply V DD while the voltage is from V L to V H , a curve with a time constant of CR from t 1 to t 2 and from t 3 onward is obtained. From t 2 to t 3 , the curve has a time constant of C(Rr). However, indicates the parallel resistance value. r
By making R sufficiently smaller than R, this effect becomes greater. Since it is sufficient to rapidly increase the voltage between the voltage of the signal line from V L to V H , any device having the function of charging the above-mentioned C may be used. In the embodiment of the present invention, the P-channel MOS shown at 7 in FIG.
Current flows through the transistor to charge the capacitor C.
第１図では、信号線の電圧が、“０”から“１”
へ遷移の場合であるが、全く同様に、“１”から
“０”への遷移の場合には、VTHを含んでいる電
圧範囲VH〜VL（“０”→“１”の場合のVL、VHと
同じである必要は全くない）で、急速に容量Ｃを
放電して急速に電圧を下降させればよい。このと
き、“１”→“０”の伝搬遅延が大幅に短縮され
る。 In Figure 1, the voltage on the signal line changes from “0” to “1”.
Similarly, in the case of a transition from "1" to "0", the voltage range V H ~ V L (in the case of "0" → "1") that includes V TH (It is not necessary that V L and V H are the same at all), it is sufficient to rapidly discharge the capacitor C and rapidly lower the voltage. At this time, the propagation delay from "1" to "0" is significantly shortened.
第２図に本発明の実施例を示す。 FIG. 2 shows an embodiment of the present invention.
１はCMOS集積回路中の比較的負荷容量の大
きい長い信号線である。８は信号線の負荷容量を
集中定数的に表わした容量Ｃである。１０は信号
線１に信号をのせる送信側の回路のバツフアであ
る。９はバツフア１２の出力抵抗を等価的に表わ
した抵抗である。２は信号線１の電圧が電圧VH
より大か否かを検出するVH検出回路であり、信
号線１の電圧ａが、０＜ａ＜VHのときは“０”、
VH≦ａ＜VDDのときには“１”となる。３は２と
同様に信号線１の電圧が電圧VLより大か否かを
検出するVL検出回路であり、信号線１の電圧ａ
が、０＜ａ＜VLのときは“０”、VL≦ａ＜VDDの
ときには“１”となる。VLはVL＜VHの関係にあ
る。４，５，６はそれぞれ、インバータ、Ｒ−Ｓ
ラツチ、NANDゲートである。７は電流流し込
み手段であるＰチヤネルエンハンスメント型
MOSトランジスタであり、ドレインが信号線１
に接続されている。 1 is a long signal line with a relatively large load capacity in a CMOS integrated circuit. 8 is a capacitance C which represents the load capacitance of the signal line as a lumped constant. Reference numeral 10 denotes a buffer of a circuit on the transmitting side that carries a signal onto the signal line 1. 9 is a resistance equivalently representing the output resistance of the buffer 12. 2, the voltage of signal line 1 is voltage V H
This is a V H detection circuit that detects whether the voltage is greater than or not, and when the voltage a of the signal line 1 is 0<a< VH , it is "0",
It becomes "1" when V H ≦a<V DD . 3 is a V L detection circuit that detects whether the voltage of the signal line 1 is higher than the voltage V L , like 2, and the voltage a of the signal line 1 is
is “0” when 0<a<V L and “1” when V L ≦a<V DD . V L has a relationship of V L < V H. 4, 5, and 6 are inverters and R-S, respectively.
It is a latch, a NAND gate. 7 is a P channel enhancement type which is a current pouring means.
It is a MOS transistor, and the drain is connected to signal line 1.
It is connected to the.
次に、第２図の実施例の動作について簡単に説
明する。第３図に、第２図の各部Ｓ，ａ〜ｆの出
力電圧波形Ｓ，ａ〜ｆとＰチヤネル・トランジス
タ７のON、OFF状態を示す。バツフア１０の入
力Ｓが時刻t1で“０”→“１”、時刻t4で“１”
→“０”と変化した場合に対応した各部の波形で
ある。“０”→“１”の遷移途中の時刻t2からt3
の間でのみＰチヤネル・トランジスタ７がONし
ているのが分かる。第３図のタイムチヤートで
は、分かり易くするためt2〜t3の時間が現実のも
のに比らべて伸長されて、逆にその他の部分が圧
縮されて表わしてある。信号線の信号伝搬遅延
は、“０”→“１”の場合、tA−t1に短縮される。 Next, the operation of the embodiment shown in FIG. 2 will be briefly explained. FIG. 3 shows the output voltage waveforms S, a to f of each part S, a to f in FIG. 2 and the ON and OFF states of the P channel transistor 7. Input S of buffer 10 changes from “0” to “1” at time t 1 and “1” at time t 4
→ This is the waveform of each part corresponding to the case where it changes to “0”. From time t 2 to t 3 during the transition from “0” to “1”
It can be seen that the P-channel transistor 7 is ON only between In the time chart of FIG. 3, the time from t 2 to t 3 is expanded compared to the actual time, and other parts are compressed to make it easier to understand. The signal propagation delay of the signal line is shortened to t A −t 1 in the case of “0” → “1”.
このように、VH、VL検出回路、インバータ、
RSラツチ、NANDゲートにより、t2からt3の間
ＰチヤネルMOSトランジスタ７を導通させるこ
とにより、信号線１の負荷容量を急速に充電する
ことができ、信号の伝達遅延は大きく短縮され
る。 In this way, V H , V L detection circuit, inverter,
By making the P-channel MOS transistor 7 conductive from t 2 to t 3 using the RS latch and the NAND gate, the load capacitance of the signal line 1 can be rapidly charged, and the signal transmission delay can be greatly shortened.
次に、本発明の他の実施例を第４図に示す。第
４図の実施例は、第２図の実施例が、信号の
“０”→“１”伝搬を速くする効果があるのに対
して、信号の“１”→“０”伝搬を速くする効果
がある。 Next, another embodiment of the present invention is shown in FIG. The embodiment of FIG. 4 has the effect of speeding up the propagation of the signal from "0" to "1" while the embodiment of FIG. 2 speeds up the propagation of the signal from "1" to "0". effective.
第４図における１〜５，８〜１０は、前述した
第２図における１〜５，８〜１０と全く同様な物
であり、その動作も同じである。１１はVH検出
回路２の出力信号ｂとＲ−Ｓラツチ５のＱ出力ｅ
とのNORをとるNORゲートであり、１２は電流
を流し出す流出手段、すなわちNORゲート１１
の出力ｇをゲート入力信号とするＮチヤネル・エ
ンハンスメント型MOSトランジスタであつて、
そのドレインは信号線１に接続されている。 1 to 5 and 8 to 10 in FIG. 4 are exactly the same as 1 to 5 and 8 to 10 in FIG. 2 described above, and their operations are also the same. 11 is the output signal b of the V H detection circuit 2 and the Q output e of the R-S latch 5.
12 is an outflow means for flowing out current, that is, NOR gate 11
An N-channel enhancement type MOS transistor whose gate input signal is the output g of
Its drain is connected to signal line 1.
第５図に、第４図の各部Ｓ，ａ〜ｅ，ｇの出力
電圧波形Ｓ，ａ〜ｅ，ｇとＮチヤネル・トランジ
スタ１２のON、OFF状態を示す。第３図と同様
に、バツフア１０の入力Ｓが時刻t1で“０”→
“１”、時刻t4で“１”→“０”と変化した場合に
対応した各部の波形である。“１”→“０”の遷
移途中の時刻t5からt6の区間のみでＮチヤネル・
トランジスタ１２がONして、信号線１の電圧ａ
を急速に下降させていることが分かる。信号線の
信号伝搬遅延は、“１”→“０”の場合、tB−t4
に短縮される。 FIG. 5 shows the output voltage waveforms S, a to e, g of each part S, a to e, g in FIG. 4 and the ON/OFF state of the N-channel transistor 12. Similarly to FIG. 3, the input S of the buffer 10 becomes “0” at time t1 →
This is a waveform of each part corresponding to the case where the signal is "1" and changes from "1" to "0" at time t4 . N channel only in the interval from time t 5 to t 6 during the transition from “1” to “0”
Transistor 12 turns on and voltage a on signal line 1
It can be seen that the value is decreasing rapidly. The signal propagation delay of the signal line is t B −t 4 when “1” → “0”
It is shortened to .
第３図と第５図のａに見られる如く、本発明の
目的のためには、VL＜VTH＜VHとなる必要があ
り、急速に一方向に遷移する電圧範囲（VLから
VHまで）が、その信号線の電圧を入力とする全
てのゲートの閾電圧VTH1，VTH2，………，VTHoを
含む、即ち、VL＜（VTH1，VTH2，………，VTHo）
＜VHとなる必要がある。 As seen in FIGS. 3 and 5a, for the purpose of the present invention, it is necessary that V L < V TH < V H , and the voltage range that rapidly transitions in one direction (from V L to
(up to V H ) includes the threshold voltages V TH1 , V TH2 , ......, V THo of all gates that input the voltage of that signal line, that is, V L < (V TH1 , V TH2 , ... …, V THo )
＜ VH .
本発明の効果は、マイクロ・コンピユータのバ
スラインのように、多数のゲートの入出力に接続
された信号線の場合に極めて大きくなる。つま
り、容量の大きなバスを急速にドライブするため
には、バスに出力が接続されている全てのゲート
の出力トランジスタのgmを大きくとる必要があ
り、面積が大きくなる。このゲートの数が多いの
で、全体としてはかなりな面積をとつてしまう。
これは、集積回路の集積度と電力消費を悪化させ
ることになる。これに対し、バスに接続されるゲ
ートは全て適度な大きさにしておき、信号線に１
個だけ本発明の回路をつけておけば、面積の増加
は必要最少限になる。 The effects of the present invention are extremely significant in the case of a signal line connected to inputs and outputs of a large number of gates, such as a bus line of a microcomputer. In other words, in order to rapidly drive a bus with a large capacity, it is necessary to increase the gm of the output transistors of all gates whose outputs are connected to the bus, which increases the area. Since there are a large number of gates, the total area will be large.
This will degrade the density and power consumption of the integrated circuit. On the other hand, all gates connected to the bus should be of appropriate size, and one gate should be connected to the signal line.
If only one circuit of the present invention is provided, the increase in area will be kept to a minimum.
以上、説明したように、本発明によれば、IC
化されたマイクロコンピユータのバスラインの如
き、負荷容量が大きいにもかかわらず、高速のデ
イジタル信号伝搬が要求される信号線の信号伝搬
遅延時間を大幅に短縮することができ、しかも、
簡単な回路構成が実現できて、特に、デイジタル
集積回路に応用したとき、極めて価値の高いもの
である。 As explained above, according to the present invention, the IC
It is possible to significantly reduce the signal propagation delay time of signal lines that require high-speed digital signal propagation despite having a large load capacity, such as the bus lines of microcomputers that have been
A simple circuit configuration can be realized, which is extremely valuable especially when applied to digital integrated circuits.
第１図は本発明の要点を説明するための図、第
２図は本発明の一実施例の電子回路の具体的回路
図、第３図は第２図の回路各部の出力信号波形
図、第４図は本発明の他の実施例の電子回路の具
体的回路図、第５図は第４図の回路各部の出力信
号波形図である。
１……信号線、２……VH検出回路、３……VL
検出回路、７……Ｐチヤネル・トランジスタ、１
２……Ｎチヤネル・トランジスタ。
FIG. 1 is a diagram for explaining the main points of the present invention, FIG. 2 is a specific circuit diagram of an electronic circuit according to an embodiment of the present invention, and FIG. 3 is an output signal waveform diagram of each part of the circuit in FIG. FIG. 4 is a specific circuit diagram of an electronic circuit according to another embodiment of the present invention, and FIG. 5 is a diagram of output signal waveforms of various parts of the circuit in FIG. 1...Signal line, 2...V H detection circuit, 3...V L
Detection circuit, 7...P channel transistor, 1
2...N-channel transistor.
Claims (1)
する検出手段と、上記検出手段の出力で制御さ
れ、上記信号線に電流を流し込む流入手段とを具
備し、上記信号線の電圧が、第１の電圧と第２の
電圧とにはさまれた所定の電圧範囲に上記第１の
電圧を越えて入つた場合にのみでかつ上記信号線
の電圧が上記所定の電圧範囲にある時にだけ、上
記流入手段が上記信号線に電流を流し込むことを
特徴とする電子回路。 ２ 所定の電圧範囲が、信号線に入力が接続され
た全ての論理回路の入力論理電圧を含むことを特
徴とする特許請求の範囲第１項記載の電子回路。 ３ 流入手段が半導体スイツチであることを特徴
とする特許請求の範囲第１項記載の電子回路。 ４ 流入手段がＰチヤネル・トランジスタである
ことを特徴とする特許請求の範囲第１項記載の電
子回路。 ５ ２値電圧信号を伝送する信号線の電圧を検出
する検出手段と、上記検出手段の出力で制御され
上記信号線から電流を流し出す流出手段とを具備
し、上記信号線の電圧が第１の電圧と第２の電圧
とにはさまれた所定の電圧範囲に上記第２の電圧
を下まわつて入つた場合にのみでかつ上記信号線
の電圧が上記所定の電圧範囲にある時にだけ、上
記流出手段が上記信号線から電流を流し出すこと
を特徴とする電子回路。 ６ 所定の電圧範囲が、上記信号線に入力が接続
された全ての論理回路の入力論理電圧を含むこと
を特徴とする特許請求の範囲第５項記載の電子回
路。 ７ 流出手段が半導体スイツチであることを特徴
とする特許請求の範囲第５項記載の電子回路。 ８ 流出手段がＮチヤネル・トランジスタである
ことを特徴とする特許請求の範囲第５項記載の電
子回路。[Scope of Claims] 1. A detection means for detecting the voltage of a signal line that transmits a binary voltage signal, and an inflow means that is controlled by the output of the detection means and flows a current into the signal line, Only when the voltage of the signal line exceeds the first voltage and falls within a predetermined voltage range sandwiched between the first voltage and the second voltage, and the voltage of the signal line falls within the predetermined voltage range. An electronic circuit characterized in that the inflow means causes current to flow into the signal line only when the signal line is within the range. 2. The electronic circuit according to claim 1, wherein the predetermined voltage range includes input logic voltages of all logic circuits whose inputs are connected to the signal line. 3. The electronic circuit according to claim 1, wherein the inflow means is a semiconductor switch. 4. Electronic circuit according to claim 1, characterized in that the inflow means is a P-channel transistor. 5 A detection means for detecting the voltage of a signal line transmitting a binary voltage signal, and a drain means for flowing a current from the signal line controlled by the output of the detection means, wherein the voltage of the signal line is and the second voltage, and only when the voltage of the signal line is within the predetermined voltage range, An electronic circuit characterized in that the outflow means causes current to flow out from the signal line. 6. The electronic circuit according to claim 5, wherein the predetermined voltage range includes input logic voltages of all logic circuits whose inputs are connected to the signal line. 7. The electronic circuit according to claim 5, wherein the outflow means is a semiconductor switch. 8. The electronic circuit according to claim 5, wherein the outflow means is an N-channel transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56051477A JPS57166734A (en) | 1981-04-06 | 1981-04-06 | Electronic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56051477A JPS57166734A (en) | 1981-04-06 | 1981-04-06 | Electronic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57166734A JPS57166734A (en) | 1982-10-14 |
| JPH0128543B2 true JPH0128543B2 (en) | 1989-06-02 |
Family
ID=12888027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56051477A Granted JPS57166734A (en) | 1981-04-06 | 1981-04-06 | Electronic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57166734A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4647797A (en) * | 1984-08-23 | 1987-03-03 | Ncr Corporation | Assist circuit for improving the rise time of an electronic signal |
| US4598216A (en) * | 1984-08-27 | 1986-07-01 | Ncr Corporation | Assist circuit for a data bus in a data processing system |
| US4933574A (en) * | 1989-01-30 | 1990-06-12 | Integrated Device Technology, Inc. | BiCMOS output driver |
| JP4588144B2 (en) * | 1998-11-10 | 2010-11-24 | 川崎マイクロエレクトロニクス株式会社 | Sample hold circuit |
-
1981
- 1981-04-06 JP JP56051477A patent/JPS57166734A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57166734A (en) | 1982-10-14 |
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