JPH01282921A - Overcurrent protection driving circuit for igbt - Google Patents
Overcurrent protection driving circuit for igbtInfo
- Publication number
- JPH01282921A JPH01282921A JP63111970A JP11197088A JPH01282921A JP H01282921 A JPH01282921 A JP H01282921A JP 63111970 A JP63111970 A JP 63111970A JP 11197088 A JP11197088 A JP 11197088A JP H01282921 A JPH01282921 A JP H01282921A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- emitter
- gate
- igbt
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006378 damage Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
Landscapes
- Electronic Switches (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、スイッチング用半導体素子の一種であるＩ
ＧＢ Ｔ （Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐ
ｏｌａｒ Ｔｒａｎｓｉｓ Ｌｏｔ ）素子の過電流保
護機能を有する駆動回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an I
GB T (Insulated Gate Bip)
The present invention relates to a drive circuit having an overcurrent protection function for a polar transistor element.
Ｉ ＧＢＴ素子はバイポーラトランジスタの有する高耐
圧、大容量化が容易であるという長所と、パワーＭＯ３
ＦＥＴの有する高速なスイッチングが可能で、ドライブ
も容易であるという長所とをあわせもった新しいデバイ
スとして注目されている。IGBT elements have the advantages of bipolar transistors, such as high breakdown voltage and easy increase in capacity, and the power MO3
It is attracting attention as a new device that combines the advantages of FETs, such as being capable of high-speed switching and being easy to drive.
第２図にＮチャネルＩ ＧＢＴの等価回路を示す。FIG. 2 shows an equivalent circuit of an N-channel IGBT.
ＮチャネルＭＯ３ＦＥＴＩ、ＮＰＮ）ランジスタ２、Ｐ
ＮＰ）ランジスタ３、及びトランジス２のベース・エミ
ッタ間短絡用抵抗４からなり、ＭＯ３ＦＥＴＩのドレー
ン・ソース間とトランジスタ２のエミッタ・コレクタ間
を並列接続し、トランジスタ２．３はサイリスク回路を
形成するものとして表すことができる。N-channel MO3FETI, NPN) transistor 2, P
NP) Consisting of a transistor 3 and a short-circuiting resistor 4 between the base and emitter of the transistor 2, the drain and source of the MO3FETI and the emitter and collector of the transistor 2 are connected in parallel, and the transistor 2.3 forms a silice circuit. It can be expressed as
前記ＮチャネルのＩ ＧＢＴをオンさせる時は、ゲート
・エミッタ間（Ｇ−Ｅ間）に順バイアス電圧をかける。When turning on the N-channel IGBT, a forward bias voltage is applied between the gate and emitter (between G and E).
その結果、ＭＯ３ＦＥＴＩにチャネルが形成され、該Ｍ
Ｏ３ＦＥＴＩが導通状態になり、ＰＮＰ トランジスタ
３のエミッタ・ベース間が順バイアスされることにより
導通が開始する。As a result, a channel is formed in MO3FETI, and the M
O3FETI becomes conductive, and the emitter-base of PNP transistor 3 is forward biased, thereby starting conduction.
逆に、本素子をＯＦＦさせる時はゲート・エミッタ間に
逆バイアス電圧をかける。この結果、ＭＯ３ＦＥＴＩは
オフになり、ＰＮＰ ）ランジスタ３のベース電流が流
れなくなり、該トランジスタがオフし、その結果ＩＧＢ
Ｔがオフする。Conversely, when turning off this element, a reverse bias voltage is applied between the gate and emitter. As a result, MO3FETI is turned off, the base current of PNP transistor 3 stops flowing, the transistor is turned off, and as a result, IGB
T turns off.
ところで、本素子は前記のようにトランジスタ２．３に
よる寄生サイリスクを有する。そのためコレクタ電流が
所定値以上になるとラッチアップ現象（寄生サイリスタ
がターンオンしてしまう現象）を生じ、電流が遮断でき
なくなってしまう場合がある。By the way, as mentioned above, this element has a parasitic Si risk due to the transistor 2.3. Therefore, when the collector current exceeds a predetermined value, a latch-up phenomenon (a phenomenon in which a parasitic thyristor turns on) occurs, and the current may not be interrupted.
このラッチアップ現象はＩ ＧＢＴの素子破壊に連結す
るので、これを生じないようにすることが必要となる。Since this latch-up phenomenon leads to element destruction of the IGBT, it is necessary to prevent this from occurring.
ＩＧＢＴの過電流保護を行う場合は、電流レベルをラッ
チアップ電流以下に抑えなければならない。また、熱破
壊に至る前にコレクタ電流を遮断することが必要である
。When protecting an IGBT from overcurrent, the current level must be kept below the latch-up current. Furthermore, it is necessary to cut off the collector current before thermal breakdown occurs.
第２図において、Ｉ ＧＥＴにオフゲート信号を与える
とまずＮチャネルＭＯ３ＦＥＴＩがターンオフする。過
負荷時にはコレクタ電流が急には減少できないためにＰ
ＮＰ ｌ−ランジスタ３の電流が増加する。このためタ
ーンオフ時はターンオン状態より小さなコレクタ電流で
ラッチアップすることになる。また、ターンオフ時にコ
レクタ・エミッタ間に印加されるｄｖ／ｄｔによる接合
容量の充電電流もラッチアップ電流を低下させる。この
ため過電流時のターンオフはゆるやかに行われなければ
ならない。In FIG. 2, when an off-gate signal is applied to I GET, first the N-channel MO3FETI is turned off. During overload, the collector current cannot decrease suddenly, so P
The current in the NP l-transistor 3 increases. For this reason, latch-up occurs with a smaller collector current in the turn-off state than in the turn-on state. Further, the charging current of the junction capacitance due to dv/dt applied between the collector and emitter at the time of turn-off also reduces the latch-up current. For this reason, turn-off at the time of overcurrent must be performed slowly.
このようなＩＧＢＴの駆動回路で、過電流保護の機能を
持たせた従来例を第３図に示す。FIG. 3 shows a conventional example of such an IGBT drive circuit equipped with an overcurrent protection function.
直列接続した順バイアス電源５ａと逆バイアス電源５ｂ
との接続中点がＩＧＢＴＩＩのエミッタに接続され、こ
れら電源５ａ、５ｂにスイッチ１０ａ。Forward bias power supply 5a and reverse bias power supply 5b connected in series
The midpoint of the connection is connected to the emitter of IGBTI II, and a switch 10a is connected to these power supplies 5a and 5b.
１０ｂが直列接続され、該スイッチ１０ａ、１０ｂの接
続中点は抵抗９ａを介してＩＧＢＴＩＩのゲートに接続
される。10b are connected in series, and the connection midpoint of the switches 10a and 10b is connected to the gate of IGBTII via a resistor 9a.
ＮＰＮ ｌ−ランジスタ８のコレクタが抵抗９Ｃを介し
て抵抗９ａとＩＧＢＴＩＩのゲートとの接続中点に、エ
ミッタが逆バイアス電源５ｂの負極とスイッチ１０ｂと
の接続中点に接続され、該トランジスタ８のベースはツ
ェナーダイオード７及び抵抗９ｂを介してスイッチ１０
ａ、１０ｂの接続中点と抵抗９ａに接続され、抵抗９ｂ
とツェナーダイオード７との接続中点はダイオード６を
介してＩＧＢＴｌｌのコレクタに接続される。The collector of the NPN l-transistor 8 is connected to the midpoint between the resistor 9a and the gate of IGBTII via the resistor 9C, and the emitter is connected to the midpoint between the negative electrode of the reverse bias power supply 5b and the switch 10b. The base is connected to a switch 10 via a Zener diode 7 and a resistor 9b.
a, 10b is connected to the connection midpoint and resistor 9a, and resistor 9b
The midpoint of the connection between the zener diode 7 and the zener diode 7 is connected to the collector of the IGBTll via the diode 6.
通常時の動作としては、順バイアス時はスイッチ１０ａ
をＯＮＬ、スイッチ１０ｂをＯＦＦする。よって順バイ
アス電源５ａの電圧がスイッチ１０ａ１抵抗９ａを介し
てＩ Ｇ Ｂ Ｔｌｌのゲート・エミッタ間に順バイア
ス電圧として印加される。一方、逆バイアス時はスイッ
チ１０ａを０ＦＦＬ、、スイッチ１０ｂをＯＮする。よ
って逆バイアス電源５ｂの電圧が抵抗９ａ、スイッチ１
０ｂを介してＩＧＢＴＩＩのゲート・エミッタ間に逆バ
イアス電圧として印加される。In normal operation, switch 10a during forward bias.
ONL and switch 10b is turned OFF. Therefore, the voltage of the forward bias power supply 5a is applied as a forward bias voltage between the gate and emitter of the IGBTll via the switch 10a1 and the resistor 9a. On the other hand, during reverse bias, the switch 10a is set to 0FFL, and the switch 10b is turned on. Therefore, the voltage of the reverse bias power supply 5b is applied to the resistor 9a and the switch 1.
It is applied as a reverse bias voltage between the gate and emitter of IGBTII via 0b.
一方、過電流時の動作は、次のようになる。On the other hand, the operation at the time of overcurrent is as follows.
順バイアス時にＩＧＢＴＩＩのコレクタ・エミッタ間電
圧が、ツェナーダイオード７のツェナー電圧とＮＰＮ
ｌ−ランジスタ８のベース・エミッタ間ダイオードの順
バイアス電圧降下分の和から逆バイアス電源５ｂの電圧
をひいた電圧を越えると、ＮＰＮ）ランジスタ８のベー
ス・エミッタ間には電Ｒ５ａの電圧が、スイッチ１０ａ
、抵抗９ｂ、ツェナーダイオード７を介して印加され、
その結果ベース・エミッタ間は順バイアスされ、該トラ
ンジスタ８は導通する。このため、ＩＧＢＴＩＩのゲー
ト・エミッタ間には逆バイアス電源５ｂの電圧が該トラ
ンジスタ８及び抵抗９ｃを介して逆バイアス電圧として
印加される。そのため、ＩＧＢＴｌｌのコレクタ電流は
遮断される。During forward bias, the collector-emitter voltage of IGBTII is equal to the Zener voltage of Zener diode 7 and NPN
When the voltage exceeds the voltage obtained by subtracting the voltage of the reverse bias power supply 5b from the sum of the forward bias voltage drops of the diodes between the base and emitter of the NPN transistor 8, the voltage of R5a between the base and emitter of the NPN transistor 8 becomes switch 10a
, applied via the resistor 9b and the Zener diode 7,
As a result, the base-emitter region is forward biased, and the transistor 8 becomes conductive. Therefore, the voltage of the reverse bias power supply 5b is applied as a reverse bias voltage between the gate and emitter of the IGBTI via the transistor 8 and the resistor 9c. Therefore, the collector current of IGBTll is cut off.
しかし前記第３図に示すような従来の駆動回路では、過
電流遮断時にゲート・エミッタ間に逆バイアス電圧を印
加することになりターンオフが速（なり、ターンオフ時
のラッチアップによる素子破壊のおそれがある。However, in the conventional drive circuit as shown in Fig. 3, a reverse bias voltage is applied between the gate and emitter when overcurrent is cut off, resulting in fast turn-off (and the risk of device destruction due to latch-up at turn-off). be.
本発明の目的は前記従来例の不都合を解消し、ターンオ
フ時のラッチアップによる素子破壊を防ぐことができる
Ｉ ＧＢＴの過電流保護駆動回路を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide an overcurrent protection drive circuit for an IGBT that can eliminate the disadvantages of the conventional example and prevent element destruction due to latch-up during turn-off.
本発明は前記目的を達成するため、Ｉ ＧＢＴの通常の
ターンオフ時にはゲート・エミッタ間に逆電圧を印加す
る駆動回路において、コレクタ・エミッタ間が導通時に
所定の電圧を越えた場合、ゲート・エミッタ間を短絡さ
せる回路を設けたことを要旨とするものである。In order to achieve the above object, the present invention has a drive circuit that applies a reverse voltage between the gate and emitter during normal turn-off of an IGBT, and when the voltage between the collector and emitter exceeds a predetermined voltage when conductive, the voltage between the gate and emitter is The gist is that a circuit is provided to short-circuit the .
本発明によれば、Ｉ ＧＢＴの過電流保護時にゲート・
エミッタ間を短絡させることにより、ゲート・エミッタ
間の接合容量からの蓄積電荷の放電を逆バイアスを印加
する場合に比しゆるやかにでき、これによりコレクタ電
流の過電流時の遮断をゆるやかに行い、遮断時のラッチ
アップを防ぐことができる。According to the present invention, during overcurrent protection of IGBT, gate
By shorting the emitters, the accumulated charge from the junction capacitance between the gate and the emitter can be discharged more slowly than when applying a reverse bias, and this allows the collector current to be cut off more slowly in the event of an overcurrent. It can prevent latch-up when shutting off.
以下、図面について本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は本発明のＩ ＧＢＴの過電流保護駆動回路の１
実施例を示す回路図で、前記従来例を示す第３図と同一
構成要素には同一参照符号を付したものである。Figure 1 shows one of the IGBT overcurrent protection drive circuits of the present invention.
This is a circuit diagram showing an embodiment, and the same components as in FIG. 3 showing the conventional example are given the same reference numerals.
すなわち、直列接続した順バイアス電源５ａと逆バイア
ス電源５ｂとの接続中点がＩＣ；ＢＴＩＩのエミッタに
接続され、これら電源５ａ、５ｂにスイッチ１０ａ、１
０ｂが直列接続され、該スイッチ１０ａ、１ｏｂの接続
中点は抵抗９ａを介してＩ ＧＢＴｌｌのゲートに接続
される。また、ＮＰＮ ）ランジスタ８のコレクタが抵
抗９ｃを介して前記抵抗９ａとＩＧＢＴＩＩのゲートと
の接続中点に、エミッタがダイオード６ｂを介して順バ
イアス電源５ａと逆バイアス電源５ｂとの接続中点に接
続され、該トランジスタ８のベースはツェナーダイオー
ド７及び抵抗９ｂを介してスイッチ１０ａ、１０ｂの接
続中点に接続され、抵抗９ｂとツェナーダイオード７と
の接続中点はダイオード６ａを介してＩＣＢＴＩＩのコ
レクタに接続される。That is, the midpoint of the connection between the forward bias power supply 5a and the reverse bias power supply 5b connected in series is connected to the emitter of IC; BTII, and the switches 10a and 1 are connected to these power supplies 5a and 5b.
0b are connected in series, and the midpoint between the switches 10a and 1ob is connected to the gate of IGBTll via a resistor 9a. In addition, the collector of the NPN transistor 8 is connected to the midpoint between the resistor 9a and the gate of IGBTII via the resistor 9c, and the emitter is connected to the midpoint of the connection between the forward bias power source 5a and the reverse bias power source 5b through the diode 6b. The base of the transistor 8 is connected to the midpoint between the switches 10a and 10b via the Zener diode 7 and the resistor 9b, and the midpoint between the resistor 9b and the Zener diode 7 is connected to the collector of ICBTII via the diode 6a. connected to.
本発明は第１図に示すような駆動回路で、トランジスタ
８のエミッタをダイオード６ｂを介して逆バイアス電源
５ｂの正極に接続し、該トランジスタ８の導通時にＩ
Ｇ Ｂ Ｔｌｌのゲートとエミッタとを抵抗９ｃを介し
て接続する回路を形成した。The present invention is a drive circuit as shown in FIG.
A circuit was formed to connect the gate and emitter of G B Tll via a resistor 9c.
次に、動作について説明する。Next, the operation will be explained.
順バイアス時はスイッチ１０ａをＯＮＬ、、スイッチｔ
ａｂをＯｊＦする。よって順バイアス電１５ａの電圧が
スイッチ１０ａ１抵抗９ａを介してＩＧＢＴｌｌのゲー
ト・エミッタ間に順バイアス電圧として印加される。During forward bias, switch 10a is ONL, switch t
OjF ab. Therefore, the voltage of the forward bias voltage 15a is applied as a forward bias voltage between the gate and emitter of the IGBTll via the switch 10a1 and the resistor 9a.
一方、逆バイアス時はスイッチ１０ａを０ＦＦＬ、スイ
ッチ１０ｂをＯＮする。よって逆バイアス電源５ｂの電
圧が抵抗９ ａ ｓスイッチ１０ｂを介してＩＧＢＴＩ
Ｉのゲート・エミッタ間に逆バイアス電圧として印加さ
れる。On the other hand, during reverse bias, the switch 10a is set to 0FFL and the switch 10b is turned on. Therefore, the voltage of the reverse bias power supply 5b is changed to IGBTI via the resistor 9a and the switch 10b.
It is applied as a reverse bias voltage between the gate and emitter of I.
ところで、順バイアス時にＩＧＢＴＩＩのコレクタ・エ
ミッタ間電圧が、ツェナーダイオード７のツェナー電圧
とＮＰＮ トランジスタ８のベース・エミッタ間ダイオ
ードの順バイアス電圧降下分の和から逆バイアス電源５
ｂの電圧をひいた電圧を越えると、ＮＰＮ ）ランジス
タ８のベース・エミッタ間には電［５ａの電圧が、スイ
ッチ１０ａ、抵抗９ｂ、ツェナーダイオード７を介して
印加されそのためベース・エミッタ間は順バイアスされ
、該トランジスタ８は導通する。Incidentally, during forward bias, the collector-emitter voltage of IGBTII is calculated from the sum of the Zener voltage of the Zener diode 7 and the forward bias voltage drop of the base-emitter diode of the NPN transistor 8.
When the voltage exceeds the voltage obtained by subtracting the voltage of NPN transistor 8, the voltage of 5a is applied between the base and emitter of the NPN transistor 8 via the switch 10a, the resistor 9b, and the Zener diode 7. Biased, the transistor 8 becomes conductive.
このとき、ＩＧＢＴＩＩのゲート・エミッタ間は抵抗９
Ｃ、トランジスタ８、及びダイオード６ｂにより短絡さ
れる。このダイオード６ｂはトランジスタ８に対して逆
耐圧を持たせるものである。At this time, a resistor 9 is connected between the gate and emitter of IGBTII.
C, transistor 8, and diode 6b. This diode 6b provides reverse breakdown voltage to the transistor 8.
すなわち、通常のターンオフ時はスイッチ１０ｂがオン
となるため、トランジスタ８のコレクタ・エミッタ間に
対して電源５ｂの電圧が逆向きに加わる。一般にトラン
ジスタは逆耐圧が弱い。そこでダイオード６ｂのカソー
ド・アノード間に電源５ｂの電圧をもたせることにより
、トランジスタ８を保護するものである。That is, since the switch 10b is turned on during normal turn-off, the voltage of the power supply 5b is applied between the collector and emitter of the transistor 8 in the opposite direction. Transistors generally have weak reverse breakdown voltage. Therefore, the transistor 8 is protected by applying the voltage of the power supply 5b between the cathode and anode of the diode 6b.
このように、ゲート・エミッタ間が短絡されるため、Ｉ
ＧＢＴＩＩのゲート・エミッタ間の電荷は逆電圧を印加
した場合に比較してゆるやかに放電され、その結果コレ
クタ電流のターンオフはゆっくりと行われ、電流遮断時
のラッチアップを起こすことなく過電流保護を行うこと
ができる。In this way, since the gate and emitter are short-circuited, I
The charge between the gate and emitter of GBT II is discharged more slowly than when a reverse voltage is applied, and as a result, the collector current is turned off more slowly, allowing overcurrent protection without latch-up when the current is cut off. It can be carried out.
以上述べたように本発明のＩ ＣＢＴの過電流保護駆動
回路は、電流遮断時のラッチアップを起こすことなく過
電流保護を行うことができるので、Ｔ ＧＢＴがより広
範囲な用途に適用できるようになるものである。As described above, the overcurrent protection drive circuit of the I CBT of the present invention can perform overcurrent protection without causing latch-up when current is cut off, so that the T GBT can be applied to a wider range of applications. It is what it is.
第１図は本発明のＩ ＧＢＴの過電流保護駆動回路の１
実施例を示す回路図、第２図はＩ ＧＢＴの等価回路図
、第３図は従来の過電流保護駆動回路を示す回路図であ
る。
１・・・ＮチャネルＦＥＴ
２・・・ＮＰＮ ）ランジスタ
３・・・ＰＮＰ ）ランジスタ
４・・・抵抗 ５ａ・・・順バイアス電源５
ｂ・・・逆バイアス電源
６．６ａ、６ｂ・・・ダイオード
７・・・ツェナーダイオード
８・・・ＮＰＮ）ランジスタ
９ ａ、 ９ ｂ、 ９ Ｃ−−−抵抗１０ａ、１
０ｂ・・・スイッチ
１１・・・Ｉ ＧＢＴ
第１図Figure 1 shows one of the IGBT overcurrent protection drive circuits of the present invention.
FIG. 2 is an equivalent circuit diagram of an IGBT, and FIG. 3 is a circuit diagram showing a conventional overcurrent protection drive circuit. 1...N-channel FET 2...NPN) transistor 3...PNP) transistor 4...resistor 5a...forward bias power supply 5
b...Reverse bias power supply 6.6a, 6b...Diode 7...Zener diode 8...NPN) Resistor 9a, 9b, 9C---Resistance 10a, 1
0b...Switch 11...I GBT Figure 1
Claims (1)
に逆電圧を印加する駆動回路において、コレクタ・エミ
ッタ間が導通時に所定の電圧を越えた場合、ゲート・エ
ミッタ間を短絡させる回路を設けたことを特徴とするＩ
ＧＢＴの過電流保護駆動回路。In a drive circuit that applies a reverse voltage between the gate and emitter during normal turn-off of the IGBT, a circuit is provided that shorts the gate and emitter if the voltage between the collector and emitter exceeds a predetermined voltage when conductive. I do
GBT overcurrent protection drive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63111970A JPH0810821B2 (en) | 1988-05-09 | 1988-05-09 | Overcurrent protection drive circuit for IGBT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63111970A JPH0810821B2 (en) | 1988-05-09 | 1988-05-09 | Overcurrent protection drive circuit for IGBT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01282921A true JPH01282921A (en) | 1989-11-14 |
| JPH0810821B2 JPH0810821B2 (en) | 1996-01-31 |
Family
ID=14574702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63111970A Expired - Lifetime JPH0810821B2 (en) | 1988-05-09 | 1988-05-09 | Overcurrent protection drive circuit for IGBT |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810821B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0348517A (en) * | 1989-04-13 | 1991-03-01 | Mitsubishi Electric Corp | Driving circuit for igbt element |
| JPH09182275A (en) * | 1995-12-12 | 1997-07-11 | Samsung Electro Mech Co Ltd | Circuit for protecting semiconductor transistor for power from overcurrent |
| US20090055664A1 (en) * | 2007-08-20 | 2009-02-26 | Funai Electric Co., Ltd. | Communication Device |
| CN101777756A (en) * | 2009-12-25 | 2010-07-14 | 天津市诺尔电气有限公司 | Over-current protection circuit for insulated gate bipolar transistor |
| CN103500989A (en) * | 2013-10-11 | 2014-01-08 | 济南诺顿科技有限公司 | Protection circuit of IGBT (Insulated Gate Bipolar Transistor) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6395724A (en) * | 1986-10-13 | 1988-04-26 | Fuji Electric Co Ltd | Driving circuit for igbt gate |
-
1988
- 1988-05-09 JP JP63111970A patent/JPH0810821B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6395724A (en) * | 1986-10-13 | 1988-04-26 | Fuji Electric Co Ltd | Driving circuit for igbt gate |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0348517A (en) * | 1989-04-13 | 1991-03-01 | Mitsubishi Electric Corp | Driving circuit for igbt element |
| JPH09182275A (en) * | 1995-12-12 | 1997-07-11 | Samsung Electro Mech Co Ltd | Circuit for protecting semiconductor transistor for power from overcurrent |
| US20090055664A1 (en) * | 2007-08-20 | 2009-02-26 | Funai Electric Co., Ltd. | Communication Device |
| US8214659B2 (en) * | 2007-08-20 | 2012-07-03 | Funai Electric Co., Ltd. | Communication device having pull-up voltage supply circuit supplying pull-up voltage via one power supply during standby state and another power supply during power-on state |
| CN101777756A (en) * | 2009-12-25 | 2010-07-14 | 天津市诺尔电气有限公司 | Over-current protection circuit for insulated gate bipolar transistor |
| CN103500989A (en) * | 2013-10-11 | 2014-01-08 | 济南诺顿科技有限公司 | Protection circuit of IGBT (Insulated Gate Bipolar Transistor) |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810821B2 (en) | 1996-01-31 |
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