JPH01274419A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01274419A JPH01274419A JP10456688A JP10456688A JPH01274419A JP H01274419 A JPH01274419 A JP H01274419A JP 10456688 A JP10456688 A JP 10456688A JP 10456688 A JP10456688 A JP 10456688A JP H01274419 A JPH01274419 A JP H01274419A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- concentration
- oxide film
- film
- type impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 abstract description 9
- 238000005260 corrosion Methods 0.000 abstract description 4
- 230000007797 corrosion Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 6
- 238000001947 vapour-phase growth Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 240000005109 Cryptomeria japonica Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 241000269821 Scombridae Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 235000020640 mackerel Nutrition 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置、詳しくは、同装置の不純物拡散
源である気相成長法により形成するシリコン酸化膜中の
Ｎ型不純物濃度プロファイルに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an N-type impurity concentration profile in a silicon oxide film formed by vapor phase growth, which is an impurity diffusion source of the device. be.
従来の技術
従来半導体装置を形成する際、気相成長法を用いたシリ
コン酸化膜中に含まれるＮ型の不純物濃度プロファイル
は、そのシリコン酸化膜の表面からシリコン基板接合面
迄一定の単層構造もしくは、その膜上に不純物を全く含
まないシリコン酸化膜を加えた２層構造の装置が用いら
れていた。BACKGROUND OF THE INVENTION Conventionally, when forming a semiconductor device, the N-type impurity concentration profile contained in a silicon oxide film using a vapor phase growth method has a constant single-layer structure from the surface of the silicon oxide film to the bonding surface of the silicon substrate. Alternatively, a device with a two-layer structure has been used in which a silicon oxide film containing no impurities is added on top of the film.
発明が解決しようとする課題
フォトレジストをマスクに前記単層シリコン酸化膜のウ
ェットエツチングを行った際、そのエツチング時間に比
例しサイドエツチング量も増加する。その結果、規定の
寸法より大きなコンタクトホールが形成され、暗室マス
クアライナ−のアライメント精度上、トランジスタ等の
セルサイズが大きくなる。また、前記単層シリコン酸化
膜は高濃度のＮ型不純物を含んでいるため、前記シリコ
ン酸化膜上にアルミニウム配線を形成すると腐食が発生
する。次に、前記単層シリコン酸化膜上に不純物を含ま
ないシリコン酸化膜を加えた２層構造のシリコン酸化膜
をフォトレジストをマスクにウェットエツチングを行っ
た場合、高濃度のＮ型不純物を含んだ下層のサイドエツ
チングが上層のそれよりも著しく進み、その結果、コン
タクトホールの断面形状はオーバーハング状になり、そ
の後の配線形成の際、または、電気的検査の際に配腺切
れが発生する。本発明は、これらの問題点に対しコンタ
クトホールを正確な大きさに開け、アルミニウム配線の
腐食や配線切れの防止可能な半導体装置を提供すること
を目的とする。Problems to be Solved by the Invention When the single layer silicon oxide film is wet etched using a photoresist as a mask, the amount of side etching increases in proportion to the etching time. As a result, a contact hole larger than the specified size is formed, and the size of a cell such as a transistor becomes large due to the alignment accuracy of a dark room mask aligner. Furthermore, since the single-layer silicon oxide film contains a high concentration of N-type impurities, corrosion occurs when aluminum wiring is formed on the silicon oxide film. Next, when a two-layer silicon oxide film, in which a silicon oxide film containing no impurities is added to the single-layer silicon oxide film, is wet-etched using a photoresist as a mask, the silicon oxide film contains a high concentration of N-type impurities. The side etching of the lower layer progresses more significantly than that of the upper layer, and as a result, the cross-sectional shape of the contact hole becomes overhanging, and disconnection occurs during subsequent wiring formation or electrical testing. SUMMARY OF THE INVENTION It is an object of the present invention to solve these problems and to provide a semiconductor device in which contact holes are formed in an accurate size and corrosion of aluminum wiring and wiring breakage can be prevented.
課題を解決するための手段
これらの問題点を解決するために、本発明は、シリコン
基板表面に気相成長するシリコン酸化膜のＮ型不純物濃
度プロファイルをシリコン基板上からシリコン酸化膜表
面方向に低濃度になる様にした構造の半導体装置である
。Means for Solving the Problems In order to solve these problems, the present invention lowers the N-type impurity concentration profile of the silicon oxide film grown in vapor phase on the surface of the silicon substrate from the top of the silicon substrate toward the surface of the silicon oxide film. This is a semiconductor device with a structure such that the concentration is high.
作用
上記構成によって気相成長されたシリコン酸化膜にコン
タクトホールを形成する際、Ｎ型不純物濃度のエツチン
グレートの差を利用してエツチングすることにより、窓
幅寸法及びテーパー角度を調整できる。また、同膜表面
のＮ型不純物濃度を調整することにより間膜および配線
の信頼性を向上させることが可能である。Operation When forming a contact hole in a silicon oxide film grown in a vapor phase with the above structure, the window width and taper angle can be adjusted by etching using the difference in etching rate of N-type impurity concentration. Furthermore, by adjusting the N-type impurity concentration on the surface of the film, it is possible to improve the reliability of the interlayer and wiring.
実施例
以下、本発明の実施例について、図面を参照しながら説
明する。図はシリコン基板上にＮ型不純物量の異なった
３濃度のシリコン酸化膜を連続的に成長した膜を用いた
半導体装置の断面図である。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. The figure is a cross-sectional view of a semiconductor device using a film in which silicon oxide films having three different concentrations of N-type impurities are successively grown on a silicon substrate.
図中、１は例えばＰ型シリコン基板、２はＮ型の不純物
拡散層、３は熱酸化膜、４は気相成長によるＮ型不純物
（リン）を含むシリコン酸化膜、５．６．７はリン濃度
を順次低くして、その濃度の段階的に異なったシリコン
酸化膜、８はシリコン基板と配線を接続するコンタクト
ホール、９は例えばアルミニウム配線、１０は例えばシ
リコンナイトライドによる保護膜である。なお、本発明
は、Ｐ型シリコン基板に限らず、Ｎ型シリコン基板も用
いられ、さらには、バイポーラ型、ＭＯ３型ＩＣにも適
用できることは言うまでもない。In the figure, 1 is, for example, a P-type silicon substrate, 2 is an N-type impurity diffusion layer, 3 is a thermal oxide film, 4 is a silicon oxide film containing N-type impurities (phosphorous) by vapor phase growth, and 5.6.7 is a A silicon oxide film whose phosphorus concentration is gradually lowered to have a different concentration; 8 is a contact hole connecting the silicon substrate and wiring; 9 is, for example, an aluminum wiring; 10 is a protective film made of, for example, silicon nitride. It goes without saying that the present invention is not limited to P-type silicon substrates, but can also be applied to N-type silicon substrates, and can also be applied to bipolar type and MO3 type ICs.
発明の詳細
な説明してきたように、本発明の半導体装置によれば、
気相成長により形成されるシリコン酸化膜中の濃度プロ
ファイルをシリコン基板上からその膜表面方向に低濃度
化することによりエツチング窓幅寸法精度向上及び窓エ
ツチングテーパー角度の調整が可能になることによりコ
ンタクトホール段差部の配線切れを防止できる。又、前
記シリコン酸化膜の表層部の濃度を調整することにより
、前記シリコン酸化膜のクラックや配線材料の腐食の問
題も低減することが可能となる。As described in detail, according to the semiconductor device of the present invention,
By lowering the concentration profile in the silicon oxide film formed by vapor phase growth from the top of the silicon substrate toward the surface of the film, it becomes possible to improve the dimensional accuracy of the etching window width and adjust the window etching taper angle, thereby improving contact. Wiring breakage at the step part of the hall can be prevented. Furthermore, by adjusting the concentration of the surface layer of the silicon oxide film, it is possible to reduce problems such as cracks in the silicon oxide film and corrosion of the wiring material.
図はＮ型不純物の異なるシリコン酸化膜を用いた半導体
装置の断面図である。
１・・・・・・シリコン基板、２・・・・・・Ｎ型不純
物拡散層、３・・・・・・熱シリコン酸化膜、４・・・
・・・気相成長により形成されたＮ型不純物を含んだシ
リコン酸化膜、５．６．７・・・・・・Ｎ型不純物濃度
の異なったシリコン酸化膜、８・・・・・・シリコン基
板と配線材料を接続するコンタクトホール、９・・・・
・・配線材料、１０・・・・・・保護膜。
代理人の氏名 弁理士 中尾敏男 ほか１名１− シリ
コン基笈
２＝ ｒ４杉不純４！７搗散・１
３− 鰺シリコン般イし凛
４−・ 気稲バツリコン鮫化願
５−Ｎ形不純物馬１度頑
６−ｍ−・ 中 や
７・−・ 仇 ・
８−コンタクトホール
？−配欅ｔｔＰｌ−
１０−一一保環臘The figure is a cross-sectional view of a semiconductor device using silicon oxide films with different N-type impurities. 1... Silicon substrate, 2... N-type impurity diffusion layer, 3... Thermal silicon oxide film, 4...
...Silicon oxide film containing N-type impurity formed by vapor phase growth, 5.6.7...Silicon oxide film with different N-type impurity concentrations, 8...Silicon Contact hole for connecting the board and wiring material, 9...
...Wiring material, 10...Protective film. Name of agent: Patent attorney Toshio Nakao and 1 other person 1- Silicon base 2 = r4 Sugi impurity 4!7 Hoshisan 1 3- Mackerel silicon general Ishi Rin 4- Keine Baturikon Samekagan 5- N-type impurity Horse 1 degree Ken 6-m-・Nakaya 7・-・Ken・8-Contact hole? -KeyakittPl- 10-11 Hokankan
Claims (1)
化膜が形成されており、前記シリコン酸化膜の不純物濃
度が表面に比べ前記シリコン酸化膜と前記シリコン基板
界面で高いことを特徴とする半導体装置。A semiconductor device characterized in that a silicon oxide film containing an N-type impurity is formed on the surface of a silicon substrate, and the impurity concentration of the silicon oxide film is higher at the interface between the silicon oxide film and the silicon substrate than at the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10456688A JPH01274419A (en) | 1988-04-27 | 1988-04-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10456688A JPH01274419A (en) | 1988-04-27 | 1988-04-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01274419A true JPH01274419A (en) | 1989-11-02 |
Family
ID=14384003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10456688A Pending JPH01274419A (en) | 1988-04-27 | 1988-04-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01274419A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100269595B1 (en) * | 1992-05-14 | 2000-10-16 | 김영환 | Method of forming contact hole with improved profile |
| US6740584B2 (en) | 1997-03-27 | 2004-05-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
-
1988
- 1988-04-27 JP JP10456688A patent/JPH01274419A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100269595B1 (en) * | 1992-05-14 | 2000-10-16 | 김영환 | Method of forming contact hole with improved profile |
| US6740584B2 (en) | 1997-03-27 | 2004-05-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
| US7084508B2 (en) | 1997-03-27 | 2006-08-01 | Renesas Technology Corp. | Semiconductor device with multiple layer insulating film |
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