JPH01270403A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH01270403A JPH01270403A JP63099903A JP9990388A JPH01270403A JP H01270403 A JPH01270403 A JP H01270403A JP 63099903 A JP63099903 A JP 63099903A JP 9990388 A JP9990388 A JP 9990388A JP H01270403 A JPH01270403 A JP H01270403A
- Authority
- JP
- Japan
- Prior art keywords
- junction
- current
- fets
- pair
- constant voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 230000005669 field effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 4
- 238000004804 winding Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体！Ａ積回路装置に関し、特に差動対ジャ
ンクション電界効果トランジスタ回路を搭載する高周波
半導体集積回路装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a semiconductor! The present invention relates to an A product circuit device, and particularly to a high frequency semiconductor integrated circuit device equipped with a differential pair junction field effect transistor circuit.
第２図は従来の差動対ジャンクション電界効果トランジ
スタ回路を搭載した高周波半導体集積回路装置の一例を
示す接続回路図である。この半導体集積回路装置は、差
動対を形成する一対のジャンクション電界効果トランジ
スタ１，２（以下ジャンクションＦＥＴという）のそれ
ぞれのソースが、トランスＴを介して抵抗Ｒおよびバイ
パス・コンデンサＣに接続され、また、共通結線された
ゲートがリード端子Ｔフを介して接地される回路構成を
有する。FIG. 2 is a connection circuit diagram showing an example of a high frequency semiconductor integrated circuit device equipped with a conventional differential pair junction field effect transistor circuit. In this semiconductor integrated circuit device, respective sources of a pair of junction field effect transistors 1 and 2 (hereinafter referred to as junction FETs) forming a differential pair are connected to a resistor R and a bypass capacitor C via a transformer T, Further, it has a circuit configuration in which commonly connected gates are grounded via a lead terminal T.
しかしながら、かかる回路構成は差動対を形成するジャ
ンクションＦＥＴの動作電流にバラツキが生じ易いので
差動対増幅器としての緒特性、例えば、最大出力電圧あ
るいは、電圧利得等が大きくバラツク等の好丈しからざ
る幾つかの問題点が指摘されて来た。However, such a circuit configuration is likely to cause variations in the operating current of the junction FETs forming the differential pair, so the initial characteristics of the differential pair amplifier, such as maximum output voltage or voltage gain, may vary greatly. Several problems have been pointed out.
第３図は従来回路構成におけるジャンクションＦＥＴの
動作特性図を示すもので、横軸にはゲート・ソース電圧
、縦軸にはドレイン電流がそれぞれ表わされている。こ
こで曲線Ｃ１およびＣ２はそれぞれゲート・ソース間電
圧ＶＳＧのバラツキによって、カットオフ電圧が大（Ｖ
ｐＩ ）きくなった場合および小（ＶＰ２ ）さくなっ
た場合の特性を示し、曲線Ｃ３は抵抗Ｒで決定される負
荷線を示している。すなわち、ジャンクションＦＥＴＩ
および２のそれぞれの動作点Ｐ１およびＰ２は何れもカ
ットオフ電圧Ｖ ｐ １ 、 Ｖ ｐ ２のバラツキに
依存してバラツクこととなり、このことによって増幅器
としての諸特性もばらつくこととなる。FIG. 3 shows an operating characteristic diagram of a junction FET in a conventional circuit configuration, with the horizontal axis representing the gate-source voltage and the vertical axis representing the drain current. Here, curves C1 and C2 each have a large cutoff voltage (V
The curve C3 shows the load line determined by the resistance R. That is, the junction FETI
The operating points P1 and P2 of the amplifiers and the amplifiers 2 vary depending on the variations in the cutoff voltages V p 1 and V p 2 , and as a result, the various characteristics of the amplifier also vary.
本発明の目的は、上記の情況に鑑み、ジャンクションＦ
ＥＴ差動対回路における動作電流のバラツキを最小限に
抑止し得る回路構成を備えた半導体４Ａ積回路装置を提
供することである。In view of the above circumstances, an object of the present invention is to
It is an object of the present invention to provide a semiconductor 4A integrated circuit device having a circuit configuration capable of minimizing variations in operating current in an ET differential pair circuit.
本発明によれば、半導体集積回路装置は、半導体基板と
、前記半導体基板上に差動対回路を形成するゲート接地
の一対のジャンクション電界効果効果トランジスタのソ
ースにそれぞれ入力信号を伝達する入力トランスと、前
記入力トランスの２次巻線の中点と接地との間に挿入さ
れ前記一対のジャンクション電界効果トランジスタのソ
ースにそれぞれ定電流を供給する定電流源とを含んで構
成される。According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, and an input transformer that transmits an input signal to the sources of a pair of junction field effect transistors with common gates forming a differential pair circuit on the semiconductor substrate. , a constant current source inserted between the middle point of the secondary winding of the input transformer and ground, and supplying a constant current to the sources of the pair of junction field effect transistors, respectively.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図は本発明をミキサー回路に実施した場合の一実施
例を示す半導体集積回路装置の接続回路図である０本実
施例によれば、本発明の半導体集積回路装置１０は、差
動対を形成するゲート接地の一対のジャンクションＦＥ
Ｔ１および２と、２次側リード端子Ｔ、、Ｔ２からジャ
ンクションＦＥＴ１および２のソース端子にそれぞれ信
号入力を伝達する入力トランスＴと、入力トランスＴの
２次巻線の中点を介しジャンクションＦＥＴＩおよび２
のそれぞれのソース端子に定電流を供給するトランジス
タ３，４．抵抗５および定電圧源６とから成る定電流回
路とを含む、ここで、Ｃはバイパス用コンデンサ、Ｔ３
〜Ｔフはそれぞれリード端子＋ Ｔ １０１ ＋ Ｔ
１０２は入力トランスＴの１次側信号入力端子である。FIG. 1 is a connection circuit diagram of a semiconductor integrated circuit device showing an embodiment of the present invention applied to a mixer circuit. According to this embodiment, the semiconductor integrated circuit device 10 of the present invention has a differential pair. A pair of junctions FE with gate ground forming
T1 and 2, and an input transformer T that transmits the signal input from the secondary side lead terminals T, T2 to the source terminals of junction FETs 1 and 2, respectively, and junctions FETI and FETI through the middle point of the secondary winding of input transformer T. 2
Transistors 3, 4 . supplying a constant current to their respective source terminals. a constant current circuit consisting of a resistor 5 and a constant voltage source 6, where C is a bypass capacitor and T3
~T is each lead terminal + T 101 + T
102 is a primary side signal input terminal of the input transformer T.
ここで、入力端子１０１．１０５から入り入力トランス
Ｔで変圧された入力信号は、それぞれ２次側のリード端
子Ｔ、、’ｒ２からジャンクションＦＥＴ１および２の
ソースにそれぞれ導びかれ、差動対増幅回路で増幅され
てそれぞれのドレインからリード端子Ｔ、、’ｒ、を介
して出力される。一方、入力トランスＴの２次側巻線の
中間点はリード端子Ｔ３に接続され、さらにトランジス
タ３．４．抵抗Ｒおよび定電圧源６とから成る定電流源
に接続される。この定電圧源６には電源供給用リード端
子Ｔ６とから電源電圧が供給される。また、Ｔ７はアー
ス用リード端子である。Here, the input signals that enter from input terminals 101 and 105 and are transformed by the input transformer T are guided from the secondary side lead terminals T, , 'r2 to the sources of junction FETs 1 and 2, respectively, and are amplified by a differential pair. The signals are amplified by the circuit and output from the respective drains via lead terminals T, ,'r,. On the other hand, the intermediate point of the secondary winding of the input transformer T is connected to the lead terminal T3, and the transistors 3.4. It is connected to a constant current source consisting of a resistor R and a constant voltage source 6. A power supply voltage is supplied to this constant voltage source 6 from a power supply lead terminal T6. Moreover, T7 is a lead terminal for grounding.
本実施例の回路構成によれば、ジャンクションＦＥＴ１
および２の各動作電流はトランジスタ３のコレクタ電流
で決定される。また、このトランジスタ３のコレクタ電
流は定電圧回路６で与えられた所定の定電圧と、抵抗５
で設定されるトランジスタ４および抵抗５とからなるカ
レントミラー回路電流とによって与えられる。従って、
定電圧回路６から供給される所定の定電圧に対して抵抗
５の値を任意に選ぶことによって、ジャンクションＦＥ
ＴＩおよび２の動作電流を任意に設定することができる
。According to the circuit configuration of this embodiment, the junction FET1
and 2 are determined by the collector current of transistor 3. In addition, the collector current of this transistor 3 is a predetermined constant voltage given by a constant voltage circuit 6 and a resistor 5.
A current mirror circuit current consisting of a transistor 4 and a resistor 5 is set as follows. Therefore,
By arbitrarily selecting the value of the resistor 5 for a predetermined constant voltage supplied from the constant voltage circuit 6, the junction FE
The operating currents of TI and 2 can be set arbitrarily.
以上の説明から明らかなように、本発明によれば、従来
の半導体集積回路装置がジャンクションＦＥＴのカット
オフ電圧等の特性のバラツキによって、動作電流が大き
く変動するのに対し、定電流源をチップ上に付加するこ
とで、そのバラツキを抑えることができるので、特性劣
化の少ない差動対ジャンクションＦＥＴ増幅器を構成す
る半導体集積回路装置を容易に提供することが可能であ
る。As is clear from the above description, according to the present invention, while the operating current of conventional semiconductor integrated circuit devices fluctuates greatly due to variations in characteristics such as the cutoff voltage of the junction FET, the constant current source is By adding it above, it is possible to suppress the variation, so it is possible to easily provide a semiconductor integrated circuit device constituting a differential pair junction FET amplifier with less deterioration of characteristics.
第１図は本発明をミキサー回路に実施した場合の一実施
例を示す半導体集荷回路装置の接続回路図、第２図は従
来の差動対ジャンクションＦＥＴｔ界効果トランジスタ
回路を搭載した高周波半導体集積回路装置の接続回路図
、第３図は従来回路構成におけるジャンクションＦＥＴ
の動作特性図である。
Ｔ１〜Ｔ７・・・リード端子、１，２・・・ジャンクシ
ョンＦＥＴ、３，４・・・バイポーラ・トランジスタ、
５・・・抵抗、６・・・定電圧源、Ｔ １０１ ＋ ７
１０２・・・信号入力端子、Ｃ・・・バイパスコンデン
サ、Ｔ・・・入力トランス。Fig. 1 is a connection circuit diagram of a semiconductor integrated circuit device showing an embodiment of the present invention applied to a mixer circuit, and Fig. 2 is a high frequency semiconductor integrated circuit equipped with a conventional differential pair junction FET field effect transistor circuit. Device connection circuit diagram, Figure 3 shows the junction FET in the conventional circuit configuration.
FIG. T1 to T7... Lead terminal, 1, 2... Junction FET, 3, 4... Bipolar transistor,
5... Resistor, 6... Constant voltage source, T 101 + 7
102...Signal input terminal, C...Bypass capacitor, T...Input transformer.
Claims (1)
するゲート接地の一対のジャンクション電界効果トラン
ジスタと、前記一対のジャンクション電界効果トランジ
スタのソースにそれぞれ入力信号を伝達する入力トラン
スと、前記入力トランスの２次巻線の中点と接地との間
に挿入され前記一対のジャンクション電界効果トランジ
スタのソースにそれぞれ定電流を供給する定電流源とを
含むことを特徴とする半導体集積回路装置。a semiconductor substrate, a pair of junction field effect transistors with common gates forming a differential pair circuit on the semiconductor substrate, an input transformer that transmits input signals to sources of the pair of junction field effect transistors, and the input transformer. a constant current source inserted between the middle point of the secondary winding of the transistor and ground, and supplying a constant current to the sources of the pair of junction field effect transistors, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63099903A JPH01270403A (en) | 1988-04-21 | 1988-04-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63099903A JPH01270403A (en) | 1988-04-21 | 1988-04-21 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01270403A true JPH01270403A (en) | 1989-10-27 |
Family
ID=14259735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63099903A Pending JPH01270403A (en) | 1988-04-21 | 1988-04-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01270403A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995011549A1 (en) * | 1993-10-19 | 1995-04-27 | Tokyo Tsuki Co., Ltd. | Direct-current impressing circuit |
| JP2015106906A (en) * | 2013-12-03 | 2015-06-08 | 日本電信電話株式会社 | Wireless receiver |
-
1988
- 1988-04-21 JP JP63099903A patent/JPH01270403A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995011549A1 (en) * | 1993-10-19 | 1995-04-27 | Tokyo Tsuki Co., Ltd. | Direct-current impressing circuit |
| AU677444B2 (en) * | 1993-10-19 | 1997-04-24 | Tokyo Tsuki Co., Ltd. | Direct-current impressing circuit |
| US5796279A (en) * | 1993-10-19 | 1998-08-18 | Tokyo Tsuki Co., Ltd. | DC application circuit with suppressed DC magnetization |
| JP2015106906A (en) * | 2013-12-03 | 2015-06-08 | 日本電信電話株式会社 | Wireless receiver |
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