JPH01268151A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01268151A JPH01268151A JP9759488A JP9759488A JPH01268151A JP H01268151 A JPH01268151 A JP H01268151A JP 9759488 A JP9759488 A JP 9759488A JP 9759488 A JP9759488 A JP 9759488A JP H01268151 A JPH01268151 A JP H01268151A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- disposed
- insulating film
- electrode layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000010410 layer Substances 0.000 claims abstract description 121
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 abstract description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 239000004411 aluminium Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 32
- 238000000034 method Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、１つの半導体基板上に順次半導体素子を２層
以上に形成してなる積層構造素子を有する半導体装置に
関し、更に詳しくはその積層構造素子の縦方向の配線、
いわゆる縦型配線の改良に関するものである。Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a semiconductor device having a laminated structure element formed by sequentially forming two or more layers of semiconductor elements on one semiconductor substrate, and more specifically, Vertical wiring of laminated structure elements,
This relates to the improvement of so-called vertical wiring.
（ロ）従来の技術
従来のこの種装置としては２層構造のＭＯ８型半導体装
置が知られている。(B) Prior Art As a conventional device of this type, a two-layer structure MO8 type semiconductor device is known.
すなわち、第３図＋ｃｂに示すように、シリコン基板上
に下層素子が配設され、酸化シリコンからなる層間絶縁
膜上に単結晶シリコンの薄膜を形成することにより上層
素子が配設されている。That is, as shown in FIG. 3+cb, lower layer elements are disposed on a silicon substrate, and upper layer elements are disposed by forming a thin film of single crystal silicon on an interlayer insulating film made of silicon oxide.
以下、製造方法について説明する。The manufacturing method will be explained below.
まず、下層素子を形成する。下層素子は、第３図（ａｌ
に示すように、Ｐ型シリコン基板１上に、Ｎ十領域２，
３および酸化シリコンＩｌ！ ４を介してＮ＋ポリシリ
コンからなるゲート５が形成され、また、Ｎ十領域２，
３のそれぞれから素子形成領域外にまで延設されたタン
グステンシリサイドからなる接続部６，７が配設されて
いる。８は酸化シリコン層、９はＰＳＧである。First, a lower layer element is formed. The lower layer elements are shown in Figure 3 (al
As shown in FIG.
3 and silicon oxide Il! A gate 5 made of N+ polysilicon is formed via the N+ region 2,
Connecting portions 6 and 7 made of tungsten silicide are provided extending from each of the connecting portions 3 to outside the element forming region. 8 is a silicon oxide layer, and 9 is PSG.
次に、上記の下層素子を形成した後、素子上にＣＶＤ法
により酸化シリコンを積層してエッチバック法による平
坦化処理をおこない下層素子と以後に形成される上層素
子とを分離する層間絶縁膜１０を形成する［第３図（ｂ
〉参照コ。Next, after forming the above-mentioned lower layer element, silicon oxide is laminated on the element by CVD method and planarization treatment is performed by etch-back method to form an interlayer insulating film that separates the lower layer element from the upper layer element to be formed later. 10 [Fig. 3(b)
〉Reference.
そして、絶縁膜１０上にＣＶＤ法によって多結晶シリコ
ン膜を形成し、その後これをレーザど一方や電子ビーム
等によって溶融再結晶化して単結晶シリコン層１１を形
成するＵ第３図（Ｃ）参照Ｊ。Then, a polycrystalline silicon film is formed on the insulating film 10 by the CVD method, and then this is melted and recrystallized using a laser beam, an electron beam, etc. to form a single crystal silicon layer 11. See FIG. 3(C). J.
次に、通常の工程にて単結晶の上層素子を形成する。こ
の上層素子には、接続端子、すなわち、素子のＰ＋領域
１２．１３およびこれらに挾まれたＮ領域１４上の酸化
シリコン膜１５を介してＮ＋ボ１ノシ１ノコンからなる
ゲート１６が形成され、下層素子の一方の接続部６に対
応する所の絶縁膜１０に縦型配線用の接続孔１７を設【
プ、この接続孔を含む上層素子の配線領域だけにスパッ
タ法により配線用アルミニウム膜を形成して略２虐の配
線長を有する縦型配線部分１８ａおよび接続端子部分１
８ｂ、１８ｃを形成する［第３図（小参照］。Next, a single-crystal upper layer element is formed in a normal process. In this upper layer element, a connecting terminal, that is, a gate 16 consisting of one N+ board and one contact is formed via a silicon oxide film 15 on the P+ region 12, 13 of the element and the N region 14 sandwiched between these. A connection hole 17 for vertical wiring is provided in the insulating film 10 at a location corresponding to one connection portion 6 of the lower layer element.
Then, an aluminum film for wiring is formed by sputtering only in the wiring area of the upper layer element including the contact hole, thereby forming a vertical wiring portion 18a and a connecting terminal portion 1 having a wiring length of about 200 mm.
8b and 18c [see FIG. 3 (small reference)].
このようにして２層構造のＭＯ８型半導体装置が製造さ
れる。In this way, an MO8 type semiconductor device with a two-layer structure is manufactured.
（ハ）発明が解決しようとする課題
しかし、上述のごとぎ２層構造においては、−方のＮ＋
領域２とＰ＋領域１２とをこのＰ十領域に接続する接続
端子部分１８ｂを介して接続するから、下層素子に接続
部６を設ける必要があり、しかも接続部６と縦型配線部
分１８ａとの接続は、いわゆる素子形成領域の外側でお
こなう必要があり、上層素子と下層素子との配線領域が
横方向に広くなり素子を高密度化することか難しい。さ
らに、上層素子の接続端子部分１８ｂや接続部６の引き
回しによる抵抗の増大が発生ずるおそれがある。また、
接続７Ｌ１７は深くて微細な形状のため、接続孔に縦型
配線部分１８ａを形成しても接続孔をすきまなく埋める
ことば難しく、断線を発生するおそれかあるとともに、
配線領域は縦方向にも広がることになる。(c) Problems to be solved by the invention However, in the above-mentioned two-layer structure, the negative N+
Since the region 2 and the P+ region 12 are connected via the connection terminal portion 18b that connects to the P+ region, it is necessary to provide the connection portion 6 in the lower layer element, and moreover, it is necessary to provide the connection portion 6 and the vertical wiring portion 18a. Connections must be made outside the so-called element formation area, and the wiring area between the upper layer element and the lower layer element becomes wider in the lateral direction, making it difficult to increase the density of the elements. Furthermore, there is a risk that resistance will increase due to the routing of the connection terminal portion 18b of the upper layer element and the connection portion 6. Also,
Since the connection 7L17 has a deep and fine shape, even if the vertical wiring portion 18a is formed in the connection hole, it is difficult to fill the connection hole without any gaps, and there is a risk of disconnection.
The wiring area will also expand in the vertical direction.
この発明は、１つの基板上に順次半導体素子を２層以上
形成した積層構造の半導体装置において、居間の配線を
短く、低抵抗におこなうことができるとともに、断線を
防止できる半導体装置を提供することを目的の一つとす
るものである。An object of the present invention is to provide a semiconductor device having a stacked structure in which two or more layers of semiconductor elements are sequentially formed on one substrate, in which wiring in a living room can be shortened and have low resistance, and disconnection can be prevented. is one of its objectives.
（ニ）課題を解決するための手段
この発明は、１つの半導体基板上に順次半導体素子を２
層以上に形成してなる積層構造を有するとともに、各層
間絶縁膜を介してそれぞれ上側に配設された半導体素子
の所定の１つの第１電極層と、それぞれ下側に配設され
た半導体素子の電極層のうち上記第１Ｎ極層直下の１つ
の第２電極層とを共通接続し、それによって居間の電気
接続をおこなうための縦型配線を有する半導体装置にお
いて、上記縦型配線を、上端部が上記第１電極層を介し
てあるいは第１電極層を貫通して上記上側の半導体素子
上に配設された接続端子に接続され、下端部が上記第２
電極層に接続され、それによっ−四 −
て上記第１および第２電極層の接続を実質的に層間絶縁
膜のみを介して最短距離でおこないうる内部配線用接続
孔と、この接続孔に選択的に埋め込まれ上記上側および
下側の半導体素子を導通しうる導体とから構成した半導
体装置である。(d) Means for Solving the Problems This invention provides two semiconductor devices in sequence on one semiconductor substrate.
A predetermined first electrode layer of a semiconductor element, which has a laminated structure formed of more than one layer, and is disposed on the upper side through each interlayer insulating film, and the semiconductor element is disposed on the lower side, respectively. In a semiconductor device having a vertical wiring for commonly connecting one second electrode layer immediately below the first N-pole layer among the electrode layers, thereby establishing an electrical connection in the living room, the vertical wiring is connected to the upper end of the semiconductor device. The lower end portion is connected to the connection terminal provided on the upper semiconductor element through or through the first electrode layer, and the lower end portion is connected to the connection terminal provided on the upper semiconductor element.
An internal wiring connection hole that is connected to the electrode layer and thereby allows connection of the first and second electrode layers through the shortest distance substantially only through the interlayer insulating film, and this connection hole is selected. This is a semiconductor device comprising a conductor that is embedded in the conductor and can conduct the upper and lower semiconductor elements.
すなわち、この発明は、層間絶縁膜の上側に配設された
半導体素子の第１電極層と層間絶縁膜を介して下側に配
設された半導体素子における上記第１電極層直下の第１
電極層とを、居間絶縁膜を最短距離で貫通させて配設し
た内部配線用接続孔によって直接に接続し、さらに、こ
の接続孔に導体を選択的に埋め込んで縦型配線を素子形
成領域内に配設したものである。That is, the present invention provides a first electrode layer of a semiconductor element disposed above an interlayer insulating film, and a first electrode layer immediately below the first electrode layer of a semiconductor element disposed below the interlayer insulating film.
The electrode layer is directly connected to the internal wiring connection hole, which is provided by penetrating the living room insulating film at the shortest possible distance. Furthermore, a conductor is selectively buried in this connection hole to connect the vertical wiring within the element formation area. It was placed in
この発明における半導体基板としては、導電型のシリコ
ン基板やザファイヤ基板あるいはＧａＡＳ等が好ましい
ものとして挙げられる。さらに、ＩｎＰも適用可能であ
る。Preferred examples of the semiconductor substrate in the present invention include a conductive type silicon substrate, a zaphire substrate, GaAS, and the like. Furthermore, InP is also applicable.
この発明における層間絶縁膜としては、材料として酸化
シリコンやＰＳＧ、あるいはＢＰＳＧ等か好ましいもの
どじて挙げられる。さらに、酸窒そして、各層間絶縁膜
上に配設される半導体素子は、単結晶のものが好ましく
、その形成方法としては、（＋）固相成長法、（ｉｉ）
多結晶シリコン膜やアモルファスシリコン膜をレーザビ
ームなどで溶融再結晶化する方法等が挙げられる。Preferred materials for the interlayer insulating film in the present invention include silicon oxide, PSG, and BPSG. Furthermore, the semiconductor element disposed on the oxynitride and each interlayer insulating film is preferably a single crystal, and its formation method includes (+) solid phase growth method, (ii)
Examples include a method of melting and recrystallizing a polycrystalline silicon film or an amorphous silicon film using a laser beam or the like.
例えば、１枚の導電型のシリコン基板上に順次配設され
るＭＯ８型半導体素子構造のものでは、酸化シリコン層
上に単結晶シリコンの薄膜を成長させる、いわゆるＳ
ＯＩ （Ｓ １ｌｉｃｏｎ−Ｏｎ−１ｎ５Ｕｌａｔｏｒ
）法によって形成されるのが好ましく、また、積層され
る半導体素子をサファイヤ基板上に、いわゆるＳＯ８法
によって形成しても良い。For example, in an MO8 type semiconductor device structure that is sequentially arranged on a single conductive silicon substrate, a thin film of single crystal silicon is grown on a silicon oxide layer.
OI (S 1licon-On-1n5Ulator
) method, and the semiconductor elements to be stacked may be formed on a sapphire substrate by the so-called SO8 method.
この発明において、上側の半導体素子上に配設された接
続端子とは、例えばスパッタ法によりその半導体素子上
の配線領域に形成され第１電極層と接続する配線用アル
ミニウム膜を意味する。In this invention, the connection terminal disposed on the upper semiconductor element means an aluminum film for wiring formed in the wiring region on the semiconductor element by sputtering, for example, and connected to the first electrode layer.
この発明において、第１および第２電８ｉ層の接続を実
質的に層間絶縁膜のみを介して最短距離でおこないうる
とは、層間絶縁膜の上側に配設された半導体素子（上層
素子）と下側に配設された半導体素子（下層素子）との
縦型配線を上層素子上に配設された接続端子部分を介し
ておこなうのではなく、第１電ｔｆ！層（上部電極層）
および第２電極層（下部電極層）間で真直なトンネルを
層間絶縁膜を縦方向に除去して開通させることにより、
縦型配線を、いわゆる素子形成領域内でおこなうことを
意味する。In this invention, the fact that the first and second electrical layers can be connected via the shortest distance substantially only through the interlayer insulating film means that the semiconductor element (upper layer element) disposed above the interlayer insulating film Vertical wiring with the semiconductor element (lower layer element) disposed on the lower side is not performed via the connection terminal portion disposed on the upper layer element, but rather through the first electric wire tf! layer (upper electrode layer)
By vertically removing the interlayer insulating film and opening a straight tunnel between the second electrode layer (lower electrode layer),
This means that vertical wiring is performed within the so-called element formation region.
この発明において、内部配線用接続孔は、０）下層素子
上にエッチバック法により居間絶縁膜を形成した後、既
知の写真蝕刻法およびドライエツチングにより形成され
たり、（ｉｉ）下層素子上に層間絶縁膜を介して上層素
子を形成し、その後接続端子を形成する前に上部Ｎ極層
を貫通して形成したりするのが好ましい。そして、この
接続孔の径は０．２〜２ｐ７ａが好ましく、０．５虐が
より好ましく、接続孔の長さ（配線長）は、（１）の場
合０．５〜４，７１１が好ましく、 １．Ｗがより好ま
しく、（ｉｉ）の場合０．８〜５所か好ましく、 １．
５廚がより好ましい。In this invention, the connection hole for internal wiring is formed by 0) forming an insulating film on the lower layer element by an etch-back method and then using known photolithography and dry etching, or (ii) forming an interlayer on the lower layer element. It is preferable to form an upper layer element through an insulating film, and then form the upper N-pole layer by penetrating the upper N-pole layer before forming the connection terminal. The diameter of this connection hole is preferably 0.2 to 2p7a, more preferably 0.5p7a, and the length (wiring length) of the connection hole is preferably 0.5 to 4,711 in the case of (1). 1. W is more preferred, and in the case of (ii), 0.8 to 5 locations are preferred; 1.
5 degrees is more preferable.
この発明における導体としては、ＷやＭｏ、あるいはＴ
ａ等の金属が好ましいものとして挙げられる。八ρも適
用可能である。The conductor in this invention may be W, Mo, or T.
Preferable examples include metals such as a. Eight rho is also applicable.
この発明においては、導体を内部配線用接続孔に選択的
に埋め込むことによって埋め込まれた導体の選択成長に
よりスパッタ法やＣＶＤ法等による埋め込みとは異なり
、接続孔に内壁面の材料に依存せずに確実に導体がすき
まなく埋め込まれる。In this invention, by selectively embedding a conductor in the connection hole for internal wiring, the buried conductor grows selectively, and unlike embedding by sputtering or CVD, the connection hole does not depend on the material of the inner wall surface. to ensure that the conductor is embedded without any gaps.
（ボ）作用
上記構成により、縦型配線を、上部および下部電極層を
層間絶縁膜のみを介して接続する接続孔と、この接続孔
に選択的に埋め込まれた導体とから構成したことから、
縦型配線を最短長にできるとともに、接続孔を導体です
きまなく埋め込むことができる。(B) Effect With the above configuration, the vertical wiring is composed of a connection hole that connects the upper and lower electrode layers only through the interlayer insulating film, and a conductor selectively embedded in this connection hole.
Vertical wiring can be made as short as possible, and connection holes can be filled with conductor without any gaps.
（へ）実施例 以下図に示す実施例にもとづいてこの発明を詳述する。(f) Example The present invention will be described in detail below based on embodiments shown in the figures.
なお、これによってこの発明は限定を受けるものではな
い。Note that this invention is not limited by this.
第１図は、シリコン基板上に形成された２層構造のＭＯ
８型半導体装置を示す。この半導体装置は、Ｐ型シリコ
ン基板上に下層素子が配設され、上層素子は酸化シリコ
ンからなる層間絶縁膜上に単結晶シリコンの薄膜を形成
することにより配設される。Figure 1 shows a two-layer MO formed on a silicon substrate.
An 8-type semiconductor device is shown. In this semiconductor device, lower layer elements are arranged on a P-type silicon substrate, and upper layer elements are arranged by forming a thin film of single crystal silicon on an interlayer insulating film made of silicon oxide.
すなわち、第１図（ｅ）に示すように、下層素子りは、
（１００）面を用いた比抵抗２０Ω’ ｃｍのＰ型シリ
コン基板２１上にＮ＋シリコンからなる電極層２２．２
３が配設されるとともに、酸化シリコンからなるゲート
絶縁膜２４を介してゲート２５が配設されている。２６
．２７は酸化シリコン層、２８は電極層２３から延設さ
れた接続部、２９ ．３０ ．３１はＰＳＧである。That is, as shown in FIG. 1(e), the lower layer element is
An electrode layer 22.2 made of N+ silicon is placed on a P-type silicon substrate 21 with a specific resistance of 20 Ω' cm using a (100) plane.
3 is provided, and a gate 25 is also provided with a gate insulating film 24 made of silicon oxide interposed therebetween. 26
．． 27 is a silicon oxide layer; 28 is a connecting portion extending from the electrode layer 23; 29. 30. 31 is PSG.
一方、上層素子Ｕには下層素子り上の膨化シリコンから
なる層間絶縁膜３２を介して電極層２２および２３の直
上にそれぞれＰ＋シリコンからなる電極層３３および３
４が配設されるとともに、素子表面にアルミニラ膜から
なる接続端子３５ 。On the other hand, in the upper layer element U, electrode layers 33 and 3 made of P+ silicon are provided directly above the electrode layers 22 and 23, respectively, via an interlayer insulating film 32 made of expanded silicon on the lower layer element.
4 is disposed, and a connection terminal 35 made of an aluminum film is provided on the surface of the element.
３６が配設されている。この一方の接続端子３５は一方
の電極層（以下、上部電極層と称呼す。）３３に接続さ
れ、他方の電極層３４には接続端子３６が接続されてい
る。３７はゲート絶縁膜３８上に配設されたＮ＋ポリシ
リコンからなるゲート、３９はＮ型シリコン層、４０．
４１は酸化シリコン層、４２ ．４３．４４はＰＳＧで
ある。36 are arranged. This one connection terminal 35 is connected to one electrode layer (hereinafter referred to as an upper electrode layer) 33, and the other electrode layer 34 is connected to a connection terminal 36. 37 is a gate made of N+ polysilicon disposed on the gate insulating film 38; 39 is an N-type silicon layer; 40.
41 is a silicon oxide layer; 42. 43.44 is PSG.
さらに、縦型配線は、上部電極層３３および電極層（以
下、下部電極層）２２間で層間絶縁膜３２を貫通して配
設された縦方向に真直な接続孔４５と、その内部に埋め
込まれたタングステンからなる導体層４５ａとで構成さ
れている。Furthermore, the vertical wiring includes a vertically straight connection hole 45 provided through the interlayer insulating film 32 between the upper electrode layer 33 and the electrode layer (hereinafter referred to as the lower electrode layer) 22, and a connection hole 45 buried therein. The conductor layer 45a is made of tungsten.
次に製造方法について説明する。Next, the manufacturing method will be explained.
まず、Ｐ型シリコン基板２１の表面に以後に形成される
上層素子Ｕとの配線工程を除いて、通常の工程で下層索
子りを形成する［Ｍ１図（ａＪ参照３０次に、ＣＶＤ法
により酸化シリコンを積層してこれにエッチバック法に
より非選択エツチングを行い、平坦化処理をして層間絶
縁膜３２を形成し、これに写真蝕刻法とドライエツチン
グにより、上層素子Ｕとの接続孔４５を開孔する「第１
図＋ｂ＋参照」。First, a lower layer is formed on the surface of the P-type silicon substrate 21 by a normal process, except for the wiring process with the upper layer element U that will be formed later. Silicon oxide is laminated, non-selective etching is performed on this using an etch-back method, and an interlayer insulating film 32 is formed by planarization, and a connecting hole 45 with the upper layer element U is formed by photolithography and dry etching. The first hole is drilled.
See figure + b +.
次に、ＣＶＤ法によりタングステンを選択的に接続孔４
５に埋め込み導体層４５ａを形成する［第１図（Ｃ）参
照］。Next, tungsten is selectively deposited in the contact hole 4 by CVD method.
A buried conductor layer 45a is formed on the substrate 5 [see FIG. 1(C)].
次に、ＣＶＤ法により多結晶シリコンを０．５虐形成し
、レーザビームにより、溶融固化することにより、単結
晶シリコン層２３を形成する［第１図＋ｄ＋参照］。Next, a polycrystalline silicon layer 23 is formed by forming polycrystalline silicon to a thickness of 0.5 by CVD and melting and solidifying it by a laser beam [see FIG. 1+d+].
次に通常の工程により、この単結晶シリコン層２３上に
所望の上層素子Ｕを形成することにより、半導体装置を
作製する［第１図（ｅ）参照］。Next, a desired upper layer element U is formed on this single-crystal silicon layer 23 by a normal process to produce a semiconductor device [see FIG. 1(e)].
このような構成の半導体装置では、縦型ｌＩｉ！線を素
子形成領域内に配設したので、配線領域が狭く、また配
線長が短くなって素子の高密度化、高速化か可能となる
。In a semiconductor device having such a configuration, vertical lIi! Since the lines are arranged within the element formation area, the wiring area is narrow and the wiring length is shortened, making it possible to increase the density and speed of the elements.
さらにタングステンの選択成長により、接続孔４５の埋
め込みが形成されるため高信頼性の配線が可能となり、
また接続部２８を１つだ〔プ配股するだけで良い等多く
の利点を有する。Furthermore, by selectively growing tungsten, the connection hole 45 is filled, making highly reliable wiring possible.
It also has many advantages, such as requiring only one connecting portion 28.
第２図は、接続孔がその上端部が上部電極層を貫通して
配設されたこの発明の他の実施例を示す。FIG. 2 shows another embodiment of the invention in which the connection hole is disposed with its upper end penetrating the upper electrode layer.
すなわち、第２図（ｅ）に示すように、縦型配線は、−
１１＝
上端部４６ａが上部電極層３３内に位置した接続孔４６
とこれに埋め込まれたタングステンよりなる導体層４７
から構成されている。That is, as shown in FIG. 2(e), the vertical wiring is -
11= Connection hole 46 whose upper end portion 46a is located within the upper electrode layer 33
and a conductor layer 47 made of tungsten embedded therein.
It consists of
次に製造方法について説明する。Next, the manufacturing method will be explained.
まず（１００）面を用いた比抵抗２０Ω・側のＰ型シリ
コン基板２１の表面に上層素子Ｕおよび下層素子１−２
層の素子間の縦型配線を除いて、通常の工程で２層の素
子ＵおよびＬを途中工程まで形成し、上層素子Ｕ上にＰ
ＳＧ５０を積層する［第２図（ａ）参照］。First, the upper layer element U and the lower layer element 1-2 are placed on the surface of the P-type silicon substrate 21 on the resistivity 20Ω side using the (100) plane.
Except for the vertical wiring between the elements in the layer, the two-layer elements U and L are formed halfway through the normal process, and the P layer is placed on the upper layer element U.
SG50 is laminated [see FIG. 2(a)].
次に写真蝕刻法とドライエツチングにより、上層素子Ｕ
および下層素子り間の接続孔４６を形成づる［第２図（
ｂ）参照］。Next, the upper layer element U is etched by photolithography and dry etching.
and a connecting hole 46 between the lower layer elements [Fig. 2 (
See b)].
次にＣＶｆ）法でタングステンを５０ｎｍ全面に形成し
、ドライエツチングを施して接続孔４６の内壁のみに中
空導体層４７ａを形成する［第２図（Ｃ）参照］。Next, tungsten is formed to a thickness of 50 nm over the entire surface using the CVf method, and dry etching is performed to form a hollow conductor layer 47a only on the inner wall of the contact hole 46 [see FIG. 2(C)].
次にＣＶＤ法でさらにタングステンを選択的に接続孔４
６のみに形成して導体層４７を形成する［第２図（ｄ＋
参照］。Next, using the CVD method, tungsten is selectively added to the contact hole 4.
6 to form a conductor layer 47 [Fig. 2 (d+
reference].
次に通常の工程により、上層素子Ｕの配線工程を進めれ
ば第２図（ｅ）に示す半導体装置を得ることができる。Next, by proceeding with the wiring process of the upper layer element U according to the usual process, the semiconductor device shown in FIG. 2(e) can be obtained.
このようなｍ成の半導体素子では、縦型配線の配線長が
上層素子Ｕの高さ分だけ長くなっても、接続孔４６の内
壁のみに中空導体層４７ａを形成した後に選択成長によ
って導体層４７を形成するから、長い接続孔４６をすき
まなく埋め込むことができる。In such an m-structured semiconductor element, even if the length of the vertical wiring is increased by the height of the upper layer element U, the conductor layer is formed by selective growth after forming the hollow conductor layer 47a only on the inner wall of the connection hole 46. 47, the long connection hole 46 can be filled without any gaps.
（ト）発明の効果
以上のように本発明によれば、１つの半導体基板上に順
次半導体素子を２層以上に形成してなる積層構造を有す
る半導体装置において、縦型配線を、素子形成領域内に
配設され上層素子と下層素子とを層間絶縁膜のみを介し
て接続する接続孔と、この接続孔に選択的に埋め込まれ
た導体とから構成したので、次のような効果を右する。(G) Effects of the Invention As described above, according to the present invention, in a semiconductor device having a laminated structure in which semiconductor elements are sequentially formed in two or more layers on one semiconductor substrate, vertical wiring is connected to the element forming area. The structure consists of a connection hole that connects the upper layer element and the lower layer element only through an interlayer insulating film, and a conductor that is selectively embedded in this connection hole, so it has the following effects. .
１、積層構造素子の縦方向の配線が最短で、狭くなるた
め、素子を高速化、高密度化できる。1. Since the vertical wiring of the stacked structure element is shortest and narrowest, the element can be made faster and more dense.
２、微細で深い接続孔を金属の選択成長法で埋め込むた
め高信頼性の配線ができる。2. Highly reliable wiring is possible because the fine and deep connection holes are filled using a selective metal growth method.
第１図（の〜（ｅ）は、それぞれ本発明の一実施例を説
明するための工程図、第２図（ａ〜（ｅｌはそれぞれ本
発明の他の実施例を説明するための工程図、第３図くω
〜＋ｄ＋はそれぞれ従来例を説明するための工程図であ
る。
２１・・・・・・Ｐ型シリコン基板、
２２・・・・・・下部電極層（第２電極層）、３２・・
・・・・層間絶縁膜、
３３・・・・・・上部電極層（第１電極層）、３５・・
・・・・接続端子、
４５．４６・・・・・・内部配線用接続孔、４５ａ
、４７・・・・・・導体層。
ヘヘ
」 Ｉ
−）」
マ 寸 （Ｎ（ＮFigures 1 (--(e) are process diagrams for explaining one embodiment of the present invention, respectively, and Figures 2 (a-(el) are process diagrams for explaining other embodiments of the present invention, respectively. , Figure 3 ω
-+d+ are process diagrams for explaining conventional examples, respectively. 21... P-type silicon substrate, 22... Lower electrode layer (second electrode layer), 32...
...Interlayer insulating film, 33... Upper electrode layer (first electrode layer), 35...
... Connection terminal, 45.46 ... Connection hole for internal wiring, 45a
, 47... Conductor layer. Hehe” I -)” Ma size (N(N
Claims (1)
形成してなる積層構造を有するとともに、各層間絶縁膜
を介してそれぞれ上側に配設された半導体素子の所定の
１つの第１電極層と、それぞれ下側に配設された半導体
素子の電極層のうち上記第１電極層直下の１つの第２電
極層とを共通接続し、それによつて層間の電気接続をお
こなうための縦型配線を有する半導体装置において、上
記縦型配線を、上端部が上記第１電極層を介してあるい
は第１電極層を貫通して上記上側の半導体素子上に配設
された接続端子に接続され、下端部か上記第２電極層に
接続され、それによって上記第１および第２電極層の接
続を実質的に層間絶縁膜のみを介して最短距離でおこな
いうる内部配線用接続孔と、この接続孔に選択的に埋め
込まれ上記上側および下側の半導体素子を導通しうる導
体とから構成した半導体装置。1. It has a laminated structure in which two or more layers of semiconductor elements are sequentially formed on one semiconductor substrate, and a predetermined first electrode of one of the semiconductor elements is disposed above each layer through an interlayer insulating film. A vertical type for commonly connecting the layers and one second electrode layer immediately below the first electrode layer among the electrode layers of the semiconductor element disposed below, thereby establishing an electrical connection between the layers. In a semiconductor device having wiring, an upper end of the vertical wiring is connected to a connection terminal disposed on the upper semiconductor element through or through the first electrode layer, an internal wiring connection hole whose lower end is connected to the second electrode layer, thereby allowing connection of the first and second electrode layers through the shortest distance substantially only through the interlayer insulating film; and this connection hole. a conductor that is selectively embedded in the semiconductor element and can conduct the upper and lower semiconductor elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9759488A JPH01268151A (en) | 1988-04-20 | 1988-04-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9759488A JPH01268151A (en) | 1988-04-20 | 1988-04-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01268151A true JPH01268151A (en) | 1989-10-25 |
Family
ID=14196562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9759488A Pending JPH01268151A (en) | 1988-04-20 | 1988-04-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01268151A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04252052A (en) * | 1991-01-28 | 1992-09-08 | Nec Corp | Wiring formation method for active layer laminated element |
| JP2005203777A (en) * | 2004-01-12 | 2005-07-28 | Samsung Electronics Co Ltd | Semiconductor integrated circuit for adopting laminated node-contact structure and laminated thin-film transistor, and manufacturing method thereof |
| JP2008028407A (en) * | 1997-04-04 | 2008-02-07 | Glenn J Leedy | Information processing method |
| JP2008098641A (en) * | 2006-10-11 | 2008-04-24 | Samsung Electronics Co Ltd | Nand flash memory device and manufacturing method therefor |
| JP2010114380A (en) * | 2008-11-10 | 2010-05-20 | Toshiba Corp | Semiconductor device |
| WO2012056663A1 (en) * | 2010-10-28 | 2012-05-03 | シャープ株式会社 | Circuit board, method for manufacturing same and display device |
| JP2019087761A (en) * | 2014-05-30 | 2019-06-06 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6041250A (en) * | 1983-08-15 | 1985-03-04 | Seiko Epson Corp | Semiconductor device |
| JPS62203359A (en) * | 1986-03-03 | 1987-09-08 | Mitsubishi Electric Corp | Laminated semiconductor device |
-
1988
- 1988-04-20 JP JP9759488A patent/JPH01268151A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6041250A (en) * | 1983-08-15 | 1985-03-04 | Seiko Epson Corp | Semiconductor device |
| JPS62203359A (en) * | 1986-03-03 | 1987-09-08 | Mitsubishi Electric Corp | Laminated semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04252052A (en) * | 1991-01-28 | 1992-09-08 | Nec Corp | Wiring formation method for active layer laminated element |
| JP2011181176A (en) * | 1997-04-04 | 2011-09-15 | Glenn J Leedy | Information processing method and laminated integrated circuit memory |
| JP2008028407A (en) * | 1997-04-04 | 2008-02-07 | Glenn J Leedy | Information processing method |
| JP2008166831A (en) * | 1997-04-04 | 2008-07-17 | Glenn J Leedy | Method of processing information |
| JP2008166832A (en) * | 1997-04-04 | 2008-07-17 | Glenn J Leedy | Information processing method |
| JP2008172254A (en) * | 1997-04-04 | 2008-07-24 | Glenn J Leedy | Information processing method |
| JP2005203777A (en) * | 2004-01-12 | 2005-07-28 | Samsung Electronics Co Ltd | Semiconductor integrated circuit for adopting laminated node-contact structure and laminated thin-film transistor, and manufacturing method thereof |
| JP2008098641A (en) * | 2006-10-11 | 2008-04-24 | Samsung Electronics Co Ltd | Nand flash memory device and manufacturing method therefor |
| JP2010114380A (en) * | 2008-11-10 | 2010-05-20 | Toshiba Corp | Semiconductor device |
| WO2012056663A1 (en) * | 2010-10-28 | 2012-05-03 | シャープ株式会社 | Circuit board, method for manufacturing same and display device |
| JP2019087761A (en) * | 2014-05-30 | 2019-06-06 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US10658389B2 (en) | 2014-05-30 | 2020-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method thereof, and electronic device |
| US11282860B2 (en) | 2014-05-30 | 2022-03-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method thereof, and electronic device |
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