JPH01267473A - Integrated circuit testing circuit - Google Patents
Integrated circuit testing circuitInfo
- Publication number
- JPH01267473A JPH01267473A JP63097247A JP9724788A JPH01267473A JP H01267473 A JPH01267473 A JP H01267473A JP 63097247 A JP63097247 A JP 63097247A JP 9724788 A JP9724788 A JP 9724788A JP H01267473 A JPH01267473 A JP H01267473A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- test
- signal
- circuit
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 45
- 238000007493 shaping process Methods 0.000 claims abstract description 9
- 230000010355 oscillation Effects 0.000 claims description 9
- 230000002950 deficient Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000012216 screening Methods 0.000 claims 1
- 238000005259 measurement Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の試験回路に関し、特に高速動作の限
界となるクリチカルパスの試験を容易に行うデジタル型
の集積回路試験回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit test circuit, and more particularly to a digital integrated circuit test circuit that easily tests critical paths that are the limit of high-speed operation.
従来、この種の集積回路試験回路では、所望する高速動
作で試験対象となる集積回路を動作させて、その出力波
形が試験パターンと一致可能であるか否かの判定を行っ
ていた。Conventionally, in this type of integrated circuit testing circuit, an integrated circuit to be tested is operated at a desired high speed, and a determination is made as to whether or not its output waveform can match a test pattern.
上述した従来の集積回路試験回路では、試験対象を所望
する周波数で動作させるために、高い周波数に対応した
高速度の試験器が必要となり、特に試験パターンを蓄え
る記憶装置は、超高速に読出し可能でなければならない
という欠点がある。In the conventional integrated circuit test circuits mentioned above, in order to operate the test target at the desired frequency, a high-speed tester that can handle high frequencies is required, and in particular, a memory device that stores test patterns can be read at ultra-high speed. The disadvantage is that it has to be.
本発明の集積回路試験回路は、予め作成したテストパタ
ーンとの一致性によって良品の選別を行う集積回路試験
回路において、パルス発振手段と、前記パルス発振手段
の出力パルスと同期したデユーティ比可変方形波を被試
験対象の集積回路のクロック入力端子に与えるための位
相整形手段と、前記パルス発振手段の出力パルスと同期
して予め作成したテストパターンを逐次読出可能な記憶
手段と、前記記憶手段の出力信号と被試験対象の集積回
路の出力信号とを比較する比較手段とを有し、前記被試
験対象の集積回路のクロックの高電位期間が短い場合と
、低電位期間が短い場合との２回の試験によってより高
速なクロック周波数における試験と等価な選別を行って
構成される。The integrated circuit testing circuit of the present invention is an integrated circuit testing circuit that selects non-defective products based on consistency with a test pattern created in advance, and includes a pulse oscillation means and a variable duty ratio square waveform synchronized with the output pulse of the pulse oscillation means. a phase shaping means for applying the signal to a clock input terminal of an integrated circuit under test; a storage means capable of sequentially reading test patterns prepared in advance in synchronization with the output pulses of the pulse oscillation means; and an output of the storage means. a comparison means for comparing the signal and an output signal of the integrated circuit to be tested, and twice: once when the high potential period of the clock of the integrated circuit under test is short and once when the low potential period is short. This test is equivalent to testing at a higher clock frequency.
次に、本発明について図面を参照して説明する。第１図
は本発明の一実施例の構成を示すブロック図である。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
パルスジェネレータ１は方形波を発振し、その出力であ
る、パルス信号１１は位相整形回路２とカウンタ回路３
へ導かれる。カウンタ回路３はパルス信号１１をカウン
トアツプクロックとして計数を行い、計数値信号３１を
出力する。計数値信号３１はテストバタンメモリ４のア
ドレス入力端子へ導かれる。パルスジェネレータ１の発
振周波数は、テストバタンメモリ４のアクセス時間を満
足する値に設定する。テストバタンメモリ４は信号４１
と信号４２を出力する。信号４１は被試験対象の集積回
路５の入力端子（クロック入力を除く）へ導かれ、信号
４２は比較回路６の一方の入力端子へ導かれる。A pulse generator 1 oscillates a square wave, and its output, a pulse signal 11, is sent to a phase shaping circuit 2 and a counter circuit 3.
be led to. The counter circuit 3 performs counting using the pulse signal 11 as a count-up clock, and outputs a count value signal 31. The count signal 31 is led to the address input terminal of the test button memory 4. The oscillation frequency of the pulse generator 1 is set to a value that satisfies the access time of the test button memory 4. Test button memory 4 is signal 41
and a signal 42 is output. The signal 41 is guided to the input terminal (excluding the clock input) of the integrated circuit 5 to be tested, and the signal 42 is guided to one input terminal of the comparison circuit 6.
位相整形回路２は信号１１によってトリガされて、信号
１１と同一周波数でパルス幅の異なる信号２１を出力し
て、集積回路５のクロック入力端子へ与える。集積回路
５の出力信号５１は、比較回路６の他方の入力端子へ導
かれる。比較回路６は、信号４２と信号５１との一致性
に従って信号６１を出力する。信号６１を観測して一致
を示す場合には集積回路５は正常と判定し、不一致を示
す場合には集積回路５は不良と判定する。The phase shaping circuit 2 is triggered by the signal 11 and outputs a signal 21 having the same frequency as the signal 11 but a different pulse width, and applies it to the clock input terminal of the integrated circuit 5. The output signal 51 of the integrated circuit 5 is led to the other input terminal of the comparator circuit 6. Comparison circuit 6 outputs signal 61 according to the consistency between signal 42 and signal 51. If the signals 61 are observed and show a match, the integrated circuit 5 is determined to be normal, and if they do not match, the integrated circuit 5 is determined to be defective.
発振回路１の発振周期をＴｏとすると、この時の集積回
路５の動作周波数は１ ／ Ｔ ｏである。集積回路５
に内在するクロック信号２１が高電位期間中のクリチカ
ルパスの試験を行う場合は、位相整形回路２を調整して
タロツク信号２１の高電位期間をＴ Ｈ＜ Ｔ ｏ ／
２とする。集積回路５に内在するクロック信号２１が
低電位期間中のクリチカルバスの試験を行う場合は、位
相整形回路２を再調整してクロック信号２１の低電位期
間をＴＬ＜Ｔ ｏ ／ ２とする。If the oscillation period of the oscillation circuit 1 is To, then the operating frequency of the integrated circuit 5 at this time is 1/To. integrated circuit 5
When testing a critical path during a high potential period of the clock signal 21 inherent in the clock signal 21, adjust the phase shaping circuit 2 so that the high potential period of the tarokk signal 21 is T H < T o /
Set it to 2. When testing a critical bus during a low potential period of the clock signal 21 inherent in the integrated circuit 5, the phase shaping circuit 2 is readjusted so that the low potential period of the clock signal 21 satisfies TL<T o /2.
前述の２通の試験を行うことにより、集積回路５はクロ
ック信号２１の周期がＴＩ＋ＴＬすなわち周波数１／
（ＴＨ＋’ｒｔ、 ）において動作可能であるか否かの
判定を行うことができる。このことは周波数１ ／ Ｔ
ｏによる測定にもかかわらず、等価的により高い周波
数１ ／ （ＴＨ＋ＴＬ、 ）による測定と見なすこと
ができる。By performing the two tests described above, the integrated circuit 5 has determined that the period of the clock signal 21 is TI+TL, that is, the frequency 1/
It is possible to determine whether or not it is operable at (TH+'rt, ). This means that the frequency 1/T
Despite the measurement with o, it can equivalently be considered as a measurement with the higher frequency 1/(TH+TL, ).
以上説明したように本発明は、被試験対象の集積回路の
クロックのパルス幅を変えて２回測定することにより、
等価的により高周波数のクロックを与えた場合の試験と
見なすことができ、テストバタンメモリのアクセス時間
に制限されない試験を行うことができるという効果があ
る。As explained above, the present invention measures the integrated circuit twice by changing the pulse width of the clock of the integrated circuit to be tested.
This can be equivalently regarded as a test when a higher frequency clock is applied, and has the effect that a test can be performed without being limited by the access time of the test button memory.
第１図は本発明の一実施例の構成を示すプロ・ンク図で
ある。
１・・・パルスジェネレータ、２・・・位相整形回路、
３・・・カウンタ回路、４・・・テストバタンメモリ、
５・・・被試験対象集積回路、６・・・比較回路。FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. 1... Pulse generator, 2... Phase shaping circuit,
3... Counter circuit, 4... Test button memory,
5... Integrated circuit under test, 6... Comparison circuit.
Claims (1)
選別を行う集積回路試験回路において、パルス発振手段
と、前記パルス発振手段の出力パルスと同期したデュー
ティ比可変方形波を被試験対象の集積回路のクロック入
力端子に与えるための位相整形手段と、前記パルス発振
手段の出力パルスと同期して予め作成したテストパター
ンを逐次読出可能な記憶手段と、前記記憶手段の出力信
号と被試験対象の集積回路の出力信号とを比較する比較
手段とを有し、前記被試験対象の集積回路のクロックの
高電位期間が短い場合と、低電位期間が短い場合との２
回の試験によってより高速なクロック周波数における試
験と等価な選別を行つて成ることを特徴とする集積回路
試験回路。In an integrated circuit test circuit that selects non-defective products based on consistency with a test pattern created in advance, a pulse oscillation means and a variable duty ratio square wave synchronized with the output pulse of the pulse oscillation means are used as clocks of the integrated circuit under test. a phase shaping means for applying to an input terminal; a storage means capable of sequentially reading test patterns prepared in advance in synchronization with the output pulses of the pulse oscillation means; and a comparison means for comparing the output signal with the output signal, and there are two cases in which the high potential period of the clock of the integrated circuit under test is short and the low potential period is short.
1. An integrated circuit testing circuit characterized in that the integrated circuit testing circuit performs screening equivalent to testing at a higher clock frequency by multiple tests.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63097247A JPH01267473A (en) | 1988-04-19 | 1988-04-19 | Integrated circuit testing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63097247A JPH01267473A (en) | 1988-04-19 | 1988-04-19 | Integrated circuit testing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01267473A true JPH01267473A (en) | 1989-10-25 |
Family
ID=14187254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63097247A Pending JPH01267473A (en) | 1988-04-19 | 1988-04-19 | Integrated circuit testing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01267473A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004343107A (en) * | 2003-05-05 | 2004-12-02 | Harman Becker Automotive Systems Gmbh | Method of testing photo-electric converter |
-
1988
- 1988-04-19 JP JP63097247A patent/JPH01267473A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004343107A (en) * | 2003-05-05 | 2004-12-02 | Harman Becker Automotive Systems Gmbh | Method of testing photo-electric converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100269704B1 (en) | Apparatus for testing delay circuit and integrated circuit including means for testing the same | |
| JP3625400B2 (en) | Test circuit for variable delay element | |
| US4881040A (en) | Signal generator for producing accurately timed pulse groupings | |
| US20040135606A1 (en) | Circuit and method for inducing jitter to a signal | |
| US7809521B1 (en) | Precise delay measurement through combinatorial logic | |
| US20090302917A1 (en) | Delay circuit and test method for delay circuit | |
| US6215345B1 (en) | Semiconductor device for setting delay time | |
| JP4320139B2 (en) | Timing generator and test device | |
| US5686846A (en) | Time duration trigger | |
| JPH01267473A (en) | Integrated circuit testing circuit | |
| JP2000090693A (en) | Memory test device | |
| JP3847150B2 (en) | Semiconductor integrated circuit and jitter measurement method thereof | |
| KR100336907B1 (en) | Memory testing apparatus | |
| JPS6067869A (en) | Timing signal generator | |
| JP2591849B2 (en) | Test circuit | |
| JP4422223B2 (en) | IC test equipment | |
| JP3633881B2 (en) | Semiconductor device and AC spec inspection method thereof | |
| WO1987001207A1 (en) | Harmonic sampling logic analyzer | |
| JPH11101852A (en) | Variable delay element inspection circuit | |
| JPH09145798A (en) | Timing signal generator | |
| JP2004279155A (en) | Jitter tester using sampling digitizer, method and semiconductor tester with sampling digitizer | |
| SU1467750A1 (en) | Multichannel analyzer | |
| JPH03265214A (en) | Data delay device | |
| JP2004144599A (en) | Semiconductor integrated circuit | |
| JPH0829487A (en) | Circuit for judging propriety of dut |