JPH01265610A - Input buffer circuit - Google Patents
Input buffer circuitInfo
- Publication number
- JPH01265610A JPH01265610A JP63094137A JP9413788A JPH01265610A JP H01265610 A JPH01265610 A JP H01265610A JP 63094137 A JP63094137 A JP 63094137A JP 9413788 A JP9413788 A JP 9413788A JP H01265610 A JPH01265610 A JP H01265610A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- current path
- supply potential
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体メモリ等の半導体装置に使用され、ＴＴ
Ｌ論理の信号レベルをＭＯＳ論理の信号レベルに変換す
る機能を有す入力バッファ回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for semiconductor devices such as semiconductor memories, and
The present invention relates to an input buffer circuit having a function of converting an L logic signal level to a MOS logic signal level.
従来の入力バッファ回路を第３図に示す、Ｐｌｏ、ｐＨ
はＰチャンネル型ＭＯＳトランジスタ、Ｎ１０、Ｎｌｌ
、Ｎ１２、Ｎ１３はＮチャンネル型ＭＯ３＋−ランジス
タ、レベル回路はトランジスタＮ１２、Ｎ１３から成り
、差動回路はトランジスタＰＩＯ１ｐＨ、Ｎ１０、Ｎｉ
ｌから成る、Ｆ、Ｇ、Ｈ１■は各端子節点を表わしＦは
入力端子、Ｇは出力端子に対応している、Ｖｏｏは電源
電位、ｖｓｓは接地電位である。 ゛この入力
バッファ回路は、製遺粂件（トランジスタの利得係数、
しきい値電圧）がバラついてもより安定したロジックベ
ルが得られる回路で以下その点について詳細に説明する
。A conventional input buffer circuit is shown in FIG.
are P-channel type MOS transistors, N10, Nll
, N12, N13 are N-channel type MO3+- transistors, the level circuit consists of transistors N12, N13, and the differential circuit consists of transistors PIO1pH, N10, Ni
1, F, G, and H1 represent each terminal node, F corresponds to an input terminal, G corresponds to an output terminal, Voo is a power supply potential, and vss is a ground potential.゛This input buffer circuit is based on manufacturing parameters (transistor gain coefficient,
This is a circuit that can obtain more stable logic bells even if the threshold voltage (threshold voltage) varies, and this point will be explained in detail below.
トランジスタＰＩＯ１ＮＩＯを流れる電流を１１、トラ
ンジスタｐＨ、Ｎｉｌを流れる電流を１２、トランジス
タＰ１０．Ｐ１１のトランジスタ利得係数をそれぞれβ
Ｐ、。、βｐＨ、ｔ’ランジスタＮ１０、Ｎｉｌ、Ｎ１
２、Ｎ１３のトランジスタ利得係数をそれぞれβＮ１゜
、βＮｌｌ、βＮ１２ 、βＮ口、トランジスタＰＩＯ
１Ｐｉｔのしきい値電圧をＶ、、、、）ランジスタＮｌ
０１Ｎ１１のしきい値電圧をｖｔＩ、Ｎ、この回路のロ
ジックレベルをＶ。Ｌ、Ｉ、）Ｉ各節点での電位をＶＩ
、ＶＨとする。The current flowing through the transistors PIO1NIO is 11, the current flowing through the transistors pH and Nil is 12, the transistor P10 . The transistor gain coefficient of P11 is β
P. , βpH, t' transistor N10, Nil, N1
2. The transistor gain coefficient of N13 is βN1゜, βNll, βN12, βN port, transistor PIO, respectively.
The threshold voltage of 1Pit is V, , ) transistor Nl
The threshold voltage of 01N11 is vtI, N, and the logic level of this circuit is V. L, I, )I The potential at each node is VI
, VH.
トランジスタＮｉｌ、Ｎ１３飽和領域動作とする。入力
端子Ｆの入力電位がこの回路が持つロジックレベル近傍
時は、出力端子の電位は電源電位Ｖｏｏと接地電位ＶＢ
＝の中間程度にあり、トランジスタＰＩＯ５ＮＩＯ共飽
和領域動作と言える。The transistors Nil and N13 operate in the saturation region. When the input potential of the input terminal F is near the logic level of this circuit, the potential of the output terminal is equal to the power supply potential Voo and the ground potential VB.
It can be said that the transistor PIO5NIO operates in the co-saturation region.
これらをふまえこの回路のロジックレベルＶ。Ｌを求め
る。Based on these, the logic level V of this circuit. Find L.
Ｖ Ｉ ＝’Ｖ ｎｏ Ｖ ｔｈｓ
・・・（１）Ｉ ｘ ＝ １ ／ ２βｐ＋＋
（Ｖｏｏ ＶＨＶ？ｈｐ ）２＝１／２βｐ＊（Ｖ
Ｉ−ＶｔｂＮ） ２ ・・・（２）Ｉ、＝１／２β
ｐ１゜（■。。−ＶＨ−Ｖｔ、、）’＝１／２βＮｓ
（ＶＯＬ Ｖｔｈ＋ｖ ） ２・・・（３）ただしβ
Ｎ２〉〉βＩ、簡単化のためトランジスタＮ１２のしき
いｆｒ１電圧のバックゲート効果による増加分は無視す
る。V I ='V no V ths
...(1) I x = 1 / 2βp++
(Voo VHV?hp)2=1/2βp*(V
I-VtbN) 2...(2) I, = 1/2β
p1゜(■..-VH-Vt,,)'=1/2βNs
(VOL Vth+v) 2...(3) However, β
N2>>βI, for simplicity, the increase in the threshold fr1 voltage of the transistor N12 due to the back gate effect is ignored.
式（２）より
Ｖ）（＝ＶＤＤ Ｖｔｈｐ Ｊβｒｕ＋
／ｊ９ｐ、ｌ （ＶＩ ＶｔｂＮ’）
”’（４）式（３）より
ＶａＬ＝７１３ｐ＋ｏ／１Ｊｓｒａ （ＶＤｏ Ｖ
ＨＶｔｈｐ ） ＋Ｖｔｂｎ ＝（５）式（１）、
（４）、（５）より
ＶＧＬ＝ＪβＮｌｌ °βＰＩＯ／βＮＩＯ／βｐｕ
（ＶＤＤ ２ＶｔｂＮ）十ＶｔｂＮ式（６）から
、この人力バッファ回路のロジックレベルＶ。Ｌは、ト
ランジスタ利得係数β旧０、存しないことがわかる。唯
一依存するしきい値電βＰ１１が０．２〜０．３である
ゆえ０．４■ｔｈＮ〜０ 、６ Ｖ ｔｈｎとよりエイ
キョウが少ない方向にある。From formula (2), V) (=VDD Vthp Jβru+
/j9p,l (VI VtbN')
''(4) From equation (3), VaL=713p+o/1Jsra (VDo V
HVthp ) +Vtbn = (5) Formula (1),
From (4) and (5), VGL=JβNll °βPIO/βNIO/βpu
(VDD 2VtbN) 10VtbN From equation (6), the logic level V of this human buffer circuit. It can be seen that L does not exist when the transistor gain coefficient β is 0. Since the only dependent threshold voltage βP11 is 0.2 to 0.3, it is 0.4 thN~0, 6 V thn, which is a direction in which there is less radiation.
半導体メモリの入力信号としては、半導体メモリチップ
の選択、非選択状態を制御するチップイネーブル信号な
どのチップコントロール系信号とアドレス信号があり、
それぞ五人カバッファ回路゛を必要とする。Input signals for semiconductor memory include chip control signals such as chip enable signals that control the selection and non-selection states of semiconductor memory chips, and address signals.
Each requires five buffer circuits.
チップイネーブル信号が非選択（電源電圧ＶＯＯ）時チ
ップの消費電流は入力バッファ回路ばかりでなくその他
の回路においても基本的ムゼロでなければならない。When the chip enable signal is not selected (power supply voltage VOO), the current consumption of the chip must be basically zero not only in the input buffer circuit but also in other circuits.
チップイネーブル用人力バッファ回路として第３図の回
路を使用した場合、入力端子Ｆの電位が電源電圧■ＤＤ
となってもＶｏｏ Ｖｓｓ間の３つの電流パス（トラ
ンジスタＰＬＯとＮＩＯが関与する電流パス、トランジ
スタｐＨとＮｉｌが関与する電流パス、トランジスタＮ
１２とＮ１３が関与する電流パス）すべてに電流が流れ
る。アドレス用人力バッファ回路として第３図の回路を
使用した場合、チップイネーブル信号の選択、非選択に
関係なく前記３つの電流パスに電流が流れる、ただし入
力端子Ｆのアドレス電位レベルがトランジスタＮＩＯの
しきい電圧以下の場合はトランジスタＰＩＯとＮＩＯか
ら成るパスに電流は流れない、さらに入力端子Ｆのアド
レス電位次第では入力バッファ回路に続くトランジスタ
段で電流が流れる可能性が生じるという間顧点を持つ。When the circuit shown in Figure 3 is used as a chip enable manual buffer circuit, the potential of input terminal F is equal to the power supply voltage ■DD
Even so, there are three current paths between Voo and Vss (current path involving transistors PLO and NIO, current path involving transistors pH and Nil, current path involving transistor N
Current flows through all current paths (including current paths involving N12 and N13). When the circuit shown in Fig. 3 is used as an address manual buffer circuit, current flows through the three current paths regardless of whether the chip enable signal is selected or not. If the voltage is below the threshold voltage, no current will flow through the path made up of transistors PIO and NIO, and depending on the address potential of input terminal F, there is a possibility that current will flow in the transistor stage following the input buffer circuit.
本発明は、かかる問題点を解決するためになされたもの
でチップイネーブル信号非選択（電源電圧Ｖｏｏ）時に
回路電流がゼロ同時に後段回路に電流を流さない入力バ
ッファ回路を提供することにある。The present invention has been made to solve such problems, and an object of the present invention is to provide an input buffer circuit in which the circuit current is zero when the chip enable signal is not selected (power supply voltage Voo), and at the same time, no current flows to the subsequent stage circuit.
第１の電源電位と出力点との間にゲートとドレインを接
続した第１のＮチャンネル型ＭＯＳトランジスタを少な
くとも１つ以上備え、前記出力点と第２の電源電位との
間に前記第１のＮチャンネル型ＭＯＳトランジスタの持
つトランジスタ利得係数より十分低いトランジスタ利得
係数を持つ第２のＮチャンネル型ＭＯＳトランジスタを
備えたレベル回路と、
前記第１の電源電位と前記第２の電源電位との間に配置
され入力信号と前記レベル回路の出力信号を入力とした
差動型回路と、
を備え製造条件（トランジスタ利得係数、しきい値電圧
）バラツキに対し安定なロジックレベルを持つ入力バッ
ファ回路において、
ａ）前記差動型回路の構成要素で前記入力信号を受ける
手段が属する前記第１の電流経路に設けられ制御信号の
状態に対応し前記第１の電流経路を切ったり切らなかっ
たりする第１のスイッチング手段と。At least one first N-channel MOS transistor having a gate and a drain connected between a first power supply potential and an output point is provided, and the first N-channel MOS transistor is provided between the output point and a second power supply potential. a level circuit including a second N-channel MOS transistor having a transistor gain coefficient sufficiently lower than the transistor gain coefficient of the N-channel MOS transistor; and between the first power supply potential and the second power supply potential. an input buffer circuit having a logic level that is stable against variations in manufacturing conditions (transistor gain coefficient, threshold voltage), comprising: ) A first current path, which is a component of the differential circuit and is provided in the first current path to which the means for receiving the input signal belongs, and is configured to cut or not cut the first current path depending on the state of the control signal. and switching means.
ｂ）前記差動型回路の出力と前記第１の電源電位または
前記第２の電源電位間に設けられ前記制御信号の状態に
対応し前記差動型回路の出力を前記第１の電源電位また
は第２の電源電位にするプルアラ１またはプルダウン手
段と、
Ｃ）前記差動型回路の構成要素で前記レベル回路の前記
出力を受ける手段が属する前記第１の電源電位と前記第
２の電源電位間の第２の電流経路に設けられ前記制御信
号の状態に対応し前記第２の電流経路を切ったり切らな
かったりする第２のスイッチング手段と、
ｄ）前記第１、第２のＮチャンネル型ＭＯ３）ランジス
タからなるレベル回路の第３の電流経路に設けられ前記
制御信号の状態に対応し前記第３の電流経路を切ったり
切らなかったりする第３のスイッチング手段と、
ｅ）前記第２の電流経路に設けられ前記入力信号の状態
に対応し、前記第２の電流経路を切ったり切らなかった
りする第４のスイッチング手段と、ｆ）前記第３の′ｒ
４流経路に設けられ前記入力信号の状態に対応し、前記
第３の電流経路を切ったり切らなかったりする第５のス
イッチング手段と、から構成された入力バッフ７回路。b) Corresponding to the state of the control signal provided between the output of the differential type circuit and the first power supply potential or the second power supply potential, the output of the differential type circuit is set to the first power supply potential or the second power supply potential. a puller 1 or pull-down means for setting the power supply potential to a second power supply potential; and C) between the first power supply potential and the second power supply potential to which the means for receiving the output of the level circuit which is a component of the differential circuit belongs. d) a second switching means provided in a second current path of the controller and configured to turn off or not turn off the second current path depending on the state of the control signal; d) the first and second N-channel type MO3; ) a third switching means provided in a third current path of a level circuit made of a transistor and configured to turn off or not turn off the third current path in accordance with the state of the control signal; e) the second current path; a fourth switching means provided in the path and configured to turn off or not turn off the second current path depending on the state of the input signal; f) the third switching means;
and a fifth switching means provided in the four current paths and configured to turn off or not turn off the third current path in response to the state of the input signal.
入力端子の電位レベルが電源電位ＶＤＤになると、レベ
ル回路の電流経路とレベル回路の出力を受けた差動回路
の構成要素が含まれた電流経路にそれぞれ設けられたス
イッチング手段がＯＦＦとなり、各電流経路を切り回路
全電流がゼロとなる。入力信号を受けた差動回路の構成
要素が含まれた電流経路の電流はレベル回路の出力を受
けた差動回路の構成要素が含まれた電流経路の電流が前
記したようにゼロとなるため自動的にゼロとなる。When the potential level of the input terminal reaches the power supply potential VDD, the switching means provided in the current path of the level circuit and the current path including the components of the differential circuit receiving the output of the level circuit are turned OFF, and each current The path is cut and the total current in the circuit becomes zero. The current in the current path that includes the components of the differential circuit that receives the input signal is zero because the current in the current path that includes the components of the differential circuit that receives the output of the level circuit becomes zero as described above. automatically becomes zero.
制御端子に半導体メモリチップ非選択に対応した信号が
入ると、レベル回路の出力を受けた差動回路の構成要素
が含まれた電流経路とレベル回路の電流経路にそれぞれ
設けられたスイッチング手段がその状態に反応し各電流
経路を切り回路全電流がゼロとなる。入力信号を受けな
差動回路の構成要素が含まれた′ｔ＆流経路の電流は前
述したと同様な理由によりゼロとなる。When a signal corresponding to the non-selection of the semiconductor memory chip is input to the control terminal, the switching means provided respectively in the current path including the components of the differential circuit receiving the output of the level circuit and the current path of the level circuit are activated. In response to the situation, each current path is cut off and the total current in the circuit becomes zero. The current in the 't& current path, which includes the components of the differential circuit that does not receive the input signal, becomes zero for the same reason as described above.
同時に差動回路の出力と電源電圧ＶＤＤまたは接地電位
Ｖｓｓ間に設けられた１ルアツ１またはプルダウン手段
が制御信号に反応し差動回路の出力を電源電圧Ｖ０゜ま
たは接地電位ＶＳＳに固定し、入力バッファ回路以降の
トランジスタ回路に電流を流さない。At the same time, a pull-down means provided between the output of the differential circuit and the power supply voltage VDD or the ground potential Vss responds to the control signal and fixes the output of the differential circuit to the power supply voltage V0° or the ground potential VSS. Do not allow current to flow through the transistor circuits after the buffer circuit.
第１図に本発明による入力バッファ回路の実施例を示す
、Ｐｌｏ、ｐＨはＰチャンネル型トランジスタで第２図
のＰＩＯｌＰｌｌとそれぞれ同一物である、Ｎ１０、Ｎ
ｉｌ、Ｎ１２、Ｎ１３はＮチャンネル型トランジスタで
第２図のＮｌ０１Ｎｉｌ、Ｎ１２、Ｎ１３とそれぞれ同
一物である、Ｆは入力端子で第２図中のＦと対応する、
Ｇは出力端子で第２図中のＧと対応する、Ｈ，Ｉは回路
中の節点で第２図中のＨ５■とそれぞれ対応する、Ｊは
チップイネーブル系制御信号端子、Ｋは回路中の節点で
ある。FIG. 1 shows an embodiment of the input buffer circuit according to the present invention. Plo and pH are P-channel transistors, respectively, and are the same as PIOlPll in FIG. 2. N10 and N
il, N12, and N13 are N-channel transistors, which are the same as Nl01Nil, N12, and N13 in FIG. 2, respectively. F is an input terminal and corresponds to F in FIG. 2.
G is an output terminal and corresponds to G in Figure 2.H and I are nodes in the circuit and correspond to H5■ in Figure 2, respectively.J is a chip enable control signal terminal, and K is a node in the circuit. It is a node.
ＰＩ３、ＰＩ３はＰチャンネル型トランジスタ、Ｎ１６
、Ｎ１７、Ｎ１８、Ｎ１９はＮチャンネル型ｌ−ランジ
スタである。PI3, PI3 is a P-channel transistor, N16
, N17, N18, and N19 are N-channel type l-transistors.
トランジスタＮ１４、Ｎ１６、Ｎ１７、Ｎ１８、Ｎ１９
の能力は、前記式（６）を決めるトランジスタＰ１０、
Ｎ１０、ｐＨ、Ｎ１１Ｎ１２、Ｎ１３からなる系にエイ
キョウを与えない程度の大きさに設定される。Transistors N14, N16, N17, N18, N19
The ability of the transistor P10, which determines the above equation (6), is
The size is set to such an extent that it does not give any effect on the system consisting of N10, pH, N11, N12, and N13.
チップイネーブル用入力バッファ回路として本発明の回
路を使用した場合、チップイネーブル系ＩＩＪ＃信号端
子の電位は電源電圧ｖ０゜に固定とする、入力端子Ｆに
電源電圧ＶＤＯが入いると、１−ランジスタＰ１３とＮ
１５から成るインバータ回路の出力Ｋが接地電位ｖ、、
となりトランジスタＮ１７とＮ１９はＯＦＦ状態となる
。トランジスタｐＨ、Ｎ１１、Ｎ１６、Ｎ１７とトラン
ジスタＮ１２、Ｎ１３、Ｎ１８、Ｎ１９と流れる電流は
なくなる。When the circuit of the present invention is used as a chip enable input buffer circuit, the potential of the chip enable system IIJ# signal terminal is fixed to the power supply voltage v0°.When the power supply voltage VDO is applied to the input terminal F, the 1-transistor P13 and N
The output K of the inverter circuit consisting of 15 is at the ground potential v,
Therefore, transistors N17 and N19 are turned off. No current flows through transistors pH, N11, N16, N17 and transistors N12, N13, N18, N19.
トランジスタＰＩＯ１Ｎ１４、ＮＩＯを流れる電流はト
ランジスタＰｉ １、Ｎｌ １、Ｎ１６、Ｎ１７を流れ
る電流がゼロであるため自動的に流れない。The current flowing through the transistors PIO1N14 and NIO does not flow automatically because the current flowing through the transistors Pi 1, Nl 1, N16, and N17 is zero.
トランジスタＰ１３とＮ１５からなるインバータ回路の
ロジックレベルはＰ１３能力）Ｎ１５能力としできるだ
け電源電圧ＶＤＤ近傍に設定する。The logic level of the inverter circuit consisting of transistors P13 and N15 is set as close to the power supply voltage VDD as possible, with P13 capability and N15 capability.
インバータ回路のロジックレベルは前記式（６）のロジ
ックレベルより低いと回路全体のロジックレベルがイン
バータ検出回路のロジックレベルになってしまうため前
記式（６）のロジックレベルより基本的に上であればよ
い。If the logic level of the inverter circuit is lower than the logic level of the above formula (6), the logic level of the entire circuit will become the logic level of the inverter detection circuit, so if it is basically higher than the logic level of the above formula (6). good.
入力信号Ｆの高い方の電位レベルが前記式（６）のロジ
ックレベルとインバータ検出回路のロジックレベルの間
にある時の入力信号Ｆに対する出力Ｇの動きはトランジ
スタＮＩＯだけの動作によって決まるため短時間である
。これに対し、入力信号Ｆの高い方の電位レベルがイン
バータ回路のロジックレベル以上にある時の入力信号Ｆ
に対する出力Ｇの動きはインバータ回路系が動作に絡む
ため時間を要する、特に入力信号Ｆが電源電圧Ｖ ｏ。When the higher potential level of the input signal F is between the logic level of equation (6) and the logic level of the inverter detection circuit, the movement of the output G with respect to the input signal F is determined by the operation of the transistor NIO only, so it takes a short time. It is. On the other hand, when the higher potential level of the input signal F is higher than the logic level of the inverter circuit, the input signal F
The movement of the output G relative to the input signal F takes time because the inverter circuit system is involved in the operation, especially when the input signal F is the power supply voltage Vo.
から接地電位ｖＩ側に変化した時がもつとも遅くれる形
となる。The time when the voltage changes from the voltage to the ground potential vI side is delayed.
入力信号が電源電圧ＶＤ、から接地電位ＶＳＳ側に変化
した時できるだけ早くインバータ回路を動作させ、出力
Ｇが電源電圧ＶＤＤに立ち上がる時間を早める所にイン
バータ回路のロジックレベルを電源電圧ｖＤＤ近傍にす
る意図がある。The intention is to operate the inverter circuit as quickly as possible when the input signal changes from the power supply voltage VD to the ground potential VSS side, and to set the logic level of the inverter circuit near the power supply voltage VDD so that the time for the output G to rise to the power supply voltage VDD is accelerated. There is.
アドレス信号の入力バッファ回路として第１図に示す本
発明の回路を使用したとする、制ａｌｌ端子Ｊにはチッ
プイネーブル信号に連動した信号が入りチップイネーブ
ル信号非選択時のその信号のレベルを接地電位ＶＳＳと
する。Assuming that the circuit of the present invention shown in FIG. 1 is used as an input buffer circuit for the address signal, a signal linked to the chip enable signal is input to the control all terminal J, and the level of that signal when the chip enable signal is not selected is grounded. The potential is set to VSS.
制御端子Ｊに接地電位■□が入いると、トランジスタＮ
１６、Ｎ１８がＯＦＦ状態となり、トランジスタｐＨ、
Ｎｉｌ、Ｎ１６、Ｎ １７からなる経路とトランジスタ
Ｎ１２、Ｎ１３、Ｎ１８、Ｎ１９からなる経路に電流は
流れなくなる、トランジスタＰＩＯ１ＮＩＯからなる経
路の電流はトランジスタＰｉ １、Ｎｌ １、Ｎ１６、
Ｎ１７からなる経路の電流がゼロとなるため自動的にゼ
ロとなる。When the ground potential ■□ is applied to the control terminal J, the transistor N
16, N18 becomes OFF state, transistor pH,
Current no longer flows in the path consisting of Nil, N16, N17 and the path consisting of transistors N12, N13, N18, N19. The current in the path consisting of transistors PIO1NIO flows through transistors Pi 1, Nl 1, N16,
Since the current in the path consisting of N17 becomes zero, it automatically becomes zero.
同時に、差動回路の出力Ｇと接地電位Ｖ。間の電流経路
がトランジスタＮ１４によって切られ、差動回路の出力
ＧがトランジスタＰ１２のプルアップ手段によって電源
電圧ＶＤｏにあげられ、次段トランジスタ回路の電流を
たつ。At the same time, the output G and ground potential V of the differential circuit. The current path between them is cut off by the transistor N14, and the output G of the differential circuit is raised to the power supply voltage VDo by the pull-up means of the transistor P12, and the current flows through the next stage transistor circuit.
この場合、トランジスタＰ１３とＰＩ３がら成るインバ
ータ回路の入力はＦに接続したままでもよいし、切り離
し接地電位■ｓ、Ｉに固定しておいてもよい。In this case, the input of the inverter circuit consisting of the transistors P13 and PI3 may remain connected to F, or may be separated and fixed to the ground potential ■s, I.
第１図においてはスイッチング手段であるトランジスタ
Ｎ１６、Ｎ１７がトランジスタＮｉｌのソースと接地電
位７１間に、トランジスタＮ１８、Ｎ１９がトランジス
タＮ１３のソースと接地電位間に入っている。トランジ
スタＮ１６、Ｎ１７がトランジスタｐＨのゲート、ドレ
インとトランジスタＮｉｌのドレイン間に、トランジス
タＮ１８、Ｎ１９がトランジスタＮ１２のソースとトラ
ンジスタＮ１３のドレイン間にそれぞれ設けてもよい。In FIG. 1, transistors N16 and N17 serving as switching means are placed between the source of transistor Nil and ground potential 71, and transistors N18 and N19 are placed between the source of transistor N13 and ground potential. Transistors N16 and N17 may be provided between the gate and drain of transistor pH and the drain of transistor Nil, and transistors N18 and N19 may be provided between the source of transistor N12 and the drain of transistor N13, respectively.
またトランジスタＮ１８、Ｎ１９をＮチャンネル型トラ
ンジスタがらＰチャンネル型トランジスタに変えて、ト
ランジスタＮ１２のゲート、ドレイン（トランジスタＮ
１３のゲート点でもある）と電源電圧Ｖｐｐ間に置いて
もよい、ただしトランジスタＮ１８に対応する物は制御
信号Ｊをインバータ回路で反転した信号をゲートに受け
、トランジスタＮ１９に対応する物は入力信号Ｆを直接
ゲートに受ける形となる。Also, transistors N18 and N19 are changed from N-channel transistors to P-channel transistors, and the gate and drain of transistor N12 (transistor N
13) and the power supply voltage Vpp, however, the transistor corresponding to transistor N18 receives at its gate a signal obtained by inverting the control signal J by an inverter circuit, and the transistor corresponding to transistor N19 receives the input signal. F is directly received by the gate.
第２図に本発明による入力バッファ回路のもう１つの実
施例を示す、基本的には第１図に示す実施例と同じであ
る、唯−異なるのは第１図のＰチャンネル型トランジス
タＰ１２とＮチャンネル型トランジスタＮ１４がなくな
り、新たにＰチャンネル型トランジスタがトランジスタ
ＰＩＯのドレインと出力Ｇの間に、Ｎチャンネル型トラ
ンジスタＮ２０が出力Ｇと接地電位の間にそれぞれ設け
られ、ゲート信号は制御信号ＪをＰチャンネル型トラン
ジスタＰ１５とＮチャンネル型トランジスタＮ２１から
なるインバータ回路で反転した信号を受けている点であ
る。動作上からは第１図の実施例ではチップイネーブル
信号が非選択という信号が制御端子Ｊに入った時差動型
回路の出力Ｇが電源電位ＶＯＯに上がるのに対し、第３
図の実施例はトランジスタＮ２０が動作し出力Ｇが接地
電位になる。FIG. 2 shows another embodiment of the input buffer circuit according to the present invention, which is basically the same as the embodiment shown in FIG. 1, the only difference being the P-channel transistor P12 of FIG. The N-channel transistor N14 is removed, a new P-channel transistor is provided between the drain of the transistor PIO and the output G, and an N-channel transistor N20 is provided between the output G and the ground potential, and the gate signal is the control signal J. It receives a signal inverted by an inverter circuit consisting of a P-channel transistor P15 and an N-channel transistor N21. From an operational point of view, in the embodiment of FIG.
In the illustrated embodiment, the transistor N20 operates and the output G becomes the ground potential.
本発明によれば、入力信号が電源電圧ＶＤＤになると、
各電流経路を切る手段と、制御信号を受けその信号状態
に応じて各電流経路を切る手段と、前記制御信号を受け
その信号状態に応じて出力点を電源電位ＶＯＯまたは接
地電位■□にする手段を設けることにより、チップイネ
ーブル信号非選択時に回路電流がゼロ、同時に後段回路
に電流を流さない入力バッファ回路が可能となる。According to the present invention, when the input signal becomes the power supply voltage VDD,
means for cutting off each current path; means for receiving a control signal and cutting off each current path according to the signal state; and means for receiving the control signal and setting the output point to power supply potential VOO or ground potential ■□ according to the signal state. By providing the means, it is possible to provide an input buffer circuit in which the circuit current is zero when the chip enable signal is not selected, and at the same time, no current flows to the subsequent stage circuit.
第１図、第２図は本発明による実施例を示す図である。
第３図は従来の入力バッファ回路図である０図において
、
Ｎ１０、Ｎｉｌ、Ｎ１２、Ｎ１３、Ｎ１４、Ｎ１５、Ｎ
１６、Ｎ１７、Ｎ１８、Ｎ１９、Ｎ２０、Ｎ２１
・・・・Ｎチャンネル型トランジスタ
Ｐ１０、Ｐｌｌ、ＰＩ３、ＰＩ３、ＰＩ３、ＰＩ３・・
・・Ｐチャンネル型トランジスタＦ・・・・・・入力信
号端子
Ｇ・・・・・・出力信号端子
Ｊ・・・・・・制御信号端子
Ｈ，Ｉ、Ｋ・・回路中の各節点
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉（他１名）第′２−ＢFIG. 1 and FIG. 2 are diagrams showing an embodiment according to the present invention. FIG. 3 is a conventional input buffer circuit diagram, in which N10, Nil, N12, N13, N14, N15, N
16, N17, N18, N19, N20, N21... N-channel transistor P10, Pll, PI3, PI3, PI3, PI3...
...P-channel transistor F...Input signal terminal G...Output signal terminal J...Control signal terminal H, I, K...Apply for each node or more in the circuit Person Seiko Epson Co., Ltd. Representative Patent Attorney Masaharu Kamiyanagi (and 1 other person) No. 2-B
Claims (1)
接続した第１のＮチャンネル型ＭＯＳトランジスタを少
なくとも１つ以上備え、前記出力点と第２の電源電位と
の間に前記第１のＮチャンネル型ＭＯＳトランジスタの
持つトランジスタ利得係数より十分低いトランジスタ利
得係数を持つ第２のＮチャンネル型ＭＯＳトランジスタ
を備えたレベル回路と、 前記第１の電源電位と前記第２の電源電位との間に配置
され入力信号と前記レベル回路の出力信号を入力とした
差動型回路と、 を備え製造条件（トランジスタ利得係数、しきい値電圧
）バラツキに対し安定なロジックレベルを持つ入力バッ
ファ回路において、 ａ）前記差動型回路の構成要素で前記入力信号を受ける
手段が属する前記第１の電源電位と前記第２の電源電位
間の第１の電流経路に設けられ制御信号の状態に対応し
前記第１の電流経路を切ったり切らなかつたりする第１
のスイッチング手段と、 ｂ）前記差動型回路の出力と前記第１の電源電位または
前記第２の電源電位間に設けられ前記制御信号の状態に
対応し前記差動型回路の出力を前記第１の電源電位また
は第２の電源電位にするプルアップまたはプルダウン手
段と、 ｃ）前記差動型回路の構成要素で前記レベル回路の前記
出力を受ける手段が属する前記第１の電源電位と前記第
２の電源電位間の第２の電流経路に設けられ前記制御信
号の状態に対応し前記第２の電流経路を切ったり切らな
かったりする第２のスイッチング手段と、 ｄ）前記第１、第２のＮチャンネル型ＭＯＳトランジス
タからなるレベル回路の第３の電流経路に設けられ前記
制御信号の状態に対応し前記第３の電流経路を切ったり
切らなかったりする第３のスイッチング手段と、 ｅ）前記第２の電流経路に設けられ前記入力信号の状態
に対応し前記第２の電流経路を切ったり切らなかつたり
する第４のスイッチング手段と、ｆ）前記第３の電流経
路に設けられ前記入力信号の状態に対応し前記第３の電
流経路を切ったり切らなかつたりする第５のスイッチン
グ手段とを具備したことを特徴とする入力バッファ回路
。[Scope of Claims] At least one first N-channel MOS transistor having a gate and a drain connected between a first power supply potential and an output point, and a first N-channel MOS transistor having a gate and a drain connected between the output point and a second power supply potential; a level circuit comprising a second N-channel MOS transistor having a transistor gain coefficient sufficiently lower than the transistor gain coefficient of the first N-channel MOS transistor between the first power supply potential and the second power supply potential; A differential circuit that is placed between the power supply potential and inputs the input signal and the output signal of the level circuit, and has a logic level that is stable against variations in manufacturing conditions (transistor gain coefficient, threshold voltage). In the input buffer circuit, a) a component of the differential circuit that is provided in a first current path between the first power supply potential and the second power supply potential to which the means for receiving the input signal belongs, and that receives the control signal; a first current path that cuts or does not cut the first current path depending on the state;
b) a switching means provided between the output of the differential circuit and the first power supply potential or the second power supply potential to switch the output of the differential circuit to the second power supply in response to a state of the control signal; c) pull-up or pull-down means for setting the power supply potential to one power supply potential or a second power supply potential; d) a second switching means provided on a second current path between the two power supply potentials and for turning off or not cutting off the second current path depending on the state of the control signal; d) the first and second switching means; e) a third switching means provided in a third current path of a level circuit consisting of an N-channel MOS transistor and configured to turn off or not turn off the third current path in response to the state of the control signal; f) fourth switching means provided in the second current path and configured to turn off or not the second current path depending on the state of the input signal; and f) fourth switching means provided in the third current path to switch the input signal and a fifth switching means for cutting off or not cutting off the third current path depending on the state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63094137A JPH01265610A (en) | 1988-04-15 | 1988-04-15 | Input buffer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63094137A JPH01265610A (en) | 1988-04-15 | 1988-04-15 | Input buffer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01265610A true JPH01265610A (en) | 1989-10-23 |
Family
ID=14102004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63094137A Pending JPH01265610A (en) | 1988-04-15 | 1988-04-15 | Input buffer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01265610A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5761779A (en) * | 1989-12-07 | 1998-06-09 | Nippon Steel Corporation | Method of producing fine metal spheres of uniform size |
-
1988
- 1988-04-15 JP JP63094137A patent/JPH01265610A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5761779A (en) * | 1989-12-07 | 1998-06-09 | Nippon Steel Corporation | Method of producing fine metal spheres of uniform size |
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