JPH01263094A - Ic card - Google Patents
Ic cardInfo
- Publication number
- JPH01263094A JPH01263094A JP63094244A JP9424488A JPH01263094A JP H01263094 A JPH01263094 A JP H01263094A JP 63094244 A JP63094244 A JP 63094244A JP 9424488 A JP9424488 A JP 9424488A JP H01263094 A JPH01263094 A JP H01263094A
- Authority
- JP
- Japan
- Prior art keywords
- module
- chip
- terminals
- external communication
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims abstract description 64
- 238000004891 communication Methods 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000007689 inspection Methods 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 5
- 239000003566 sealing material Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 19
- 239000011162 core material Substances 0.000 description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Credit Cards Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野Ｊ
本発明は、ＩＣカードに関し、詳しくは検査用端子を備
えたＩＣモジュールを備えたＩＣカードに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J] The present invention relates to an IC card, and more particularly to an IC card equipped with an IC module equipped with a test terminal.
［従来の技術］
集積回路チップをカード状のコア内に設けたＩＣカード
として、外表面に外部通信用端子を設は演算素子や記憶
素子等か装填されたＩＣモジュールをＩＣカードの強度
部材であるコア材にはめ込みＩＣカードを形成するいわ
ゆるはめ込み型と、外部接続用端子がプリントされたプ
リンＩ・配線基板にＩＣモジュールを載置しこのプリン
ト配線基板をはさみ込みＩＣカードを形成するラミネー
ト型が知られている。[Prior Art] An IC card has an integrated circuit chip installed in a card-shaped core, and an IC module loaded with an arithmetic element, a memory element, etc., which has external communication terminals on the outer surface, is used as a strength member of the IC card. There are two types: the so-called inset type, which is inserted into a certain core material to form an IC card, and the laminated type, in which an IC module is placed on a printed wiring board on which external connection terminals are printed, and this printed wiring board is sandwiched to form an IC card. Are known.
はめ込み型の公知技術例として、特開昭６０−５８９号
公報、特開昭６１−２９７１９１号公報、特開昭５８−
１３８０５７号公報があり、ラミネート型の公知技術と
しては特公昭６１−３０３１５号公報、特開昭４７−４
５１３４号公報がある。Examples of known techniques of the inset type include JP-A-60-589, JP-A-61-297191, and JP-A-58-
There is Japanese Patent Publication No. 138057, and known technologies for laminate type include Japanese Patent Publication No. 61-30315 and Japanese Unexamined Patent Application Publication No. 47-4
There is a publication No. 5134.
上述のようなＩＣカードに使用されるＩＣモジュールは
、ＩＣモジュールが製造された時点で健全性が検査され
、健全なものがＩＣカードに装填される。The soundness of the IC modules used in the above-mentioned IC cards is inspected at the time they are manufactured, and those that are sound are loaded into the IC cards.
［発明が解決しようとする課題］
ところか従来のＩＣモジュールの本体には８つの外部通
信用端子しか設けられておらず、ＩＣモジュール内のＩ
Ｃチップに含まれる要素を検査するには、これらの外部
通信用端子を利用し行なわれている。しかし、外部通信
用端子を利用しＩＣチップ内の全ての要素を検査するに
は外部通信用端子が萌紀要素の総てとは接続されていな
いことより困難であるとともに、ＩＣモジュールｌｐｌ
当りの検査時間が非常に長くなる。したがってＩＣモジ
ュールの生産性か悪く、生産コストが」二昇するという
問題点があった。[Problem to be solved by the invention] However, the main body of a conventional IC module is only provided with eight external communication terminals, and the I/O inside the IC module is
These external communication terminals are used to inspect the elements included in the C chip. However, it is difficult to inspect all the elements in the IC chip using the external communication terminal because the external communication terminal is not connected to all the Moeki elements, and the IC module lpl
The time required for each inspection becomes extremely long. Therefore, there was a problem in that the productivity of the IC module was poor and the production cost increased by 20%.
本発明は、上述した問題点を解決するためになされたも
ので、ＩＣチップ内の全ての要素を短時間で検査ができ
るＩＣモジュールと、面記ＩＣモジュールを使用したＩ
Ｃカードを提供することを目的とする。The present invention was made to solve the above-mentioned problems, and includes an IC module that can inspect all the elements in an IC chip in a short time, and an IC module that uses a surface-mounted IC module.
The purpose is to provide C cards.
［課題を解決するための手段］
第１の発明のＩＣモジュールは、装填されるＩＣチップ
と接続する複数の外部通信用端子と、ｌＣチップの健全
性を検査するため前記ＩＣチップと接続する複数の検査
用端子とを外表面に設けたことを特徴とする。[Means for Solving the Problems] The IC module of the first invention includes a plurality of external communication terminals connected to a loaded IC chip, and a plurality of external communication terminals connected to the IC chip for inspecting the health of the IC chip. It is characterized by having a test terminal provided on the outer surface.
上記の構成によれば、検査用端子はＩＣモジュール内の
要素の健全性を検査するために使用され、外部通信用端
子は検査用端子として用いられるとともに外部との通信
用に使用される。According to the above configuration, the test terminal is used to test the health of elements within the IC module, and the external communication terminal is used both as a test terminal and for communication with the outside.
第２の発明のＩＣカードは面記ＩＣモジュールに設けら
れる検査用端子は被覆され外部通信用端子のみ外部デー
タ処理装置と接続できるように露出したＩＣモジュール
を備えたことを特徴とする。The IC card of the second aspect of the invention is characterized in that the test terminal provided on the surface IC module is covered, and only the external communication terminal is exposed so that it can be connected to an external data processing device.
さらに第３の発明のＩＣカードは検査用端子と外部通信
用端子とを有ケるＩＣモジュールを載置可能で、ＩＣモ
ジュールの外部通信用端子とのみ接続する外部接続用端
子が形成されたプリント基板を備えたことを特徴とする
。Furthermore, the IC card of the third invention is capable of mounting an IC module having an inspection terminal and an external communication terminal, and has a printed circuit board formed with an external connection terminal that connects only to the external communication terminal of the IC module. It is characterized by having a substrate.
上記の構成によれば、検査用端子は、ＩＣモジュールの
健全性を検査した後被覆されたり、外部接続用端子と結
線されないので、外部の端子と接続することはない。外
部通信用端子は、ＩＣカード外表面に露出するので外部
の端子と接続することができる。According to the above configuration, the test terminals are not coated after the health of the IC module is tested and are not connected to external connection terminals, so they are not connected to external terminals. Since the external communication terminal is exposed on the outer surface of the IC card, it can be connected to an external terminal.
さらに第４の発明のＩＣカードの製造方法は以下の特徴
を有する。Furthermore, the method for manufacturing an IC card according to the fourth invention has the following features.
外部データ処理装置と接続される複数の外部通信用端子
と、ＩＣチップの健全性を検査するＩＣチップと接続す
る複数の検査用端子とを備えたＩＣモジュールは、検査
用端子を利用してＩＣチップの健全性が検査される。検
査後、検査用端子は被覆され外部通信用端子のみを外表
面に露出して製造することを特徴とする。An IC module equipped with a plurality of external communication terminals connected to an external data processing device and a plurality of test terminals connected to an IC chip that tests the health of the IC chip uses the test terminals to test the IC chip. The health of the chip is inspected. After the test, the test terminal is covered and only the external communication terminal is exposed on the outer surface.
さらに本発明のＩＣカードの製造方法は以下の特徴を有
する。Furthermore, the method for manufacturing an IC card of the present invention has the following features.
外部データ処理装置と接続される複数の外部通信用端子
と、ＩＣチップの健全性を検査するＩＣチップと接続す
る複数の検査用端子とを備えたＩＣモジュールは、検査
用端子を利用してＩＣチップの健全性が検査される。検
査後ＩＣモジュールの外部通信用端子のみが外部接続用
端子と結線され製造されることを特徴とする。An IC module equipped with a plurality of external communication terminals connected to an external data processing device and a plurality of test terminals connected to an IC chip that tests the health of the IC chip uses the test terminals to test the IC chip. The health of the chip is inspected. After inspection, only the external communication terminal of the IC module is connected to the external connection terminal during manufacture.
上記の方法によれば、ＩＣカードは検査後ＩＣカード内
に装填される。さらにＩＣモジュールの外部通信用端子
のみがＩＣカードの外表面に露出するようにＩＣカード
は製造される。According to the above method, the IC card is loaded into the IC card after being inspected. Furthermore, the IC card is manufactured so that only the external communication terminal of the IC module is exposed on the outer surface of the IC card.
［実施例］
ＩＣモジュール２は第１図に示すように、中央演算処理
素子３（以下ＣＰＵと略す）と記憶素子４の２つのＩＣ
チップより成る２チツプタイプのものと、第２図に示す
ようにＣＰＵ３．記憶素子４等を含むマイクロプロセッ
サ５の１つのＩＣチップよりなるｌチップタイプのもの
がある。どちらのタイプにおいても本発明のＩＣモジュ
ール２の外表面２ａ上には、ＩＣモジュール２内のＩＣ
チップに含まれる要素を検査するのに用いられる検査用
端子７と、ＩＣモジュール２と外部データ処理装置とを
接続する外部通信用端子６とが電気的に接触可能に露出
して設けられる。以下に検査用端子７を形成する具体例
を説明する。[Example] As shown in FIG.
A two-chip type consisting of a chip, and a CPU3. There is an l-chip type device consisting of one IC chip of a microprocessor 5 including a memory element 4 and the like. In either type, an IC inside the IC module 2 is provided on the outer surface 2a of the IC module 2 of the present invention.
Test terminals 7 used to test elements included in the chip and external communication terminals 6 that connect the IC module 2 and an external data processing device are exposed and provided so as to be electrically contactable. A specific example of forming the test terminal 7 will be described below.
ＩＣモジュール２は、公知の方法である、テープキャリ
ア方式、フリップチップ方式、ワイヤボンディング方式
にて形成される。例えば第３図は、テープキャリア方式
にて形成された本発明のＩＣモジュール２の一実施例を
示している。又、第４図は第３図に示すＩＣモジュール
２の平面図である。The IC module 2 is formed by a known method such as a tape carrier method, a flip chip method, or a wire bonding method. For example, FIG. 3 shows an embodiment of the IC module 2 of the present invention formed using a tape carrier method. Further, FIG. 4 is a plan view of the IC module 2 shown in FIG. 3.
ポリイミド等にてなるテープキャリア８の外表面上には
、８個の外部通信用端子６と複数の検査用端子７とが露
出して形成される。尚、これらの外部通信用端子６と検
査用端子７はテープキャリア８の中央部の方形状の空間
９の周囲の４辺方向にそれぞれ延在している。又、外部
通信用端子６と検査用端子７とは帯状を有する導電材よ
りなり各々電気的に絶縁して形成される。前記端子６及
び７と、ＩＣチップＩＯの表面上に形成されるパッドと
は、金等にてなるバンブ１１にて接続される。On the outer surface of the tape carrier 8 made of polyimide or the like, eight external communication terminals 6 and a plurality of test terminals 7 are formed to be exposed. Note that these external communication terminals 6 and inspection terminals 7 extend in the four sides of the rectangular space 9 in the center of the tape carrier 8, respectively. Further, the external communication terminal 6 and the inspection terminal 7 are made of a conductive material having a band shape and are electrically insulated from each other. The terminals 6 and 7 and pads formed on the surface of the IC chip IO are connected by bumps 11 made of gold or the like.
バンブ１１は封止材１４にて覆われる。さらにテープキ
ャリア８．ＩＣチップｌＯ等は、樹脂等にてなる絶縁部
２０で覆われ、密閉される。尚、検査用端子７、外部通
信用端子６は露出した状態のままである。The bump 11 is covered with a sealant 14. Furthermore, tape carrier 8. The IC chip IO and the like are covered and sealed with an insulating part 20 made of resin or the like. Note that the test terminal 7 and the external communication terminal 6 remain exposed.
第５図は、フリップチップ方式にて形成された本発明の
ＩＣモジュール２の一実施例を示す。基板Ｉ２上に前述
と同様に露出して形成された外部通信用端子６及び検査
用端子７の表面上には前記バンブ１１にてＩＣチップ１
０が接続される。バンブ１１は、封止材１４にて覆われ
る。さらにＩＣチップ１０．基板１２等は、樹脂等にて
なる絶縁部２０で覆われ、密閉される。尚、検査用端子
７、外部通信用端子６は露出した状態のままである。FIG. 5 shows an embodiment of the IC module 2 of the present invention formed by a flip-chip method. The IC chip 1 is placed on the surface of the external communication terminal 6 and the inspection terminal 7, which are exposed and formed on the substrate I2 in the same manner as described above, by the bump 11.
0 is connected. The bump 11 is covered with a sealant 14. Furthermore, IC chip 10. The substrate 12 and the like are covered and sealed with an insulating part 20 made of resin or the like. Note that the test terminal 7 and the external communication terminal 6 remain exposed.
第６図は、ワイヤボンディング方式にて形成された本発
明のＩＣモジュール２の一実施例を示す。FIG. 6 shows an embodiment of the IC module 2 of the present invention formed by wire bonding.
基板１２上に前述と同様に露出して形成された外部通信
用端子６及び検査用端子７の表面と、基板１２の外表面
に形成される空間９に載置されるＩＣチップＩＯ上のパ
ッドは金等にてなる細い接続ワイヤ１３にて接続される
。接続ワイヤ１３及びＩＣチップｌＯは封止材１４にて
覆われる。さらに基板１２．封止材１４等は、樹脂等に
てなる絶縁部２０で覆われ、密閉されろ。尚、検査用端
子７、外部通信用端子６は露出した状態のままであ以上
のようにラミネート型のＩＣカードに使用するＩＣモジ
ュール２において、外部通信用端子６と検査用端子７は
同一平面上に形成される。The surfaces of the external communication terminals 6 and inspection terminals 7 formed exposed on the substrate 12 in the same manner as described above, and the pads on the IC chip IO placed in the spaces 9 formed on the outer surface of the substrate 12. are connected by a thin connection wire 13 made of gold or the like. The connection wire 13 and the IC chip IO are covered with a sealing material 14. Furthermore, the substrate 12. The sealing material 14 and the like are covered with an insulating part 20 made of resin or the like and sealed. Note that the test terminals 7 and the external communication terminals 6 remain exposed, and as described above, in the IC module 2 used for the laminated IC card, the external communication terminals 6 and the test terminals 7 are on the same plane. formed on top.
はめ込み型のＩＣカードに使用するＩＣモジュール２に
ついても、ラミネート型の場合と同様に公知の方法であ
るフリップチップ方式、ワイヤボンディング方式にてＩ
Ｃモジュール２は形成される。The IC module 2 used in the built-in type IC card is also manufactured using the flip-chip method and wire bonding method, which are well-known methods, as in the case of the laminated type.
C module 2 is formed.
第７図は、フリップチップ方式にて形成された本発明の
ＩＣモジュール２の一実施例を示す。平面形状が方形状
である基板１２の上表面１２ａの中央部には方形状の空
間９が形成される。帯状で例えば８本以上の検査用端子
７のみが空間９の周囲四辺方向にそれぞれ延在する。尚
、各検査用端子７は電気的に絶縁されている。空間９上
にＩＣチップ１０を設置し、各検査用端子７と、ＩＣチ
ップのパッドは、バンブ１１を介して接続される。FIG. 7 shows an embodiment of the IC module 2 of the present invention formed by the flip-chip method. A rectangular space 9 is formed in the center of the upper surface 12a of the substrate 12, which has a rectangular planar shape. Only the strip-shaped test terminals 7, for example eight or more, extend in the four sides of the space 9, respectively. Note that each test terminal 7 is electrically insulated. An IC chip 10 is installed in the space 9, and each test terminal 7 and the pad of the IC chip are connected via bumps 11.
又、基板１２の下表面１２ｂには例えば１列に４個ずつ
２列にわたり合計８個の外部通信用端子６か形成される
。外部通信用端子６の平面形状は検査用端子７と同じ方
形状である。さらに、上表面１２ａに形成された検査用
端子７の内、ＩＣチップｌｌ円内ＣＰＵのパッドに接続
する８ｆ１．！ｉＩの検査用端子７と、下表面１２ｂに
形成された８個の外部通信用端子６とは基板【２の上表
面１２ａから下表面１２ｂ方向へ基板１２を貫通する導
電材にてなるビン１５を介し接続される。さらに■Ｃチ
ップ１０．基板１２等は、樹脂にてなる絶縁部２０で覆
われ密閉される。尚、検査用端子７、外部通信用端子６
は露出し・た状態のままである。Further, on the lower surface 12b of the substrate 12, a total of eight external communication terminals 6 are formed, for example, in two rows, four in each row. The planar shape of the external communication terminal 6 is the same as the test terminal 7, which is a rectangular shape. Further, among the test terminals 7 formed on the upper surface 12a, 8f1. ! The inspection terminal 7 of iI and the eight external communication terminals 6 formed on the lower surface 12b are connected to a via 15 made of a conductive material that penetrates the substrate 12 from the upper surface 12a of the substrate 2 in the direction of the lower surface 12b. connected via. Furthermore ■C chip 10. The substrate 12 and the like are covered and sealed with an insulating section 20 made of resin. In addition, the inspection terminal 7 and the external communication terminal 6
remains exposed.
第８図は、ワイヤホンディング方式にて形成された本発
明のＩＣモジュール２の一実施例を示す。FIG. 8 shows an embodiment of the IC module 2 of the present invention formed by the wire bonding method.
例えばガラスエポキシにてなる方形状の平面形状と適宜
な厚さを有する基板１６は、上表面１６ａの中央部に３
段の段差を形成するように平面形状が各々方形状で、順
次平面面積が小さくなる開口１６ｃ、 ｌ ６ｄ、ｌ
６ｅを存する。最下段である開口１６ｅの底面１６ｒの
中央部にはＩＣチップＩＯが接着される。開口１６ｅよ
り上表面１６ａ側の開口１６ｄの底面１６ｇから最上段
である開口１６ｃの底面１６ｈには開口１６ｃ、１６ｄ
にて形成される段差に一致して屈曲延在する検査用端子
７が形成される。尚、これらの検査用端子７は各々電気
的に絶縁されている。又、形成された検査用端子７の１
段目の上表面７ａは、基板１６の上表面１６ａと同一面
で露出して設けられる。これらの検査用端子７の２段目
の上表面７ｂとＩＣチップｌＯのパッドとは接続ワイヤ
１３にて接続される。又、下表面１６ｂには方形状の平
面形状にてなる１列に４個ずつ２列に並んだ外部通信用
端子６か、外表面を基板１６の下表面＋６ｂと同一面と
し基板１６の下表面１６ｂと平行して基板Ｉ６内に形成
される。尚、上述のように形成された外部通信用端子６
は、下表面＋６ｂに露出している。さらに検査用端子７
の内ＩＣチップ１０内のＣＰＵに接続する８つの検査用
端子７と、下表面１６ｂに形成する８つの外部通信用端
子６は、開口１６ｄの底面１６ｇより基板ｉ６の下表面
１６ｂ方向へ基板１６を貫通する導電材にてなるビン１
５を介して接続される。For example, the substrate 16 is made of glass epoxy and has a rectangular planar shape and an appropriate thickness.
Openings 16c, l, 6d, l each have a rectangular planar shape so as to form a step difference, and the planar area gradually decreases.
6e exists. An IC chip IO is bonded to the center of the bottom surface 16r of the opening 16e at the bottom. From the bottom surface 16g of the opening 16d on the upper surface 16a side of the opening 16e to the bottom surface 16h of the opening 16c at the top, there are openings 16c, 16d.
Test terminals 7 are formed to extend in a curved manner in accordance with the step formed in the step. Note that each of these test terminals 7 is electrically insulated. In addition, 1 of the formed test terminals 7
The upper surface 7a of the step is provided so as to be exposed on the same plane as the upper surface 16a of the substrate 16. The upper surface 7b of the second stage of these test terminals 7 and the pad of the IC chip IO are connected by a connecting wire 13. Further, on the lower surface 16b, there are external communication terminals 6 having a rectangular planar shape and arranged in two rows of four terminals per row, or there are terminals 6 for external communication arranged in two rows with four terminals in each row, or there are terminals 6 for external communication arranged on the lower surface of the substrate 16 with the outer surface flush with the lower surface +6b of the substrate 16. It is formed in substrate I6 parallel to surface 16b. Note that the external communication terminal 6 formed as described above
is exposed on the lower surface +6b. Furthermore, the inspection terminal 7
Eight test terminals 7 connected to the CPU in the IC chip 10 and eight external communication terminals 6 formed on the lower surface 16b are connected to the substrate 16 from the bottom surface 16g of the opening 16d toward the lower surface 16b of the substrate i6. A bottle 1 made of a conductive material that penetrates the
5.
さらに開口１６ｃ、 Ｉ ６ｄ、 １６ｅには、外表面
を基板１６の上表面１６ａと同じくして封止材１４が注
入される。Furthermore, the sealing material 14 is injected into the openings 16c, I6d, and 16e so that the outer surface thereof is the same as the upper surface 16a of the substrate 16.
以上のように形成されるラミネート型及びはめ込み型の
ＩＣカードに使用する［Ｃモジュール２は、例えば第９
図（ｃ）に示すように平面形状か方形状の平板よりなる
絶縁部２０の４辺より検査用端子７を突出させた形状で
ある。このような絶縁部２０を含むＩＣモジコール２は
、第９図（ａ）又は（ｂ）に示すように絶縁部２０より
大きい方形状の平面形状をなす絶縁体よりなる検査用端
子保護板２■上の中央部に載置されてらよい。又、第１
θ図に示すようにＩＣモジュール２は、外部通信用端子
６と検査用端子７とを同一方向に形成した乙のでもよい
。すなわち絶縁体よりなる平面形状が方形状の第１の平
板２２の上表面中央部に第１の平板２２より平面形状の
小さい第２の平板２３を備え、方形状の外部通信用端子
６は、第２の平板２３の上表面２３ａに１列に４個ずつ
２列に３１２び合計８個形成される。さらに方形状の検
査用端子７は、第２の平板２３が形成される以外の第１
の平板２２の上表面の４辺に１列ずつ複数個形成される
。The C module 2 is used for the laminated type and inset type IC cards formed as described above.
As shown in Figure (c), the test terminal 7 is formed to protrude from the four sides of the insulating section 20, which is a planar or rectangular flat plate. The IC module 2 including such an insulating part 20 has a terminal protection plate 2 for inspection made of an insulator having a rectangular planar shape larger than the insulating part 20, as shown in FIG. 9(a) or (b). It should be placed in the top center. Also, the first
As shown in the θ diagram, the IC module 2 may have an external communication terminal 6 and an inspection terminal 7 formed in the same direction. That is, a second flat plate 23 having a smaller planar shape than the first flat plate 22 is provided at the center of the upper surface of a first flat plate 22 made of an insulator and having a rectangular planar shape, and the rectangular external communication terminal 6 includes: On the upper surface 23a of the second flat plate 23, 312 pieces are formed in two rows, 4 pieces per line, for a total of 8 pieces. Furthermore, the rectangular test terminal 7 is connected to the first terminal other than the second flat plate 23 formed thereon.
A plurality of rows are formed on each of the four sides of the upper surface of the flat plate 22.
尚、２チツプタイプのＩＣモジュールにおいて外部通信
用端子数は、従来例及び本発明の実施例と乙に８９Ｊで
ある。検査用端子数は従来例では０側、本発明の実施例
では６６ｇである。この場合ｌＣモジュール内のＩＣチ
ップのパッド数は、ＣＰ Ｕ側が１８個、記憶素子側が
・１８ｇである。又、！チップタイプのＩＣモジュール
において、従来例では外部通信用端子数及び検査用端子
数ともに上述と同じであるが、本発明の実施例において
検査用端子数は１６個、外部通信用端子数は８個である
。この場合ＩＣチップのパッド数は２４個である。The number of external communication terminals in the two-chip type IC module is 89J in the conventional example, the embodiment of the present invention, and B. The number of test terminals is 0 in the conventional example and 66 g in the embodiment of the present invention. In this case, the number of pads of the IC chip in the IC module is 18 on the CPU side and 18g on the memory element side. or,! In the chip type IC module, in the conventional example, both the number of terminals for external communication and the number of terminals for testing are the same as described above, but in the embodiment of the present invention, the number of terminals for testing is 16, and the number of terminals for external communication is 8. It is. In this case, the number of pads on the IC chip is 24.
以上のようなＩＣモジュール２は、検査用端子゛７を利
用し内包するＩＣチップの健全性を確認する。健全なＩ
Ｃモジュール２は、ＩＣカード内へ組み込まれる。以下
にＩＣカードの製造方法を記載する。The IC module 2 as described above uses the inspection terminal 7 to confirm the soundness of the IC chip contained therein. healthy I
C module 2 is incorporated into the IC card. A method for manufacturing an IC card will be described below.
はめ込み型ＩＣカードの場合、第１１図に示すプラスチ
ックにてなるＩＣカードの強度部材で平板状のコア材２
５の縦横寸法及び厚さ寸法は、規格化された寸法であり
、コア材２５は、所定の形状をなす開口部２５ａを有し
、この開口部２５ａにＩＣモジュール２がはめ込まれる
。このＩＣモジュール２は、例えば上表面に外部通信用
端子６が形成され、第１２図に示すように下表面に検査
用端子７を形成したものである。コア材２５の上下表面
にはコア材２５と同じ平面形状で樹脂にてなる薄い表フ
ィルム２６及び裏フィルム２７がコア材２５に一致して
接着されｌＣカードｌを形成する。In the case of a built-in type IC card, a flat core material 2 is used as a strength member of the IC card made of plastic as shown in FIG.
The vertical and horizontal dimensions and the thickness dimension of 5 are standardized dimensions, and the core material 25 has an opening 25a having a predetermined shape, and the IC module 2 is fitted into this opening 25a. This IC module 2 has, for example, an external communication terminal 6 formed on the upper surface, and an inspection terminal 7 formed on the lower surface as shown in FIG. 12. A thin front film 26 and a thin back film 27 made of resin and having the same planar shape as the core material 25 are adhered to the upper and lower surfaces of the core material 25 in alignment with the core material 25 to form an IC card l.
尚、表フィルム２６には内包するＩＣモジュール２の外
部通信用端子６か対応する位置に予め開口部２６ａが形
成されており、ＩＣカードの外部データ処理装置は、こ
の開口部２６ａを通してＩＣモジュール２の外部通信用
端子６と接続することができる。一方検査用端子７は裏
フィルム２７により覆われ絶縁されるのでＩＣカードの
外部データ処理装置と接続することはない。Note that an opening 26a is previously formed in the front film 26 at a position corresponding to the external communication terminal 6 of the IC module 2 contained therein, and the external data processing device of the IC card is connected to the IC module 2 through this opening 26a. It can be connected to the external communication terminal 6 of. On the other hand, since the test terminal 7 is covered and insulated by the backing film 27, it is not connected to an external data processing device of the IC card.
又、ラミネート型ＩＣカードの場合、第１３図に示すよ
うに縦横寸法が前述したコア材２５とほぼ同一である回
路基板２８には載置されるＩＣモジュール２より幾分小
さい面積よりなる方形状の開口部２８ｂが形成される。In the case of a laminated IC card, as shown in FIG. 13, a circuit board 28 whose vertical and horizontal dimensions are almost the same as those of the core material 25 described above has a rectangular shape whose area is somewhat smaller than that of the IC module 2 to be mounted. An opening 28b is formed.
この開口部２８ｂの各４辺周辺にはＩＣモジュール２の
外表面に形成する８つの通信用端子６のみが接触可能な
ように方形状の平面形状の接続用端子２９が合計８個プ
リントされる。さらに接続用端子２９は、回路基板２８
上にプリントされた配線導体を介し同じく回路基板２８
上の一角に４個ずつ２列にプリントされた方形状の８個
の外部接続用端子３０と接続されている。一方ＩＣモジ
ュール２の検査用端子７は、結線されないので検査用端
子７とＩＣカードの外部データ処理装置とが接続される
ことはない。A total of eight connection terminals 29 in a rectangular planar shape are printed around each of the four sides of the opening 28b so that only the eight communication terminals 6 formed on the outer surface of the IC module 2 can contact them. . Further, the connection terminal 29 is connected to the circuit board 28
The circuit board 28 is also connected via the wiring conductor printed on the top.
It is connected to eight rectangular external connection terminals 30 printed in two rows of four terminals in each upper corner. On the other hand, since the test terminal 7 of the IC module 2 is not wired, the test terminal 7 and the external data processing device of the IC card are not connected.
このようなＩＣモジュール２が載置された回路基板２８
の上表面２８ａにはＩＣカードの強度部材である前述し
たコア材２５と同様のコア材２５゛が接着される。尚、
コア材２５゛には外部接続用端子３０が対応する位置に
予め開口部２５°ａが形成されている。さらにコア材２
５′の表面にはコア材２５゛と同形状にてなる薄い表フ
ィルム２６゛が接着され、回路基板２８の下表面２８ｂ
にはコア材２５′と同形状の裏フィルム２７が接着され
、ＩＣカードｌが形成されろ。尚、表フィルム２６′に
は外部接続用端子３０が対応する位置に予め４個ずつ２
列に方形状の開口部２６゛ａが形成されるので、回路基
板２８の上表面２８ａに形成される外部接続用端子３０
は、ＩＣカード表面より外部データ処理装置と接続可能
である。A circuit board 28 on which such an IC module 2 is mounted
A core material 25' similar to the aforementioned core material 25, which is a strength member of the IC card, is adhered to the upper surface 28a of the IC card. still,
An opening 25°a is previously formed in the core material 25′ at a position corresponding to the external connection terminal 30. Furthermore, core material 2
A thin front film 26'' having the same shape as the core material 25'' is adhered to the surface of the circuit board 28, and the lower surface 28b of the circuit board 28
A backing film 27 having the same shape as the core material 25' is adhered to the core material 25' to form an IC card 1. In addition, on the front film 26', two terminals (four each) are installed in advance at positions corresponding to the external connection terminals 30.
Since rectangular openings 26'a are formed in the rows, the external connection terminals 30 formed on the upper surface 28a of the circuit board 28 are
can be connected to an external data processing device from the surface of the IC card.
以上のようにＩＣモジュール内に装填されるＩＣチップ
と接続されろ複数の検査用端子を露出して備えることで
、ＩＣチップ内の各構成要素は、上記検査用端子を介し
て測定装置などと接続して健全性を直接検査できるので
、検査が行なえない構成部位はなくなる。さらにＩＣモ
ジュール１ｇ当りの検査時間は、例えば２チツプタイプ
のＩＣモジュールにおいて従来６分ｌＯ秒であったのに
対し本発明のＩＣモジュールでは３０秒であり、！チッ
プタイプのＩＣモジュールにおいては、従来３分５０秒
であったのに対し本発明のＩＣモジュールでは１５秒で
ある。このように本発明のＩＣモジュールは、検査時間
を従来の十分の一以下に短縮することができる。したが
って検査に要する工程数が減少しかつＩＣカードの大量
生産が可能となるので、ＩＣカードの大幅なコストダウ
ンを計ることができる。As described above, by providing a plurality of exposed test terminals connected to the IC chip loaded in the IC module, each component in the IC chip can be connected to a measuring device etc. via the test terminals. Since it can be connected and its health can be directly inspected, there are no components that cannot be inspected. Furthermore, the inspection time per gram of IC module was conventionally 6 minutes and 10 seconds for a 2-chip type IC module, but for the IC module of the present invention, it was 30 seconds! In a chip-type IC module, the conventional time is 3 minutes and 50 seconds, but in the IC module of the present invention, it is 15 seconds. In this way, the IC module of the present invention can shorten the inspection time to less than one-tenth of the conventional test time. Therefore, the number of steps required for inspection is reduced and IC cards can be mass-produced, resulting in a significant cost reduction of IC cards.
［発明の効果］
以上詳述したように本発明によれば、ＩＣモジュールに
装填されるｌＣチップに接続される複数の検査用端子を
ＩＣモジュールの外表面に露出して設置し、この検査用
端子を利用しＩＣチップ内の構成要素を直接検査するこ
とができるので、１個のＩＣモジュールに要する検査時
間は、大幅に短縮することができるとともに検査できな
いＩＣチップ内の構成要素はなくなる。[Effects of the Invention] As detailed above, according to the present invention, a plurality of test terminals connected to the IC chip loaded in the IC module are exposed and installed on the outer surface of the IC module, and the test terminals are exposed on the outer surface of the IC module. Since the components within the IC chip can be directly inspected using the terminals, the inspection time required for one IC module can be significantly reduced, and there are no components within the IC chip that cannot be inspected.
第１図及び第２図は、本発明のＩＣモジュールの構成を
概略に示す平面図、第３図は本発明のＩＣモジュールの
一実施例を示す縦断面図、第４図は第３図に示すＩＣモ
ジュールの平面図、第５図ないし第８図は、本発明のＩ
Ｃモジュールの一実施例を示す縦断面図、第９図（ａ）
ないしくｃ）は、本発明のＩＣモジュールの検査用端子
の一実施例を示す平面図、第１Ｏ図は、本発明のＩＣモ
ジュールの検査用端子の一実施例を示す斜視図、第１１
図及び第１３図は、本発明のＥＣモジュールを利用した
ＩＣカードの製造方法を示す斜視図、第１２図は、第１
１図に示すｔＣカードに使用されるＩＣモジュールの斜
視図である。
２・・・ＩＣモジュール、６・・・外部通信用端子、７
・・・検査用端子、 ３０・・・外部接続用端子。1 and 2 are plan views schematically showing the configuration of an IC module of the present invention, FIG. 3 is a longitudinal sectional view showing an embodiment of the IC module of the present invention, and FIG. The plan views of the IC module shown in FIGS. 5 to 8 are
A vertical cross-sectional view showing one embodiment of the C module, FIG. 9(a)
or c) is a plan view showing one embodiment of the test terminal of the IC module of the present invention, FIG. 1O is a perspective view showing one embodiment of the test terminal of the IC module of the present invention, and FIG.
13 and 13 are perspective views showing a method for manufacturing an IC card using the EC module of the present invention, and FIG.
2 is a perspective view of an IC module used in the tC card shown in FIG. 1. FIG. 2...IC module, 6...External communication terminal, 7
...Terminal for inspection, 30...Terminal for external connection.
Claims (5)
装置接続用の複数の外部通信用端子と、ＩＣチップの健
全性を検査するため前記ＩＣチップと接続する複数の検
査用端子とを外表面に設けたことを特徴とするＩＣモジ
ュール。(1) A plurality of external communication terminals for connection to an external data processing device to be connected to the loaded IC chip, and a plurality of test terminals to be connected to the IC chip to inspect the soundness of the IC chip are provided on the outer surface. An IC module characterized by being provided with.
用端子は被覆され外部通信用端子のみ外部データ処理装
置と接続できるように露出した、ＩＣモジュールを備え
たことを特徴とするＩＣカード。(2) An IC card comprising an IC module according to claim 1, wherein the test terminal provided in the IC module is covered and only the external communication terminal is exposed so that it can be connected to an external data processing device.
ュールを載置可能で、ＩＣモジュールの外部通信用端子
とのみ接続する外部接続用端子が形成されたプリント基
板を備えたことを特徴とするＩＣカード。(3) A printed circuit board on which an IC module having an inspection terminal and an external communication terminal can be placed, and an external connection terminal that connects only to the external communication terminal of the IC module is formed. IC card.
用端子と、ＩＣチップの健全性を検査するＩＣチップと
接続する複数の検査用端子とを備えたＩＣモジュールは
、検査用端子を利用してＩＣチップの健全性が検査され
る。検査後、検査用端子は被覆され外部通信用端子のみ
を外表面に露出して製造することを特徴とするＩＣカー
ドの製造方法。(4) An IC module equipped with a plurality of external communication terminals connected to an external data processing device and a plurality of test terminals connected to an IC chip that tests the health of the IC chip uses the test terminals. The health of the IC chip is then inspected. A method for manufacturing an IC card, characterized in that after the test, the test terminals are covered and only the external communication terminals are exposed on the outer surface.
用端子と、ＩＣチップの健全性を検査するＩＣチップと
接続する複数の検査用端子とを備えたＩＣモジュールは
、検査用端子を利用してＩＣチップの健全性が検査され
る。検査後ＩＣモジュールの外部通信用端子のみが外部
接続用端子と結線され製造されることを特徴とするＩＣ
カードの製造方法。(5) An IC module equipped with a plurality of external communication terminals connected to an external data processing device and a plurality of test terminals connected to an IC chip that tests the health of the IC chip uses the test terminals. The health of the IC chip is then inspected. An IC characterized in that after inspection, only the external communication terminal of the IC module is connected to the external connection terminal and manufactured.
How to make cards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63094244A JPH01263094A (en) | 1988-04-14 | 1988-04-14 | Ic card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63094244A JPH01263094A (en) | 1988-04-14 | 1988-04-14 | Ic card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01263094A true JPH01263094A (en) | 1989-10-19 |
Family
ID=14104895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63094244A Pending JPH01263094A (en) | 1988-04-14 | 1988-04-14 | Ic card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01263094A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7234644B2 (en) | 2000-01-25 | 2007-06-26 | Renesas Technology Corp. | IC card |
-
1988
- 1988-04-14 JP JP63094244A patent/JPH01263094A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7234644B2 (en) | 2000-01-25 | 2007-06-26 | Renesas Technology Corp. | IC card |
| US7303138B2 (en) | 2000-01-25 | 2007-12-04 | Renesas Technology Corp. | Integrated circuit card having staggered sequences of connector terminals |
| US7552876B2 (en) | 2000-01-25 | 2009-06-30 | Renesas Technology Corp. | IC card |
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