JPH01262672A - Pin diode - Google Patents
Pin diodeInfo
- Publication number
- JPH01262672A JPH01262672A JP9197388A JP9197388A JPH01262672A JP H01262672 A JPH01262672 A JP H01262672A JP 9197388 A JP9197388 A JP 9197388A JP 9197388 A JP9197388 A JP 9197388A JP H01262672 A JPH01262672 A JP H01262672A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- type semiconductor
- type
- pin diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000000969 carrier Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 59
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は順方向直列抵抗ｒ、が小さく且つ静電容量Ｃが
小さいＰＩＮダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a PIN diode with a small forward series resistance r and a small capacitance C.
（ロ）従来の技術
ＰＩＮダイオードは電子スイッチの基本回路動作を行う
半導体素子で、ＴＶやＦＭ等のチューナに利用される電
子同調システムや、ＶＴＲの高周波信号切替えスイッチ
として用いられ、スイッチ以外にもバンド切替えやＡＧ
Ｃ回路等に幅広く応用されている（特開昭５８−２２３
３７５号公報、ＨＯＩＬ２９／９１）。(b) Conventional technology A PIN diode is a semiconductor element that performs the basic circuit operation of an electronic switch, and is used in electronic tuning systems used in tuners such as TVs and FM, and as a high-frequency signal changeover switch in VTRs. Band switching and AG
It is widely applied to C circuits, etc. (Japanese Patent Laid-Open No. 58-223
375, HOIL29/91).
第６図は従来のＰＩＮダイオードを示す断面図である。FIG. 6 is a sectional view showing a conventional PIN diode.
同図において、（１）は例えば２，０００Ω口以上のＮ
形半導体基体、（２）はこのＮ形半導体基体（１）の−
主面の中心部分に形成したＰ″領域、（３）はこのＮ形
半導体基体（１）のＰ′″領域（３）を形成したー主面
の反対面に形成したＮ＋領領域（４）は前記Ｎ形半導体
基体（１）の表面に形成した酸化膜、（５〉は前記Ｐ１
領域（２）の中心部分に接すると共に、この酸化膜（４
）の周辺部分に接するように形成した電極、（６〉はＮ
”型のチャンネルストッパ、（７〉はフィールドプレー
トである。In the same figure, (1) is, for example, an N of 2,000Ω or more.
type semiconductor substrate, (2) is - of this N type semiconductor substrate (1)
The P'' region (3) formed at the center of the main surface is the P'' region (3) of this N-type semiconductor substrate (1) - the N+ region (4) formed on the opposite surface of the main surface. is an oxide film formed on the surface of the N-type semiconductor substrate (1), and (5> is the oxide film formed on the surface of the P1).
This oxide film (4) is in contact with the central part of the region (2).
), (6> is N
" type channel stopper, (7> is the field plate.
なお、前記半導体基体（１）中のＰ０領域（２）および
Ｎ３領域（３）を除いた領域がイントリンシック層とし
て動作する。Note that the region in the semiconductor substrate (1) other than the P0 region (2) and the N3 region (3) operates as an intrinsic layer.
この構成によるＰＩＮダイオードの主要な電気的特性は
周知のように、静電容量Ｃと順方向直列抵抗ｒ、とがあ
る。これらの特性はＰＩＮダイオードの設計寸法と密接
な関係があり、例えば順方向直列抵抗ｒ、はＰＩＮダイ
オードのイントリンシック層厚さｔｉに正比例し、接合
面積Ｓに反比例する。今、順方向直列抵抗ｒ、を非常に
小さな値に設計したい場合にはイントリンシック層厚ｄ
ｔｉを非常に薄くするか、または接合面積Ｓを非常に大
きくするかの何れかである。いいかえればＰＩＮダイオ
ードの機能を理想的な状態に近ずけるためにはこのイン
トリンシック層の実行的不純物濃度をできるだけ低下さ
せるため、Ｐ′″′″（２）およびＮ９領域（３）はそ
の不純物分布を階段状に形成する必要があり、そのため
にはＰ４領域（２）およびＮ４領域（３）を浅くする必
要がある。As is well known, the main electrical characteristics of a PIN diode with this configuration are a capacitance C and a forward series resistance r. These characteristics are closely related to the design dimensions of the PIN diode; for example, the forward series resistance r is directly proportional to the intrinsic layer thickness ti of the PIN diode and inversely proportional to the junction area S. Now, if you want to design the forward series resistance r to a very small value, the intrinsic layer thickness d
Either ti should be made very thin, or the bonding area S should be made very large. In other words, in order to bring the function of the PIN diode close to the ideal state, the effective impurity concentration of this intrinsic layer should be reduced as much as possible, so the P'''''' (2) and N9 regions (3) are It is necessary to form a stepwise distribution, and for this purpose it is necessary to make the P4 region (2) and the N4 region (3) shallow.
しかしながら、従来のＰＩＮダイオードではイントリン
シック層厚さｔｉを非常に薄くするためには半導体基体
の厚さを非常に薄くしなければならず、製造工程中で破
損し易くなる。現在の製造技術では、このイントリンシ
ック層厚キｔｉは１５０μｍ以上ないと、実際上取扱い
ができない。このため、大量生産を実施する上で、イン
トリンシック層厚さｔｉには下限があるため、性能上満
足できるＰＩＮダイオードが得られない。一方、接合面
積Ｓを非常に大きくして、順方向直列抵抗ｒ、を非常に
小言くする場合、ＰＩＮダイオードチップの面積も必然
的に非常に大きくなり、製造原価が高く、実際上市場性
がなくなる。However, in a conventional PIN diode, in order to make the intrinsic layer thickness ti very thin, the thickness of the semiconductor substrate must be made very thin, making it easy to break during the manufacturing process. With current manufacturing technology, it is practically impossible to handle this intrinsic layer thickness if it is less than 150 μm. For this reason, in carrying out mass production, there is a lower limit to the intrinsic layer thickness ti, making it impossible to obtain a PIN diode with satisfactory performance. On the other hand, if the junction area S is made very large and the forward series resistance r is made very small, the area of the PIN diode chip will inevitably become very large, and the manufacturing cost will be high, making it practically unmarketable. It disappears.
また、ＰＩＮダイオードの静電容量Ｃは空乏層の浮きと
反比例し、その空乏層の厚きはイントリンシック層の不
純物濃度と厚みｔｉによって大きく左右される。静電容
量Ｃを小さくしたい場合には、前記空乏層がより拡がり
易いように設計すれば良い。ところが、Ｎ型半導体基体
（１）と酸化膜（４）の界面付近では酸化膜（４）中に
含まれるＮａイオンの影響等により表面状態が変化し、
前記空乏層の厚みが他の部分よりも薄くなる為、静電容
量Ｃを増加させてしまう。Furthermore, the capacitance C of the PIN diode is inversely proportional to the lift of the depletion layer, and the thickness of the depletion layer is largely influenced by the impurity concentration and thickness ti of the intrinsic layer. If it is desired to reduce the capacitance C, the depletion layer may be designed to expand more easily. However, near the interface between the N-type semiconductor substrate (1) and the oxide film (4), the surface condition changes due to the influence of Na ions contained in the oxide film (4).
Since the thickness of the depletion layer becomes thinner than other parts, the capacitance C increases.
（ハ〉発明が解決しようとする課題
このように、従来は順方向直列抵抗ｒ、が非常に小さい
ＰＩＮダイオードを量産的規模で製造するには製造技術
上の問題があり、実現が困難である欠点があった。また
、静電容量Ｃが小さいＰＩＮダイオードを得るには前記
表面状態の問題があり、やはり実現が困難である欠点が
あった。(C) Problems to be Solved by the Invention As described above, it has been difficult to manufacture PIN diodes with very small forward series resistance r on a mass production scale due to manufacturing technology problems. In addition, there was the problem of the surface condition mentioned above in order to obtain a PIN diode with a small capacitance C, which also had the drawback of being difficult to realize.
（ニ）課題を解決するための手段
本発明は衛士した欠点に鑑み、Ｐ′″型半型体導体層４
）の周囲を囲むようにＰ０型のガードリング領域（１５
）を設けることによって、順方向直列抵抗ｒ。(d) Means for Solving the Problems In view of the disadvantages of the present invention, the P''' type semi-conductor conductor layer 4
) P0 type guard ring area (15
), the forward series resistance r.
が小さく、且つ静電容量Ｃが小さいＰＩＮダイオードを
提供するものである。The present invention provides a PIN diode with a small capacitance C and a small capacitance C.
（＊）作用
Ｎ型半導体基板（１１）は比抵抗が極めて高く、表面に
Ｐ型反転層が生じる為、Ｐ′″型半型体導体層４）とＰ
′″′″−ドリング領域（１５）とが前記反転層によっ
てつながり、電流注入がＰゝ型ガードリング領域（１５
）からも行なわれる。また、Ｐ１型型半体層（１４）か
ら横方向へ注入されたキャリアはガードリング領域（１
５）で捕獲され、再度下方向へ注入される。その為、実
質的にＰ＋型半導体層〈１４）をガードリング領域（１
５）の位置まで拡大したものに略等しくなり、電流の注
入効率が増す、さらに、Ｎ型半導体基板（１１）にはＰ
＋型ガードリング領域（１５）の拡散電位だけで空乏層
が拡がるので、との空乏層とＰ′″型半型体導体層４）
による空乏層とを重ねることにより基板（１１）表面近
傍での空乏層（２１）の厚みを厚くできる。(*) The working N-type semiconductor substrate (11) has an extremely high resistivity and a P-type inversion layer is formed on the surface, so the P''' type semi-conductor layer 4) and the P
The ``''''''-guard ring region (15) is connected by the inversion layer, and the current injection is connected to the P-type guard ring region (15).
) is also performed. Further, carriers injected laterally from the P1 type half layer (14) are transferred to the guard ring region (14).
5) and is injected downward again. Therefore, the P+ type semiconductor layer (14) is substantially covered by the guard ring region (1
5), which increases the current injection efficiency.Furthermore, the N-type semiconductor substrate (11) contains P.
Since the depletion layer expands only by the diffusion potential of the + type guard ring region (15), the depletion layer and the P'' type semi-conductor layer 4)
The thickness of the depletion layer (21) near the surface of the substrate (11) can be increased by overlapping the depletion layer (21) with the depletion layer (21).
〈へ）実施例
以下、本発明の一実施例を図面を参照しながら詳細に説
明する。Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
第１図は本発明によるＰＩＮダイオードの断面構造を示
す、同図において、（１１）は面方位（１１１）、比抵
抗ρ＝２０００Ω・σ、厚さｔｉ−１００乃至２００μ
ｍ程度のイントリンシック（Ｉ型）層となるＮ型半導体
シリコン基板、（１２）は基板（１１）の裏面に拡散法
あるいはエピタキシャル成長法によって形成した低比抵
抗のＮ９型半導体層、（１３）は基板＜１１）表面の周
端部にリング状に形成したＮ＋型のチャンネルストッパ
、（１４）は基板（１１）表面に選択的に拡散形成した
拡散深さ３乃至４μｍのＰ００型半導層、（１５）はＰ
＋型半導体層（１４）を囲む基板（１１）表面にリング
状に形成したＰ″型ガードリング領域、（１６〉は基板
（１１）表面を覆う酸化膜、（１７）はＰ＋型半導体層
（１４）にオーミックコンタクトするアノード電極、（
１８）はＮ″）型半導体層（１２）の全面にオーミック
コンタクトするカソード電極、（１９）はフィールドプ
レートである。Figure 1 shows the cross-sectional structure of the PIN diode according to the present invention. In the figure, (11) is the plane orientation (111), resistivity ρ = 2000Ω・σ, thickness ti-100 to 200μ
(12) is a low resistivity N9 type semiconductor layer formed on the back surface of the substrate (11) by a diffusion method or epitaxial growth method; (13) is an Substrate <11) N+ type channel stopper formed in a ring shape at the peripheral edge of the surface; (14) is a P00 type semiconductor layer with a diffusion depth of 3 to 4 μm selectively diffused on the surface of the substrate (11); (15) is P
A P″ type guard ring region formed in a ring shape on the surface of the substrate (11) surrounding the + type semiconductor layer (14), (16> is an oxide film covering the surface of the substrate (11), and (17) is a P+ type semiconductor layer ( 14) Anode electrode in ohmic contact with (
18) is a cathode electrode that makes ohmic contact with the entire surface of the N'' type semiconductor layer (12), and (19) is a field plate.
本願の特徴とするＰ＋型ガードリング領域（１５）は−
例としてＰ９９型半導層（１４）の形成と同時に拡散形
成しである。The P+ type guard ring region (15), which is a feature of the present application, is -
For example, diffusion is performed simultaneously with the formation of the P99 type semiconductor layer (14).
この様な本願構成のＰＩＮダイオードの両端に順方向バ
イアス電圧を印加するとＰ′″型半導体層（１４）から
！型層へのキャリア（ホール）の注入が行なわれ、アノ
ードからカソードへ順方向電流Ｉｔが流れる。その際、
順方向電流Ｉ、の大半はＰ３３型半導層（１４）の底部
から垂直にＮ１型半導体層（１２）へと流れる。When a forward bias voltage is applied to both ends of the PIN diode having the structure of the present invention, carriers (holes) are injected from the P'' type semiconductor layer (14) to the ! type layer, and a forward current flows from the anode to the cathode. It flows. At that time,
Most of the forward current I flows vertically from the bottom of the P33 type semiconductor layer (14) to the N1 type semiconductor layer (12).
ところが、Ｎ型半導体基板（１４）は比抵抗ρが約２０
００Ω・国と極めて高いので、基板（１１）の表面は外
部からの影響を受は易く、その表面順位や重金属の影響
等によりＰ型反転層（２ｏ）が生じている。すると、Ｐ
＋型半導体層（１４）とＰ９型ガードリング領域（１５
）とがつながるので、順方向電流Ｉ。However, the specific resistance ρ of the N-type semiconductor substrate (14) is approximately 20.
Since the resistance is extremely high at 00 Ω/mm, the surface of the substrate (11) is easily affected by external influences, and a P-type inversion layer (2o) is generated due to the surface order and the influence of heavy metals. Then, P
+ type semiconductor layer (14) and P9 type guard ring region (15)
) are connected, so the forward current I.
はＰ＋型ガードリング領域（１４）底部からの注入によ
っても流れる。また、順バイアス時にＰ９９型半導層（
１４）からＩ型層へ横方向に注入きれたキャリアは、大
部分が消滅せずにＰ４′型ガードリング領域（１５）に
達し、ガードリング領域（１５）に達したキャリアは、
順バイアスによる電界によってガードリング領域（１５
）底部から■型層へと再度注入される。その為、構造的
にはＰ９９型半導層（１４）をガードリング領域（１５
）の位置まで拡大したものに略等しく、順方向電流Ｉ、
の効率が増すので、順方向電圧Ｖ、を小さく、従って順
方向直列抵抗ｒ。also flows due to injection from the bottom of the P+ type guard ring region (14). In addition, when forward biasing, the P99 type semiconductor layer (
Most of the carriers that have been injected laterally into the I-type layer from 14) reach the P4'-type guard ring region (15) without disappearing, and the carriers that have reached the guard ring region (15) are
The guard ring region (15
) is injected again from the bottom into the ■ type layer. Therefore, structurally, the P99 type semiconductor layer (14) is connected to the guard ring region (15).
), and the forward current I,
The efficiency of the forward voltage, V, is reduced, and hence the forward series resistance, r, increases.
を低減できる。can be reduced.
一方、本願構造のＰＩＮダイオードの両端に逆方向バイ
アス電圧を印加すると、Ｐ００型半導層（１４）とＮ型
半導体基板（１１）とが形成するＰＮ接合に空乏層（２
１）が拡がり、その空乏層（２１）の厚みによってＰＩ
Ｎダイオードの接合容量Ｃが決まる。On the other hand, when a reverse bias voltage is applied to both ends of the PIN diode of the present structure, a depletion layer (2
1) expands, and due to the thickness of the depletion layer (21), PI
The junction capacitance C of the N diode is determined.
ところで、Ｎ型半導体基板（１１）のＮ型（Ｉ型）層は
比抵抗ρが極めて高いので、前記逆バイアス電圧が無く
てもＰ＋型半導体層（１４）の拡散電位だけである程度
の空乏層（２１）が拡がる。この現象は何の電位も印加
されないＰ０型ガードリング領域（１５）でも同様であ
る。その為、無バイアス時にこれらの空乏層（２１）が
連結するような位置にＰ０型ガードリング領域（１５）
を配設しておけば、空乏層（２１）が重畳するので基板
（１１）表面近傍における空乏層（２１〉の厚みを増大
できる。結果、ＰＩＮダイオードの接合容量Ｃを低減で
きる。尚、前記逆バイアス電圧を変化させてもＰ′″型
ガードリング領域（１５）の拡散電位による空乏層（２
１）は変化しないので、Ｐ′″型半導体層（１４）から
の空乏層（２１）がガードリング領域（１５）からの空
乏層（２１）を追い越すような逆バイアスを与えると前
記接合容量Ｃの低減効果は薄れる。By the way, since the N-type (I-type) layer of the N-type semiconductor substrate (11) has an extremely high specific resistance ρ, a depletion layer can be formed to some extent by the diffusion potential of the P+ type semiconductor layer (14) even without the reverse bias voltage. (21) expands. This phenomenon also occurs in the P0 type guard ring region (15) to which no potential is applied. Therefore, a P0 type guard ring region (15) is placed at a position where these depletion layers (21) are connected when no bias is applied.
By disposing the depletion layer (21), the thickness of the depletion layer (21) near the surface of the substrate (11) can be increased.As a result, the junction capacitance C of the PIN diode can be reduced. Even if the reverse bias voltage is changed, the depletion layer (2) due to the diffusion potential of the P'' type guard ring region (15)
1) does not change, so if a reverse bias is applied such that the depletion layer (21) from the P''' type semiconductor layer (14) overtakes the depletion layer (21) from the guard ring region (15), the junction capacitance C The reduction effect of
第２図に本願の第２の実施例を示す０本実施例はＰ＋型
ガードリング領域（１５）を深さ５〜１０μｍとより深
く形成したものであり、ガードリング領域（１５）が高
不純物濃度で深い為、ガードリング領域〈１５）の底部
から注入きれる電流経路の抵抗成分がＰ１１型半導層（
１４）の底部から注入される電流経路のそれよりも小さ
い、その為、全体の順方向直列抵抗ｒ、を一層低減でき
る。この効果はガードリング領域（１５）が深い程大き
く、またガードリング領域（１５）の不純物濃度が高い
程大きい、−方、ガードリング領域（１５）には何ら電
極が配設きれないので、ガードリング領域（１５）が形
成するＰＮ接合の空乏層はその拡散電位によるものより
は厚く拡がらない。その為、上述したＰＩＮダイオード
の耐圧はやはりＰゝ型半導体層（１４）が形成するＰＮ
接合の空乏層によるので、ガードリング領域（１５）を
深くしたことによる耐圧劣化は無い。FIG. 2 shows a second embodiment of the present application. In this embodiment, the P+ type guard ring region (15) is formed deeper to a depth of 5 to 10 μm, and the guard ring region (15) is highly impurity-containing. Because the concentration is deep, the resistance component of the current path that can be injected from the bottom of the guard ring region (15) is the P11 type semiconductor layer (
14) is smaller than that of the current path injected from the bottom of 14), so the overall forward series resistance r can be further reduced. This effect increases as the guard ring region (15) becomes deeper, and as the impurity concentration in the guard ring region (15) increases. The depletion layer of the PN junction formed by the ring region (15) does not expand to be as thick as that due to its diffusion potential. Therefore, the withstand voltage of the above-mentioned PIN diode is still the same as that of the PN formed by the P-type semiconductor layer (14).
Since this is due to the depletion layer of the junction, there is no breakdown voltage deterioration due to making the guard ring region (15) deep.
このように、本願はＰＩ型ガードリング領域（１５）を
設けることにより高性能のＰＩＮダイオードを得るもの
であり、その効果は第３図乃至第５図に示す如くになる
。第３図と第４図は夫々ＰＩＮダイオードのｒ、−Ｉ、
特性とＩ、−Ｖ、特性を示す０本願のＰＩＮダイオード
は順方向直列抵抗ｒ。As described above, the present invention provides a high performance PIN diode by providing the PI type guard ring region (15), and the effects thereof are as shown in FIGS. 3 to 5. Figures 3 and 4 show r, -I, and PIN diodes, respectively.
Characteristics and I, -V, Characteristics 0 The PIN diode of this application has a forward series resistance r.
が従来の５Ωから２〜３Ω（Ｉ Ｆ−１０ｍＡ ）に低
減できると共に、同図から明らかな如く順方向電流！、
に対する順方向直列抵抗ｒ、の直線性に優れる。また、
第５図はＰＩＮダイオードのＣ−Ｖ ＊特性を示し、同
図から明らかな如く、本願構造のものは逆方向電圧Ｖ、
が小さい領域で特に接合容量Ｃの低減効果が大きい。can be reduced from the conventional 5Ω to 2 to 3Ω (IF-10mA), and as is clear from the figure, the forward current! ,
Excellent linearity of the forward series resistance r. Also,
Figure 5 shows the C-V* characteristics of a PIN diode, and as is clear from the figure, the structure of the present invention has a reverse voltage V,
The effect of reducing the junction capacitance C is particularly large in the region where C is small.
（ト〉発明の詳細
な説明した如く、本発明によれば順方向直列抵抗ｒ、が
小きく且つ直線性に優れ、接合容量Ｃが小さい高性能の
ＰＩＮダイオードを提供できる利点を有する。その為、
電子チューナの高周波信号切替スイッチとして用いて好
適である。(G) As described in detail, the present invention has the advantage of providing a high-performance PIN diode with a small forward series resistance r, excellent linearity, and a small junction capacitance C. ,
It is suitable for use as a high frequency signal changeover switch for an electronic tuner.
第１図及び第２図は夫々本発明の第１と第２の実施例を
説明する為の断面図、第３図乃至第５図は本発明を説明
する為の特性図、第６図は従来例を説明する為の断面図
である。
〈１１）は１層となるＮ型半導体基板、（１２〉はＮ３
型半導体層、（１４）はＰ＋型半導体暦、（１５）はＰ
゛型ガードリング領域、（２１）は空乏層である。1 and 2 are sectional views for explaining the first and second embodiments of the present invention, FIGS. 3 to 5 are characteristic diagrams for explaining the present invention, and FIG. 6 is a sectional view for explaining the first and second embodiments of the present invention. FIG. 2 is a sectional view for explaining a conventional example. (11) is a single layer N-type semiconductor substrate, (12) is N3
type semiconductor layer, (14) is P+ type semiconductor layer, (15) is P
The ゛-type guard ring region (21) is a depletion layer.
Claims (3)
選択的に逆導電型の半導体層を形成したＰＩＮダイオー
ドにおいて、前記逆導電型半導体層を囲む前記高比抵抗
基板の表面に逆導電型のガードリング領域を設け、前記
逆導電型半導体層から前記高比抵抗基板へのキャリア注
入を行なうと共に、前記ガード、リング領域からもキャ
リア注入が行なわれるようにしたことを特徴とするＰＩ
Ｎダイオード。(1) In a PIN diode in which a semiconductor layer of an opposite conductivity type is selectively formed on the surface of a high resistivity substrate having a high concentration layer of one conductivity type, the surface of the high resistivity substrate surrounding the opposite conductivity type semiconductor layer is A guard ring region of opposite conductivity type is provided, and carriers are injected from the opposite conductivity type semiconductor layer to the high resistivity substrate, and carriers are also injected from the guard and ring regions. P.I.
N diode.
層と前記ガードリング領域の拡散電位が形成する空乏層
とが連結するような位置にガードリング領域を配置した
ことを特徴とする請求項第１項に記載のＰＩＮダイオー
ド。(2) A guard ring region is arranged at a position such that a depletion layer formed by the diffusion potential of the opposite conductivity type semiconductor layer and a depletion layer formed by the diffusion potential of the guard ring region are connected. PIN diode according to item 1.
同時形成されたものであることを特徴とする請求項第１
項に記載のＰＩＮダイオード。(3) Claim 1, wherein the guard ring region is formed simultaneously with the opposite conductivity type semiconductor layer.
PIN diode described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9197388A JPH01262672A (en) | 1988-04-14 | 1988-04-14 | Pin diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9197388A JPH01262672A (en) | 1988-04-14 | 1988-04-14 | Pin diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01262672A true JPH01262672A (en) | 1989-10-19 |
Family
ID=14041470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9197388A Pending JPH01262672A (en) | 1988-04-14 | 1988-04-14 | Pin diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01262672A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304824A (en) * | 1990-08-31 | 1994-04-19 | Sumitomo Electric Industries, Ltd. | Photo-sensing device |
| US6504178B2 (en) * | 1999-07-02 | 2003-01-07 | Digirad Corporation | Indirect back surface contact to semiconductor devices |
| WO2015194590A1 (en) * | 2014-06-18 | 2015-12-23 | 富士電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
-
1988
- 1988-04-14 JP JP9197388A patent/JPH01262672A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304824A (en) * | 1990-08-31 | 1994-04-19 | Sumitomo Electric Industries, Ltd. | Photo-sensing device |
| US6504178B2 (en) * | 1999-07-02 | 2003-01-07 | Digirad Corporation | Indirect back surface contact to semiconductor devices |
| WO2015194590A1 (en) * | 2014-06-18 | 2015-12-23 | 富士電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
| JPWO2015194590A1 (en) * | 2014-06-18 | 2017-04-20 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US10050133B2 (en) | 2014-06-18 | 2018-08-14 | Fuji Electric Co., Ltd. | Application of thin insulating film layer in semiconductor device and method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4607270A (en) | Schottky barrier diode with guard ring | |
| US5028548A (en) | Method of manufacturing a planar semiconductor device having a guard ring structure | |
| US6885077B2 (en) | Schottky diode | |
| US5041881A (en) | Whiskerless Schottky diode | |
| KR910008712B1 (en) | Schottky barrier semiconductor device | |
| US5345100A (en) | Semiconductor rectifier having high breakdown voltage and high speed operation | |
| US5705830A (en) | Static induction transistors | |
| JPH0766433A (en) | Semiconductor rectifier element | |
| US4999683A (en) | Avalanche breakdown semiconductor device | |
| US6225653B1 (en) | Semiconductor components and methods of manufacturing semiconductor components | |
| US4380021A (en) | Semiconductor integrated circuit | |
| US3755722A (en) | Resistor isolation for double mesa transistors | |
| JPH01262672A (en) | Pin diode | |
| US3707656A (en) | Transistor comprising layers of silicon dioxide and silicon nitride | |
| US4157561A (en) | High power transistor | |
| EP0064614B1 (en) | Improved emitter structure for semiconductor devices | |
| US3579278A (en) | Surface barrier diode having a hypersensitive {72 {30 {0 region forming a hypersensitive voltage variable capacitor | |
| US3855609A (en) | Space charge limited transistor having recessed dielectric isolation | |
| JPH08130317A (en) | Semiconductor device provided with resistive field plate | |
| JP3266250B2 (en) | Semiconductor device | |
| JP2001250962A (en) | Diode | |
| US4097887A (en) | Low resistance, durable gate contact pad for thyristors | |
| JPH02202061A (en) | Reverse conduction gate turn off thyristor | |
| JPH09181335A (en) | Semiconductor device | |
| KR19990010738A (en) | Power semiconductor device and manufacturing method |