JPH01261850A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH01261850A JPH01261850A JP8902688A JP8902688A JPH01261850A JP H01261850 A JPH01261850 A JP H01261850A JP 8902688 A JP8902688 A JP 8902688A JP 8902688 A JP8902688 A JP 8902688A JP H01261850 A JPH01261850 A JP H01261850A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- layer
- sealing resin
- substrate
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 239000011347 resin Substances 0.000 claims abstract description 56
- 229920005989 resin Polymers 0.000 claims abstract description 56
- 238000007789 sealing Methods 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 43
- 230000002093 peripheral effect Effects 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000012790 adhesive layer Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 230000001681 protective effect Effects 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229920001721 polyimide Polymers 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000002952 polymeric resin Substances 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 4
- 230000035939 shock Effects 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 238000005336 cracking Methods 0.000 description 11
- 230000006866 deterioration Effects 0.000 description 10
- 239000009719 polyimide resin Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920002050 silicone resin Polymers 0.000 description 4
- 239000007779 soft material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に係り、特に樹脂封止後
の封止！Ｉ４脂の硬化収縮によって、封入される回路基
板（以後、半導体チップと記す）の機能および封止樹脂
自体の特性が劣化するのを軽減するための構造の改良に
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resin-sealed semiconductor device, and particularly to sealing after resin-sealing! The present invention relates to an improvement in a structure for reducing deterioration of the function of an encapsulated circuit board (hereinafter referred to as a semiconductor chip) and the characteristics of the sealing resin itself due to curing shrinkage of I4 resin.
樹脂封止型半導体装置は、半導体素子、配線。 Resin-sealed semiconductor devices include semiconductor elements and wiring.
保護膜等が多数作り込まれた半導体ウェハを半導体チッ
プ（以下チップと略記する）に分割し、得られたチップ
をリードフレームに搭載し、チップの１′ｔ！極とリー
ドフレームのリードとを金線などで結線した後、該リー
ドフレームを金型にセットしてエポキシ樹脂等を主成分
とする樹脂により封止している。近年の大規模集積回路
では、チップ寸法が増々大きくなる傾向にあり、封Ｉｌ
ユ樹脂の硬化収縮によって発生する内部応力が急増大す
る。その結果、応力の集中するチップ周辺、特にコーナ
ー部での装ｆｆ！！成材料の変形や割れ、素子特性の劣
化等、さまざまな問題が顕在化してきた。A semiconductor wafer on which a large number of protective films and the like have been fabricated is divided into semiconductor chips (hereinafter abbreviated as chips), the resulting chips are mounted on a lead frame, and the 1't! After the poles and the leads of the lead frame are connected with gold wire or the like, the lead frame is set in a mold and sealed with a resin whose main component is epoxy resin or the like. In recent years, in large-scale integrated circuits, the chip size has tended to become larger and larger, and the packaging
The internal stress generated by the curing and shrinkage of the resin suddenly increases. As a result, mounting around the chip where stress is concentrated, especially at the corners, is reduced! ! A variety of problems have emerged, including deformation and cracking of component materials and deterioration of device characteristics.
第５図は、従来の樹脂封止型半導体装置の要部構造を示
す断面概略図であり、同図（ａ）はパッケージ内全体を
表わす断面図、同図（ｂ）は半導体チップ周辺領域の部
分断面図である。第５図（、ｉ）において４００はエポ
キシ等の樹脂から成る封止用樹脂、２００はリードフレ
ーム、１００は半導体素子（図示せず）が形成されてい
る半導体チップ、１１０はアルミニウム等から成る金属
配線、１１１はアルミニウム等から成る外部端子取出し
電極（ポンディングパッド）、１５０はシリコン酸化膜
（Ｓ ｉ Ｏｚ ）もしくはポリイミド樹脂等から成る
表面保護膜、３ｏＯは結線用の金線を表わす、また、同
図（ｂ）において１０１は半導体基板内の不純物拡散層
、１０２はシリコン酸化膜等の第１の層間絶縁層、１０
３は該層間絶縁層の一部に設けた接続用開孔部を表わす
、なおチップ分割を容易にするためにチップ周縁部（基
板ＶＲａ層）５００上の表面保護膜は通常除去する。FIG. 5 is a schematic cross-sectional view showing the structure of the main part of a conventional resin-sealed semiconductor device. FIG. FIG. In FIG. 5(,i), 400 is a sealing resin such as epoxy, 200 is a lead frame, 100 is a semiconductor chip on which a semiconductor element (not shown) is formed, and 110 is a metal such as aluminum. Wiring, 111 is an external terminal extraction electrode (ponding pad) made of aluminum or the like, 150 is a surface protection film made of silicon oxide film (S i Oz ) or polyimide resin, etc., 3oO is a gold wire for connection, and In the same figure (b), 101 is an impurity diffusion layer in the semiconductor substrate, 102 is a first interlayer insulating layer such as a silicon oxide film, and 10
Reference numeral 3 represents a connection opening provided in a part of the interlayer insulating layer. Note that the surface protective film on the chip peripheral portion (substrate VRa layer) 500 is usually removed to facilitate chip division.
このようなチップ１００を樹脂対＋ｈＬ、た場合。When such a chip 100 is made of resin +hL.
特にこの樹脂封止型半導体装置を低温と高温の雰囲気に
繰り返しさらした場合（熱衝撃試験）には、封Ｌ）、樹
脂の硬化収縮により半導体チップ１００に応力が加わる
。この応力は半導体チップ１００の端部、特にコーナー
部で大きく、その近傍の封止樹脂４００には割れが生じ
たり、チップ周縁部５００上のシリコン酸化膜から剥離
したりする。In particular, when this resin-sealed semiconductor device is repeatedly exposed to low and high temperature atmospheres (thermal shock test), stress is applied to the semiconductor chip 100 due to curing and shrinkage of the resin. This stress is large at the edges of the semiconductor chip 100, especially at the corners, and the sealing resin 400 in the vicinity may crack or peel off from the silicon oxide film on the chip peripheral portion 500.
特に封止用樹脂はシリコン、シリコン酸化膜、シリコン
窒化膜等との接着力は弱く、収縮応力により封止用樹脂
が割れたり、剥離したりしやすい。In particular, the sealing resin has weak adhesion to silicon, silicon oxide film, silicon nitride film, etc., and is likely to crack or peel off due to shrinkage stress.
その結果、応力の集中場所がより内側に移動し。As a result, the location of stress concentration moves further inward.
この応力によりチップ上の表面保護膜１５０がシリコン
酸化膜の場合には割れが生じ、ポリイミド樹脂膜の場合
には変形、剥離が生じ、その結果金属配線１１０が変形
、断線、短絡したりする故障が問題となっている。また
、封止用樹脂の割れは。This stress causes cracks in the case where the surface protection film 150 on the chip is a silicon oxide film, and causes deformation and peeling in the case of a polyimide resin film, resulting in failures such as deformation, disconnection, and shorting of the metal wiring 110. is a problem. Also, cracks in the sealing resin.
外部からの水の浸入を促すため、配線金属等の腐食を加
速させたり外部端子接続用の金線とボンデインパッドと
の接合も破壊したりし装置の信頼性を低下せしめ１重大
な問題となる。Because it encourages water intrusion from the outside, it accelerates the corrosion of metal wiring, etc., and destroys the bond between the gold wire for external terminal connection and the bonding pad, reducing the reliability of the device.1 This is a serious problem. Become.
このような問題に対して、従来からいくつかの対策が請
じられている。これらは、封止樹脂４００を改良して低
応力化すること、チップ上の表面保護膜１５０を改良し
てチップに加オ）る応力を軽減したり緩和することの２
つに大別できろ、このうち１表面保護膜の改良方法とし
て以下の公知例などがある。特公昭６１−３４２５６に
は表面保護膜として用いるシリコン酸化膜１５０のＰｉ
みを金属配線１１０の厚み以上にする、また特開昭６１
−２８４９３０には半導体チップの外周部だけに表面保
護膜として機械的強度の大きな窒化膜を設けることが記
載されている。また、他の例として、特開昭６０−１４
０７３９には表面保護膜としてシリコン酸化膜から成る
層の上にさらにポリイミド樹脂等の比較的弾性率の小さ
な材料を設は応力を吸収しようとするもの、特開昭６１
−１７１１５６には半導体チップ周縁部にシリコン樹脂
等の軟質材を設は同じく応力負荷を吸収するもの等が記
載されている。Several countermeasures have been sought to address such problems. These include improving the sealing resin 400 to reduce stress and improving the surface protective film 150 on the chip to reduce or alleviate the stress applied to the chip.
It can be roughly divided into two types. Among these methods, there are the following known examples of methods for improving the surface protective film. Japanese Patent Publication No. 61-34256 discloses a silicon oxide film 150 used as a surface protection film.
The thickness of the metal wiring 110 is made to be greater than the thickness of the metal wiring 110.
284930 describes that a nitride film with high mechanical strength is provided as a surface protection film only on the outer periphery of a semiconductor chip. In addition, as another example, JP-A-60-14
No. 0739 discloses a method in which a material with a relatively low elastic modulus such as a polyimide resin is further provided on a layer of silicon oxide film as a surface protective film in order to absorb stress.
171156 describes a device in which a soft material such as silicone resin is provided at the peripheral edge of a semiconductor chip to absorb the stress load.
さらにまた特開昭５８−２７３４！１に記載の半導体装
置は、半導体チップの周囲に溝を形成し、半導体チップ
と封止樹脂との密着性を向上させ半導体装置の信頼性を
高めていた。Furthermore, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 58-2734!1, a groove is formed around the semiconductor chip to improve the adhesion between the semiconductor chip and the sealing resin, thereby increasing the reliability of the semiconductor device.
近年、半導体装置の集積化が進み、チップの大型化や素
子、配線の微細化が急速に進んでいる。In recent years, the integration of semiconductor devices has progressed, and the size of chips and the miniaturization of elements and wiring are rapidly progressing.
その結果、チップサイズが１０ｍ口を起えたり。As a result, the chip size increased to 10m.
配線の幅や間隔がサブミクロン領域にまで縮小された来
秋回路が実現されている。これらのチップを樹脂封止し
た場合、前記従来技術ではチップに加わる応力の軽減が
不充分となってきた。A circuit will be realized next fall in which the width and spacing of wiring lines has been reduced to the submicron range. When these chips are sealed with resin, the stress applied to the chips has not been sufficiently reduced by the conventional techniques.
特に前述の従来例のうち最初の２つの例では。Especially in the first two examples of the prior art mentioned above.
表面保護膜としてのシリコン酸化膜や窒化膜と封止用レ
ジンとの接着力が弱いという欠点をいぜん有しており、
収縮応力の増大にともない封止用樹脂が割れたり、剥離
したりし半導体装置の信頼性を低下させる。また、その
次の２つの公知例のようにチップ表面や周縁部にポリイ
ミド樹脂やシリコン樹脂等の軟質材を設けても１本構造
の場合以下の点で問題があった。半導体ウェハをチップ
に分割する時には１分離のためにダイヤモンドポイント
やダイヤモンドブレードで溝を入れるスクライビング工
程および溝に応じてウェハを割り個々のチップに分割す
るクラッキング工程を行なう必要がある。前述の公知例
（従来構造）では、スクライブ領域にもポリイミド樹脂
やシリコーン樹脂等の軟質材があり、スクライビング時
にはこれらの材料をも切断することになる。しかしなが
らポリイミド樹脂やシリコーン樹脂等の軟質材の切断は
極めて作業性が悪い、また、本工程はこれらの樹脂層の
剥離の原因ともなり、樹脂封ｌヒ後の半導体装置の信頼
性の低下をきたす要因ともなる。However, it still has the disadvantage of weak adhesion between the silicon oxide film or nitride film used as a surface protection film and the sealing resin.
As the shrinkage stress increases, the sealing resin may crack or peel, reducing the reliability of the semiconductor device. Further, even if a soft material such as polyimide resin or silicone resin is provided on the chip surface or peripheral portion as in the following two known examples, the single-piece structure has the following problems. When dividing a semiconductor wafer into chips, it is necessary to perform a scribing process in which grooves are created with a diamond point or a diamond blade for one separation, and a cracking process in which the wafer is divided into individual chips according to the grooves. In the above-mentioned known example (conventional structure), there is also a soft material such as polyimide resin or silicone resin in the scribe area, and these materials are also cut during scribing. However, cutting soft materials such as polyimide resin and silicone resin is extremely difficult to work with, and this process also causes peeling of these resin layers, reducing the reliability of semiconductor devices after resin sealing. It can also be a factor.
また前述の最後に示した公知例においては、半導体チッ
プ周辺に設けた溝内へ、封止樹脂が充填されにくいため
にその効果が少なく、封止樹脂の割れ９表面保護膜の剥
離、配線特性の劣化等に起因した故障の発生は避けられ
なかった。In addition, in the known example shown at the end of the above, the sealing resin is difficult to fill into the groove provided around the semiconductor chip, so the effect is small, cracks in the sealing resin, peeling of the surface protective film, and wiring characteristics. The occurrence of failures due to deterioration, etc., was unavoidable.
なお、大規模化、複雑化する集積回路の実現に不可欠な
多層配線構造においても、封止樹脂の収縮応力に起因し
て生じる配線層間の絶縁性の劣化や配線層間の接続（コ
ンタクト）特性の劣化等がより深刻な問題となっている
。In addition, even in the multilayer wiring structure that is essential for realizing integrated circuits that are becoming larger and more complex, there is a risk of deterioration of the insulation between wiring layers due to the shrinkage stress of the sealing resin, and of the connection (contact) characteristics between the wiring layers. Deterioration has become a more serious problem.
本発明の目的は、前述の問題、特に封止用樹脂の割れや
剥離の問題を解決し、ひいては表面保護膜の変形、剥離
、配線特性の劣化の問題を解決し大型化、微細化、多層
配線化する樹脂封止半導体装置の信頼性を向上すること
にある。The purpose of the present invention is to solve the above-mentioned problems, especially the problems of cracking and peeling of the sealing resin, and also solve the problems of deformation, peeling, and deterioration of wiring characteristics of the surface protective film, and to solve the problem of increasing size, miniaturization, and multilayer The object of the present invention is to improve the reliability of resin-sealed semiconductor devices that are wired.
上記目的は、従来技術においては周辺基板層と封止用樹
脂との接着性に留意されていなかったのに対し、本発明
においては、周縁部領域の表面がシリコン、シリコン酸
化膜、シリコン窒化膜などの比較的封止用樹脂と密着力
が弱い周縁基板層を有する半導体チップであっても、前
記周縁部領域の該周縁基板層や封止用樹脂との密着性が
、該周縁基板層と該封止用樹脂との密着性より大なる接
着層を該周縁基板層と該封止用樹脂との間に介在させる
ことにより達成される。前述の接着層としては、金属膜
や金属の酸化物、窒化物、硅化物等の金属化合物膜が適
している。The above object is achieved by using a method in which the surface of the peripheral region is coated with silicon, silicon oxide film, silicon nitride film, etc. whereas in the prior art, no attention was paid to the adhesion between the peripheral substrate layer and the sealing resin. Even in a semiconductor chip having a peripheral substrate layer having relatively weak adhesion to the encapsulating resin such as This is achieved by interposing an adhesive layer with greater adhesion than the sealing resin between the peripheral substrate layer and the sealing resin. As the adhesive layer mentioned above, a metal film or a metal compound film such as a metal oxide, nitride, or silicide is suitable.
本発明においては、前記接着層が半導体チップの周縁部
領域の基板周縁層と封止用樹脂との接着層となる。半導
体チップと封止用樹脂の密着力が強くなると、封止用樹
脂の割れや剥離が生じにくくなり、その結果表面保護膜
の変形や剥離、金属配線の変形、断線、短絡等の故障の
発生率が低減する。In the present invention, the adhesive layer serves as an adhesive layer between the substrate peripheral layer in the peripheral region of the semiconductor chip and the sealing resin. When the adhesion between the semiconductor chip and the encapsulating resin becomes stronger, cracking and peeling of the encapsulating resin become less likely to occur, resulting in failures such as deformation and peeling of the surface protective film, deformation of metal wiring, disconnection, and short circuits. rate is reduced.
以下１本発明を実施例により詳細に説明する。 The present invention will be explained in detail below using examples.
実施例１ 第１図は本発明の樹脂封止型半導体装置の一例である。Example 1 FIG. 1 shows an example of a resin-sealed semiconductor device of the present invention.
同図は、半導体チップの周ａ領域の部分断面概略図であ
り、（ａ）〜（Ｑ）は半導体ウニへ上での製作過程を示
し、（ｄ）は半導体チップを組立て、封止した後の樹脂
封止型半導体装置を示す、以下第１図に従って説明する
が製作方法はすべて周知の半導体装置製造技術によるも
のである。まず同図（、）に示すように、不純物拡＠層
１０１を形成したシリコン基板１００上に、ｆｔｔ横取
出し孔１０３および半導体チップの周縁領域（基板周縁
層）５００以外を０．５μｍ程度のノダさを有するシリ
コン酸化物から成る第１の層間絶＄１［１０２によって
被覆する。なお、１６０で示した位置は隣接する半導体
チップとの境界となり。The same figure is a partial cross-sectional schematic diagram of the peripheral region a of the semiconductor chip, (a) to (Q) show the manufacturing process of the semiconductor chip, and (d) shows the process after the semiconductor chip is assembled and sealed. A resin-sealed semiconductor device will be described below with reference to FIG. 1, and all manufacturing methods are based on well-known semiconductor device manufacturing techniques. First, as shown in FIG. The first interlayer 102 is made of silicon oxide having a high temperature. Note that the position indicated by 160 is the boundary between adjacent semiconductor chips.
この位置で半導体ウェハが切断され、チップに分割され
ることになる。At this location, the semiconductor wafer will be cut and divided into chips.
次に、同図（ｂ）に示すようにアルミニウム合金等から
成る厚さ約１μｍの金属配線１１０を被覆し、所望のパ
ターンに加工する。ついで、シリコン基板が露出した基
板周縁層に、０．１μｍ程度の厚さを有する窒化チタン
膜１２０を形成する。Next, as shown in FIG. 4B, a metal wiring 110 made of aluminum alloy or the like having a thickness of about 1 μm is coated and processed into a desired pattern. Next, a titanium nitride film 120 having a thickness of about 0.1 μm is formed on the substrate peripheral layer where the silicon substrate is exposed.
本窒化チタン膜は、スパッタターゲットとしてチタンを
用い、放電ガスとしてアルゴンと窒素の混合ガスを用い
た通常のＲＦスパッタ法により堆積した。加工は、四塩
化炭素と酸素を主成分とした反応ガスを用いたドライエ
ツチングにより行った。This titanium nitride film was deposited by a normal RF sputtering method using titanium as a sputtering target and a mixed gas of argon and nitrogen as a discharge gas. The processing was carried out by dry etching using a reactive gas containing carbon tetrachloride and oxygen as main components.
次に第１図（Ｑ）に示すように１表面保護膜１５０を形
成した０本表面保護膜は２μｍ程度の厚さを有するポリ
イミド系の高分子樹脂から成り、ポンディングパッド１
１１および基板周縁層５００上の表面保護膜は除去した
。その後、半導体ウェハをスクライブライン１６０に沿
って通常のスクライビングおよびクラッキング工程によ
りチップ分割した。その後周知の樹脂封止組立技術によ
り。Next, as shown in FIG. 1 (Q), the surface protective film 150 on which the single surface protective film 150 is formed is made of polyimide-based polymer resin with a thickness of about 2 μm, and the bonding pad 150 is
11 and the surface protective film on the substrate peripheral layer 500 were removed. Thereafter, the semiconductor wafer was divided into chips along the scribe line 160 by a conventional scribing and cracking process. Then, using the well-known resin sealing assembly technology.
同図（ｄ）に示すように該チップをリードフレーム（図
示せず）に搭載し、チップのＷ１極とリードフレームの
リードとを金線３００で結線し、該リードフレームを金
型にセットしてエポキシ等を主成分とする封止用樹脂４
００により封止した。As shown in the same figure (d), the chip is mounted on a lead frame (not shown), the W1 pole of the chip and the lead of the lead frame are connected with a gold wire 300, and the lead frame is set in a mold. Sealing resin 4 whose main component is epoxy etc.
It was sealed with 00.
本実施例で適用した窒化チタン膜は、シリコン基板１０
０および封止用樹脂４００との接着力は極めて強い、し
たがって、本実施例によれば半導体チップ周縁領域にお
けるチップと封止用樹脂との被着強度が向上し、熱衝撃
試験による封止用樹脂の割れや剥離を防止する効果があ
る。したがって、封止用樹脂の割れやはがれに起因した
半導体回路の劣化を防ぐことができる。The titanium nitride film applied in this example was applied to a silicon substrate 10.
0 and the sealing resin 400 are extremely strong. Therefore, according to this example, the adhesion strength between the chip and the sealing resin in the peripheral area of the semiconductor chip is improved, and the sealing resin 400 is It has the effect of preventing cracking and peeling of the resin. Therefore, deterioration of the semiconductor circuit due to cracking or peeling of the sealing resin can be prevented.
８ｍｍ口サイズのテストチップを樹脂封止した試料を用
いて配線特性の熱Ｎ撃試験を行った結果。The results of a thermal N shock test on wiring characteristics using a resin-sealed test chip with an 8mm opening size.
従来法による場合の不良率が４０％以上あったのに対し
１本実施例によるものの不良率は１０％以下に低減され
た。While the defective rate in the case of the conventional method was 40% or more, the defective rate in the case of the present embodiment was reduced to 10% or less.
なお１本実施例では、接着層１２０が表面保護膜１５０
の外周部下の一部に延在しているが、基板周縁層上のみ
に配置しても本発明の効果が失われるものではない。Note that in this embodiment, the adhesive layer 120 is the surface protective film 150.
However, the effects of the present invention are not lost even if it is placed only on the peripheral edge layer of the substrate.
また、本実施例ではチップ分割工程（スクライビング、
クラッキング）での作業性の低下や製品留歩りの低下と
いった問題は全く生じなかった。In addition, in this example, the chip dividing process (scribing,
There were no problems such as a decrease in workability due to cracking or a decrease in product retention.
実施例２
第２図は１本発明の樹脂封止型半導体装置の他の実施例
を表わす図であり、半導体チップ周縁部の部分断面概略
図を示す０本実施例では、チップの基板周縁層５００上
に設けた窒化チタン膜１２０が、表面保護膜であるポリ
イミド樹脂１５０上の一部の上に延在していることが先
の実施例１と大きく異なる点である。製作工程も実施例
１とほとんど同じであるが１表面保護膜の形成・加工後
に接着層１２０の形成加工を行い、かつ接着層である窒
化チタン膜の加工は過酸化水素水によるウェットエツチ
ングにより行った事が先の例とは異なる点である。Embodiment 2 FIG. 2 is a diagram showing another embodiment of the resin-sealed semiconductor device of the present invention, and shows a partial cross-sectional schematic diagram of the peripheral edge of a semiconductor chip. In this embodiment, the peripheral layer of the substrate of the chip is This embodiment differs greatly from the first embodiment in that the titanium nitride film 120 provided on the surface protection film 120 extends over a portion of the polyimide resin 150 serving as the surface protection film. The manufacturing process is also almost the same as in Example 1, except that the adhesive layer 120 is formed after the surface protective film is formed and processed, and the titanium nitride film that is the adhesive layer is processed by wet etching with hydrogen peroxide solution. This is different from the previous example.
本実施例の構造では、接着層１２０が表面保護膜１５０
の外周端部を保護しているため１表面保護膜１５０の剥
離防止により効果がある。In the structure of this embodiment, the adhesive layer 120 is connected to the surface protective film 150.
Since it protects the outer peripheral edge of the first surface protective film 150, it is more effective in preventing peeling of the first surface protective film 150.
実施例３
第３図は、本発明の樹脂封止型半導体装置の他の実施例
を表わす図である０本実施例ではチップの基板周縁層５
００の表面はシリコン酸化物１０２から成ることが実施
例１と異なる点である。接着層である窒化チタンＩＩＪ
１２０はシリコン酸化物との接着力も強く本構造にお
いても封止用樹脂の割れ、剥離等は発生せず、従来構造
に比べ装置の信頼性が向上した。Embodiment 3 FIG. 3 is a diagram showing another embodiment of the resin-sealed semiconductor device of the present invention. In this embodiment, the substrate peripheral layer 5 of the chip is
The difference from Example 1 is that the surface of 00 is made of silicon oxide 102. Titanium nitride IIJ as adhesive layer
120 has strong adhesion to silicon oxide, and even in this structure, cracking or peeling of the sealing resin did not occur, and the reliability of the device was improved compared to the conventional structure.
実施例４
第４図は１本発明の樹脂封止型半導体装置の他の実施例
を表わす図であり、半導体チップの周縁領域の部分断面
概略図である０本実施例は金属配線１１０，１３０が第
２の層間絶縁膜１４０を介して二層構造化していること
が先の実施例１と異なる。実施例１と同様にシリコン基
板１００上に第１の層間絶縁膜１０２として０．５μｍ
厚さのシリコン酸化膜、接着層１２０として０．１μｍ
の厚さを有する窒化チタン股、第１の配線ＷＪ１１０と
して１μｍの厚さのアルミニウム合金属を形成した後、
第２の層間絶縁膜１３０としてポリイミド樹脂を約２．
３μｍの厚さに形成し、配線層間接続孔１１５をおよび
基板周ａ層５００の領域を除去した後、１．５μｍの厚
さを有するアルミニウム合金から成る第２の配線層１４
０を形成した。Embodiment 4 FIG. 4 is a diagram showing another embodiment of the resin-sealed semiconductor device of the present invention, and is a schematic partial cross-sectional view of the peripheral area of a semiconductor chip. This embodiment differs from the first embodiment in that it has a two-layer structure with a second interlayer insulating film 140 interposed therebetween. As in Example 1, a first interlayer insulating film 102 of 0.5 μm is formed on a silicon substrate 100.
Silicon oxide film with a thickness of 0.1 μm as the adhesive layer 120
After forming a titanium nitride crotch with a thickness of , and an aluminum alloy metal with a thickness of 1 μm as the first wiring WJ110,
The second interlayer insulating film 130 is made of polyimide resin about 2.
A second wiring layer 14 made of aluminum alloy is formed to have a thickness of 3 μm, and after removing the interconnection interlayer connection hole 115 and the area of the substrate peripheral A layer 500, the second wiring layer 14 is formed to have a thickness of 1.5 μm.
0 was formed.
その後、ポリイミド樹脂から成る表面保護膜１５０を実
施例１と同様に、ポンディングパッド１１１および基板
間ａ層５００以外の領域に形成し、最後に樹脂封止組立
てを行った。Thereafter, a surface protection film 150 made of polyimide resin was formed in a region other than the bonding pad 111 and the inter-substrate a layer 500 in the same manner as in Example 1, and finally resin sealing was performed.
従来の二層金属配線構造は、特に封止樹脂の応力が加わ
った場合に配線がＴｐｆｒ線したり短絡したりしやすく
、その耐性が弱かった。しかしながら、本実施例によれ
ば、二層金属配線構造においても封止樹脂の割れ、剥離
や配線特性の劣化などに起因した不良率は、従来の１７
５以下となり、信頼性の向上に効果があった。In the conventional two-layer metal wiring structure, the wiring tends to become a Tpfr line or short-circuit, especially when stress from the sealing resin is applied, and its resistance is weak. However, according to this example, even in a two-layer metal wiring structure, the defective rate due to cracking and peeling of the sealing resin, deterioration of wiring characteristics, etc. is lower than the conventional 17.
5 or less, which was effective in improving reliability.
なお、本実施例ではチップ上に形成した金属配線は二層
箭造であるが、配線が３ＸＩＪ以上の構造の場合でも本
発明が有効であることは言うまでもない。In this embodiment, the metal wiring formed on the chip has a two-layer structure, but it goes without saying that the present invention is effective even when the wiring has a structure of 3XIJ or more.
以上の実施例では、基板周、１１！層５００はシリコン
やシリコン酸化物の例を挙げたが、窒化チタン膜と接着
力が大きい物質、シリコン窒化膜等でも同様の効果が得
られる。In the above embodiment, the substrate circumference is 11! Although the layer 500 is made of silicon or silicon oxide as an example, the same effect can be obtained by using a material that has strong adhesion to the titanium nitride film, such as a silicon nitride film.
また、実施例では、基板周縁層５００上に設ける接着層
として窒化チタン膜を適用したが、封止樹脂やシリコン
等との接着力が、封止樹脂とシリコン等との接着力が大
なるものであれば、他の物質を適用しても本発明の効果
は得られる。封止用樹脂やシリコン等との接着力が比較
的大きな材料としては、本実施例で採用した窒化チタン
の他。In addition, in the embodiment, a titanium nitride film was used as the adhesive layer provided on the substrate peripheral layer 500, but the adhesive strength with the sealing resin, silicon, etc. is strong, and the adhesive strength between the sealing resin and silicon, etc. is strong. If so, the effects of the present invention can be obtained even if other substances are used. In addition to titanium nitride, which was used in this example, materials that have relatively strong adhesive strength with sealing resin, silicon, etc.
チタン、アルミニウム、タングステン等の金属やアルミ
ナ、酸化チタン等の金属の窒化物、Ｍ化物。Nitride and Mide of metals such as titanium, aluminum, and tungsten, and metals such as alumina and titanium oxide.
硅化物等があり、ニオしらの単層膜もしくは積層膜を用
いても本発明の目的は達成される。There are silicides, etc., and the object of the present invention can be achieved even if a single layer film or a laminated film of niobium silica is used.
なお、樹脂封止型半導体装置では半導体チップに働く応
力はチップ外縁部、特にチップコーナー部で最も大きく
、その影響による故障も発生しやすい０本発明で示した
接着層を、少なくともチップコーナー部に設けることだ
けでも本発明の効果があられれることは明らかである。In a resin-sealed semiconductor device, the stress acting on the semiconductor chip is greatest at the outer edges of the chip, especially at the chip corners, and failures due to this influence are likely to occur. It is clear that the effects of the present invention can be achieved simply by providing the above.
以上説明したように本発明によれば、封止用樹脂と半導
体チップの周縁領域との接着強度が向上し、熱衝撃等で
生じる封止用樹脂の応力によって引き起こされる封止用
樹脂の割れや剥離２表面保護膜の変形やクラックや剥離
等を防止することができる。したがって、それらに起因
した配線の変形、断線、短絡等の劣化による装置の品質
の低下が防止されるので、半導体装置の信頼性が向上す
る。As explained above, according to the present invention, the adhesive strength between the encapsulating resin and the peripheral area of the semiconductor chip is improved, and cracks in the encapsulating resin caused by stress in the encapsulating resin caused by thermal shock, etc. can be improved. Peeling 2 Deformation, cracking, peeling, etc. of the surface protective film can be prevented. Therefore, deterioration of the quality of the device due to deterioration such as deformation, disconnection, short circuit, etc. of the wiring caused by these is prevented, and the reliability of the semiconductor device is improved.
第１図〜第４図は本発明の一実施例の樹脂封止型半導体
装置の部分断面概略図、第５図は従来の樹脂封止型半導
体装置の全体断面概略図および部分断面概略図である。
１００・・・半導体チップ、１０２・・・第１の層間絶
縁膜、１１０・・・第１の配線層、１２０・・・接Ｍ層
。
１３０・・・第２の層間絶縁膜、１４０・・・第２の配
線層、１５０・・・表面保護膜、２００・・・リードフ
レーム、３００・・・ボンディングワイヤ、４００・・
・封止用樹脂、５００・・・基板周縁層。
第５凹
（ｂ）
７５０ 表面伏ｊｌ躾1 to 4 are partial cross-sectional schematic diagrams of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 5 is an overall cross-sectional schematic diagram and a partial cross-sectional schematic diagram of a conventional resin-sealed semiconductor device. be. 100... Semiconductor chip, 102... First interlayer insulating film, 110... First wiring layer, 120... Contact M layer. 130... Second interlayer insulating film, 140... Second wiring layer, 150... Surface protective film, 200... Lead frame, 300... Bonding wire, 400...
- Sealing resin, 500...substrate peripheral layer. 5th concave (b) 750 surface down jl discipline
Claims (1)
よび表面保護膜を有し、該周縁部領域の表面がシリコン
、シリコン酸化物もしくはシリコン窒化物の層からなる
基板周縁層をそなえた半導体回路基板を封止用樹脂によ
り封止した半導体装置において、前記周縁部領域の基板
周縁層および該封止用樹脂との密着性が、該基板周縁層
と該封止用樹脂との密着性より大なる接着層を該基板周
縁層と該封止用樹脂との間に介在させたことを特徴とす
る樹脂封止型半導体装置。 ２、前記接着層が少なくとも金属、金属の酸化物、窒化
物もしくは硅化物等の膜であることを特徴とする特許請
求の範囲第１項記載の樹脂封止型半導体装置。 ３、前記表面保護膜がポリイミド系の高分子樹脂膜であ
ることを特徴とする特許請求の範囲第１項もしくは第２
項記載の樹脂封止型半導体装置。 ４、前記接着層が少なくとも前記表面保護膜の外周部上
もしくは外周部下に延在していることを特徴とする特許
請求の範囲第１項ないし第３項記載の半導体装置。 ５、前記基板周縁層が、前記半導体回路基板の少なくと
もコーナー部に位置していることを特徴とする特許請求
の範囲第１項ないし第３項記載の半導体装置。 ６、前記半導体回路基板上の配線が、層間絶縁膜を介し
て２層以上の金属配線層を有する多層配線構造であるこ
とを特徴とする特許請求の範囲第１項ないし第５項記載
の半導体装置。[Claims] 1. A substrate peripheral layer having a semiconductor element, wiring, and a surface protective film in at least a region other than the peripheral region, and the surface of the peripheral region is made of a layer of silicon, silicon oxide, or silicon nitride. In a semiconductor device in which a semiconductor circuit board having a semiconductor circuit board is sealed with a sealing resin, the adhesion between the substrate peripheral layer and the sealing resin in the peripheral region is such that the adhesiveness between the substrate peripheral layer and the sealing resin is 1. A resin-sealed semiconductor device, characterized in that an adhesive layer having an adhesiveness greater than that of the substrate is interposed between the substrate peripheral layer and the sealing resin. 2. The resin-sealed semiconductor device according to claim 1, wherein the adhesive layer is at least a film of metal, metal oxide, nitride, or silicide. 3. Claim 1 or 2, characterized in that the surface protective film is a polyimide-based polymer resin film.
The resin-sealed semiconductor device described in Section 1. 4. The semiconductor device according to any one of claims 1 to 3, wherein the adhesive layer extends at least above or below the outer periphery of the surface protection film. 5. The semiconductor device according to any one of claims 1 to 3, wherein the substrate peripheral layer is located at least at a corner portion of the semiconductor circuit board. 6. The semiconductor according to claims 1 to 5, wherein the wiring on the semiconductor circuit board has a multilayer wiring structure having two or more metal wiring layers with an interlayer insulating film interposed therebetween. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8902688A JPH01261850A (en) | 1988-04-13 | 1988-04-13 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8902688A JPH01261850A (en) | 1988-04-13 | 1988-04-13 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01261850A true JPH01261850A (en) | 1989-10-18 |
Family
ID=13959400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8902688A Pending JPH01261850A (en) | 1988-04-13 | 1988-04-13 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01261850A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661076B2 (en) * | 2000-11-29 | 2003-12-09 | Nec Electronics Corporation | Semiconductor device |
| KR100764363B1 (en) * | 2005-04-28 | 2007-10-08 | 산요덴키가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| US7830023B2 (en) | 2007-05-30 | 2010-11-09 | Denso Corporation | Resin molded semiconductor device |
| JP2014116333A (en) * | 2012-12-06 | 2014-06-26 | Mitsubishi Electric Corp | Semiconductor device |
| JP6005306B2 (en) * | 2014-04-28 | 2016-10-12 | 三菱電機株式会社 | Semiconductor device |
| WO2018194090A1 (en) * | 2017-04-20 | 2018-10-25 | ローム株式会社 | Semiconductor device |
| JP2018182330A (en) * | 2017-04-20 | 2018-11-15 | ローム株式会社 | Semiconductor device |
-
1988
- 1988-04-13 JP JP8902688A patent/JPH01261850A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661076B2 (en) * | 2000-11-29 | 2003-12-09 | Nec Electronics Corporation | Semiconductor device |
| KR100764363B1 (en) * | 2005-04-28 | 2007-10-08 | 산요덴키가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| US7830023B2 (en) | 2007-05-30 | 2010-11-09 | Denso Corporation | Resin molded semiconductor device |
| JP2014116333A (en) * | 2012-12-06 | 2014-06-26 | Mitsubishi Electric Corp | Semiconductor device |
| JP6005306B2 (en) * | 2014-04-28 | 2016-10-12 | 三菱電機株式会社 | Semiconductor device |
| US10068825B2 (en) | 2014-04-28 | 2018-09-04 | Mitsubishi Electric Corporation | Semiconductor device |
| WO2018194090A1 (en) * | 2017-04-20 | 2018-10-25 | ローム株式会社 | Semiconductor device |
| JP2018182330A (en) * | 2017-04-20 | 2018-11-15 | ローム株式会社 | Semiconductor device |
| CN110447099A (en) * | 2017-04-20 | 2019-11-12 | 罗姆股份有限公司 | Semiconductor devices |
| US11233037B2 (en) | 2017-04-20 | 2022-01-25 | Rohm Co., Ltd. | Semiconductor device |
| US11776936B2 (en) | 2017-04-20 | 2023-10-03 | Rohm Co., Ltd. | Semiconductor device |
| CN110447099B (en) * | 2017-04-20 | 2023-11-07 | 罗姆股份有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
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