JPH01258490A - Formation of printed wiring board circuit - Google Patents
Formation of printed wiring board circuitInfo
- Publication number
- JPH01258490A JPH01258490A JP8506388A JP8506388A JPH01258490A JP H01258490 A JPH01258490 A JP H01258490A JP 8506388 A JP8506388 A JP 8506388A JP 8506388 A JP8506388 A JP 8506388A JP H01258490 A JPH01258490 A JP H01258490A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- physically
- printed wiring
- face
- roughened
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 4
- 238000005530 etching Methods 0.000 claims abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000011889 copper foil Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000007788 roughening Methods 0.000 claims abstract description 5
- 238000010030 laminating Methods 0.000 claims 1
- 238000002203 pretreatment Methods 0.000 claims 1
- 239000003513 alkali Substances 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線板の回路形成法にかかわり、特に
、銅箔とエツチングレジストとの密着力を高めるのに好
適な銅箔面粗化処理に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for forming circuits on printed wiring boards, and in particular, a copper foil surface roughening treatment suitable for increasing the adhesion between the copper foil and the etching resist. Regarding.
従来、プリント配線板の回路形成工程においては、エツ
チングレジストが現像やエツチング処理に耐えられるよ
うに、ラミネート処理前に、第２図に示すごとく銅張り
積層板１をバフ２で研磨するパフ研磨や、第３図に示す
ごとく積層板１をブラシ３と研磨粉４とで研磨するスク
ラブ研磨等の物理的な銅箔面粗化処理を行っていた。し
かし、パターンの細線化に伴い、上記物理的粗化処理だ
けでは、第４図（イ）Ｋ示すエツチングレジスト５と銅
箔６との密着力が不十分となり、エツチング処理時に、
第４図（ロ）に示すような回路欠陥部８が発生しやすか
った。Conventionally, in the process of forming circuits on printed wiring boards, in order to make the etching resist resistant to development and etching, the copper-clad laminate 1 is polished with a buff 2 as shown in FIG. 2 before lamination. As shown in FIG. 3, a physical copper foil surface roughening process such as scrub polishing was performed on the laminate 1 using a brush 3 and polishing powder 4. However, with the thinning of the pattern, the adhesion between the etching resist 5 and the copper foil 6 shown in FIG.
Circuit defects 8 as shown in FIG. 4(b) were likely to occur.
密着力を向上させる従来技術としては、特公昭５７−４
１２０号公報に記載のものがある。同公報には、銅箔と
プリプレグとの密着力を向上させる方法として、銅箔表
面をエツチング液により粗化し、多層板の接着強度を高
めることが開示されている。しかし、この技術はエツチ
ングレジストとの密着力向上に関するものではなく、ま
た同公報にはアルカリエツチングに関してはなんら記載
されていない。As a conventional technique for improving adhesion, there is
There is one described in Publication No. 120. This publication discloses that as a method of improving the adhesion between copper foil and prepreg, the surface of the copper foil is roughened with an etching solution to increase the adhesive strength of the multilayer board. However, this technique does not relate to improving adhesion to etching resists, and the publication does not mention anything about alkali etching.
上記従来技術は、エツチングレジストと銅箔との密着力
が不十分であり、そのため、−々ターンの細線化に伴っ
て回路欠陥部が発生しやすく・密着力を向上させること
が課題となってぃた。In the above conventional technology, the adhesion between the etching resist and the copper foil is insufficient, and as a result, circuit defects are likely to occur as the -2 turns become thinner, and improving the adhesion is an issue. Ita.
本発明の目的は、銅箔とエツチングレジストとの密着力
をさらに向上させる方法を提供することにある。An object of the present invention is to provide a method for further improving the adhesion between copper foil and etching resist.
上記目的は、物理的に粗化した銅箔面に、さらにアルカ
リエツチング液による化学的な粗化処理を行うことによ
り、達成される。The above object is achieved by further subjecting the physically roughened surface of the copper foil to chemical roughening treatment using an alkaline etching solution.
上記構成により、アルカリエツチング液により化学的に
粗化した銅箔表面は、物理的に研磨した表面よりも凹凸
が細かいので、投錨効果が穴毎＜なり、エツチングレジ
ストとの密着力が向上する。With the above structure, the surface of the copper foil chemically roughened by the alkaline etching solution has finer irregularities than the physically polished surface, so that the anchoring effect is greater for each hole, and the adhesion to the etching resist is improved.
以下、本発明の一実施例を第７図（イ）、（ｒ：１）に
より説明する。第１図（イ）は銅張り積層板１の銅箔６
の表面を物理的に研磨して物理的研磨面９を形成した状
態を示し、（ロ）は該面をさらにアルカリエツチング液
により粗化してアルカリエツチング処理面１０を形成し
た状態を示す。An embodiment of the present invention will be described below with reference to FIGS. 7(a) and (r:1). Figure 1 (a) shows the copper foil 6 of the copper-clad laminate 1.
(b) shows a state in which the surface has been physically polished to form a physically polished surface 9, and (b) shows a state in which the surface has been further roughened with an alkaline etching solution to form an alkali-etched surface 10.
本実施例では、アルカリエツチング液として、アン毫ニ
ア濃度８．５Ｎ、塩素濃度１５５５Ｅ／Ａ、銅濃度１３
３±３１／！の組成のものを用いた。また、処理温度は
４０〜５０℃、デイラグ時間は３０〜６０秒が望ましい
。In this example, the alkaline etching solution used was an oxide concentration of 8.5N, a chlorine concentration of 1555E/A, and a copper concentration of 13N.
3±31/! A composition with the following composition was used. Further, it is desirable that the treatment temperature is 40 to 50°C and the delay time is 30 to 60 seconds.
本実施例において、アルカリエツチング液で粗化した面
１０は、物理的に粗化した面９に比べて凹凸が細かくな
るので、表面積もより大となり、エツチングレジストと
の密着力が向上する。In this embodiment, the surface 10 roughened with the alkaline etching liquid has finer irregularities than the physically roughened surface 9, so the surface area becomes larger and the adhesion to the etching resist is improved.
本発明によれば、プリント配線板の回路形成において、
銅箔表面とエツチングレジストとの密着力が向上できる
ため、エツチング時の回路形成品質が向上する。According to the present invention, in circuit formation of a printed wiring board,
Since the adhesion between the copper foil surface and the etching resist can be improved, the quality of circuit formation during etching is improved.
第１図は本発明の一実施例にかかわる銅張り積層板の銅
箔表面の状態を模式的に示した断面図、第２図および第
３図はそれぞれ従来の物理的研磨方法を示す説明図、第
４図はプリント配線板における回路欠陥発生を示す説明
図である。
符号の説明
ユ・・・銅張り積層板、２・・・パフ、３・・・ブラシ
、４・・・研磨粉、５・・・エツチングレジスト、６．
・・Ｍ箔、７・・・基材、８・・・回路欠陥部、９・・
・物理的研磨面、１０・・・アルカリエツチング処理面
。
第１０
第４図FIG. 1 is a cross-sectional view schematically showing the state of the copper foil surface of a copper-clad laminate according to an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams showing conventional physical polishing methods, respectively. , FIG. 4 is an explanatory diagram showing the occurrence of circuit defects in a printed wiring board. Explanation of symbols: Copper-clad laminate, 2, puff, 3, brush, 4, polishing powder, 5, etching resist, 6.
...M foil, 7...Base material, 8...Circuit defective part, 9...
- Physically polished surface, 10... Alkaline etching treated surface. 10 Figure 4
Claims (1)
ミネートし、エッチングを行って回路を形成するプリン
ト配線板の回路形成法において、エッチングレジストの
ラミネート前処理として、物理的に粗化した銅箔面に、
アルカリエッチング液による粗化処理を行うことを特徴
とするプリント配線板の回路形成法。1. In the circuit formation method for printed wiring boards in which a circuit pattern etching resist is laminated on the copper foil surface and etched to form a circuit, as a pre-treatment for laminating the etching resist, a physically roughened copper foil surface is
A method for forming a circuit on a printed wiring board, characterized by performing a roughening treatment using an alkaline etching solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8506388A JPH01258490A (en) | 1988-04-08 | 1988-04-08 | Formation of printed wiring board circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8506388A JPH01258490A (en) | 1988-04-08 | 1988-04-08 | Formation of printed wiring board circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01258490A true JPH01258490A (en) | 1989-10-16 |
Family
ID=13848174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8506388A Pending JPH01258490A (en) | 1988-04-08 | 1988-04-08 | Formation of printed wiring board circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01258490A (en) |
-
1988
- 1988-04-08 JP JP8506388A patent/JPH01258490A/en active Pending
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