JPH01254014A - Power amplifier - Google Patents

Power amplifier

Info

Publication number
JPH01254014A
JPH01254014A JP63082470A JP8247088A JPH01254014A JP H01254014 A JPH01254014 A JP H01254014A JP 63082470 A JP63082470 A JP 63082470A JP 8247088 A JP8247088 A JP 8247088A JP H01254014 A JPH01254014 A JP H01254014A
Authority
JP
Japan
Prior art keywords
fet
terminal
power
voltage
output impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63082470A
Other languages
Japanese (ja)
Inventor
Ikuro Ichitsubo
市坪　幾郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63082470A priority Critical patent/JPH01254014A/en
Publication of JPH01254014A publication Critical patent/JPH01254014A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)
  • Transmitters (AREA)

Abstract

PURPOSE:To reduce a peak current, to increase the fundamental wave output impedance and to improve the power addition rate by connecting an output impedance circuit across three-terminal semiconductor element groups connected in series. CONSTITUTION:The source of a 1st three-terminal semiconductor element (FET) 20 is connected to ground and a bias terminal 27 is connected to the gate via a high frequency input terminal 25 and a high frequency (RF) blocking resistor 26. A voltage -VP near a pinch-off voltage is applied to the bias terminal 27. The drain of the FET 20 is connected to the source of the 2nd FET 28, the drain is connected to a DC power terminal 21 via an RF choke 22 and connected to ground via an output impedance circuit 23 and a load 24. The gate of the FET 28 is connected to ground via a resistor 301 and to a power line via a resistor 302. Thus, the peak current is reduced, the fundamental wave output impedance is increased and the power addition efficiency is improved.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、通信機器等の出力段に用いられる電力増幅器
に係り、特に高効率化をはじめとする高性能化をした高
周波電力増幅器に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a power amplifier used in the output stage of communication equipment, etc. Regarding high frequency power amplifiers.

（従来の技術） 高周波電力増幅器の重要な性能上の課題は高効率化であ
る。増幅器の基本動作はＡ級動作であるが、高効率化の
点からＢ級、および０級が用いられてきた。Ａ級、Ｂ級
動作の理論効率（以下単に効率と言う場合はコレクタ効
率あるいはドレイン効率をさす）の限界はそれぞれ５０
％、　７８．５％である。ちなみにＢ級動作の流通角（
コレクタあるいはドレインにＲＦ（高周波）電流が流れ
る間の位相角）は１８０度であるか、Ｃ級動作では効率
を上げるため流通角を少なくしており、流通角０度の時
に理論効率１００　％か得られる。しかし利得は流通角
の減少とともに低下するので電力付加効率の上限は実際
には７０〜８０％程度に止まる。(Prior Art) An important performance issue for high-frequency power amplifiers is high efficiency. Although the basic operation of an amplifier is class A operation, class B and class 0 have been used from the standpoint of increasing efficiency. The theoretical efficiency limit for class A and class B operation (hereinafter simply referred to as efficiency refers to collector efficiency or drain efficiency) is 50 for each.
%, 78.5%. By the way, the flow angle of class B operation (
The phase angle during which RF (high frequency) current flows through the collector or drain is 180 degrees, or in class C operation, the flow angle is reduced to increase efficiency, and the theoretical efficiency is 100% when the flow angle is 0 degrees. can get. However, since the gain decreases as the flow angle decreases, the upper limit of the power added efficiency actually remains at about 70 to 80%.

高周波電力増幅器の効率をさらに高めるためにＥ級やＦ
級動作が提案されている。これらの動作はいずれも半導
体素子を高周波で作動するスイッチとして利用するもの
で、半導体素子の持つ基本的増幅機能を利用するＡ級、
Ｂ級、Ｃ級動１ヤとは概念的に異なる動作モードである
。いずれの動作ら利得が高く理論効率が１００％である
ために電力付加効率として０級より高効率である。Ｅ級
とＦ級の違いは高周波成分も含めた出力負荷のインピー
ダンス条件の差による。以下、第３図により従来のＦＥ
Ｔを用いたＦ級動作を例にスイッチングによる高効率電
力増幅器を説明する。In order to further increase the efficiency of high frequency power amplifiers,
A class action has been proposed. All of these operations use semiconductor devices as switches that operate at high frequencies;
This is a conceptually different operation mode from class B and class C operation. Since the gain from both operations is high and the theoretical efficiency is 100%, the power added efficiency is higher than class 0. The difference between class E and class F is due to the difference in the impedance conditions of the output load, including high frequency components. Below, according to Figure 3, the conventional FE
A high-efficiency power amplifier using switching will be explained using class F operation using T as an example.

第３図（ａ）で１０はソース接地のＦＥＴで、このＦＥ
Ｔｌ０のドレインにはＲＦチョーク１２を介してＤＣ電
源端子１１が接続されると共に出力インピーダンス回１
ｉＩ８１３を介して電力増幅器の負荷（５０オーム）１
４が接続される。ＰＥＴ１０のゲートはＲＦ阻止用の高
抵抗１６を介してほぼピンチオフ近傍の電圧−Ｖｐにバ
イアスされる。入力信号は端子１５に印加され、ＲＦ信
号が正の時ＦＥＴｌ０を導通、負の時非導通の状態にオ
ン、オフする。これは第３図（ｂ）に示す様な入力信号
の周期に同期したスイッチ１９を含む回路と考えられ、
スイッチ１つのオン状態においてはスイッチ１つの端子
電圧■は０となり、オフ状態においてはスイッチ１９を
流れる電流１が０となる。具体的な電流電圧波形はスイ
ッチ１９がら負荷１４側を見たインピーダンスＺ（ω）
による。In Figure 3(a), 10 is a source-grounded FET, and this FE
A DC power supply terminal 11 is connected to the drain of Tl0 via an RF choke 12, and an output impedance circuit 1 is connected to the drain of Tl0.
Power amplifier load (50 ohms) 1 via iI813
4 is connected. The gate of the PET 10 is biased to a voltage -Vp approximately near pinch-off via a high resistance 16 for RF blocking. The input signal is applied to the terminal 15, and when the RF signal is positive, the FET10 is made conductive, and when it is negative, the FET10 is turned on and off. This is considered to be a circuit including a switch 19 synchronized with the cycle of the input signal as shown in FIG. 3(b).
When one switch is in the on state, the terminal voltage (2) of one switch becomes 0, and when one switch is in the off state, the current 1 flowing through the switch 19 becomes 0. The specific current and voltage waveform is the impedance Z (ω) when looking at the load 14 side from the switch 19.
by.

ここでωは角周波数である。Here ω is the angular frequency.

今、第３図（ｃ）に示す様に流通角が１８０度、電流が
正弦波の半波波形、電圧が短形波とすれば、電流、電圧
は次の様な周波数成分に展開される。Now, as shown in Figure 3(c), if the flow angle is 180 degrees, the current is a half-sine wave waveform, and the voltage is a rectangular wave, the current and voltage are expanded into the following frequency components. .

従って、基本波に対するインピーダンス条件はとなり、
高調波に対しては の条件が要求される。なお、（１）、（２）式から電流
および電圧のピーク値Ｉ、ｖｏは増幅器のＤＣ（直流）
を流■と電圧Ｖにより次の様に定まる事がわかる。Therefore, the impedance condition for the fundamental wave is,
The following conditions are required for harmonics. Furthermore, from equations (1) and (2), the peak values I and vo of current and voltage are the DC (direct current) of the amplifier.
It can be seen that it is determined by the current (2) and the voltage V as follows.

１−Ｊ［ π Ｅ　＝　＝　　　　　　　　　　　（６）以上の事から
ＤＣ消費電電力。。、および基本波ＲＦ出力Ｐ。は となる。1-J [ π E = = (6) From the above, DC power consumption. . , and fundamental RF output P. Hato becomes.

（発明が解決しようとする課趙） しかしながら、（７）式かられかる様に出力電力はスイ
ッチ素子を流Ｉ　と電圧ＶＯの積で定まるので、所要の
高出力電力を得るには電流が電圧のいずれかを増やさね
ばならない。ところが、半導体素子の耐電圧には限度が
あり、例えば高周波ＧａＡｓ　ＦＥＴではゲート・ドレ
イン間の耐圧は２０Ｖ程度、従ってドレイン・ソース間
ではおよそ１５Ｖが限度である。そこで高出力化のため
には電流を増やす事で対処せざるを得ない。(Problem to be solved by the invention) However, as can be seen from equation (7), the output power is determined by the product of the current I through the switch element and the voltage VO, so in order to obtain the required high output power, the current Either of these must be increased. However, there is a limit to the withstand voltage of a semiconductor element; for example, in a high frequency GaAs FET, the withstand voltage between the gate and drain is about 20V, and therefore the limit between the drain and source is about 15V. Therefore, in order to achieve high output, we have no choice but to increase the current.

例えば出力３Ｗを得るには約１．３Ａのピーク電流が必
要となり、電流容量の大きいＦＥＴを用いるか、その様
な大電流容量のＦＥ、ＴがなければＦＥＴを並列接続し
等測的に電流容量を大きくする必要がある。ところが電
流容量の大きいＦＥＴは高価であり、一方ＦＥＴを並列
接続するのはＦＥＴや回路のアンバランスによるＦＥＴ
破壊の問題がある。For example, in order to obtain an output of 3 W, a peak current of about 1.3 A is required, so either use a FET with a large current capacity, or if you do not have an FE or T with such a large current capacity, connect FETs in parallel to reduce the current isometrically. It is necessary to increase the capacity. However, FETs with large current capacity are expensive, and on the other hand, connecting FETs in parallel is a problem due to unbalanced FETs and circuits.
There is a problem of destruction.

又、高出力化に伴う第２の問題点は（３）式で与えられ
る基本波出力インピーダンスが低くなる事である。先の
３Ｗ出力の場合にはＺ−１５Ωであり、高出力化ととも
にインピーダンスはさらに低下し出力負荷である５０Ω
との差が大きくなる。A second problem associated with higher output is that the fundamental wave output impedance given by equation (3) becomes lower. In the case of the above 3W output, it is Z-15Ω, and as the output increases, the impedance further decreases to 50Ω, which is the output load.
The difference between

これは整合回路の損失による効率低下の原因となるだけ
でなく、動作周波数帯域の狭帯域化や整合回路の大形化
を招く。This not only causes a reduction in efficiency due to loss in the matching circuit, but also causes the operating frequency band to become narrower and the matching circuit to become larger.

更に、従来技術の第３の問題点は利得が十分大きくない
ために電力不可効率が低下することである。今電力利得
をＧとすれば電力付加効率ηａｄｄは次のようになる。Furthermore, the third problem with the prior art is that the gain is not large enough, resulting in a decrease in power efficiency. Now, if the power gain is G, the power added efficiency ηadd is as follows.

ηａｄｄ　−（１−ニ）η　　　　　　　　　（８）Ｇ 〈ηニドレイン効率） ８００ＭＨｚ帯におけるＦ級増幅器の利得はおよそ１０
ｄＢであるので電力付加効率はトレイン効率の約９０％
となる。１００％に近い高効率増幅器ではこの効率低下
は発熱量の大幅な割合増を意味する。ηadd -(1-d)η (8)G <ηdrain efficiency) The gain of a class F amplifier in the 800MHz band is approximately 10
dB, so the power added efficiency is approximately 90% of the train efficiency.
becomes. For high efficiency amplifiers approaching 100%, this reduction in efficiency means a significant percentage increase in heat generation.

本発明は上記の事情に鑑みてなされたもので、ピークｔ
Ｋ値が少なく、また基本波出力インピーダンスが高く、
かつ電力は加力率の高い、半導体素子のスイッチング動
作による高効率の電力増幅器を提供することを目的とす
る。The present invention has been made in view of the above circumstances, and has a peak t
The K value is small and the fundamental wave output impedance is high.
Another object of the present invention is to provide a highly efficient power amplifier using a switching operation of a semiconductor element, which has a high power application rate.

［発明の課題］ （課題を解決するための手段と作用） 本発明は上記目的を達成すために、被を流制御路を直列
に共有するように直列接続された複数個の３端子半導体
素子と、この直列接続された３端子半導体素子群の両端
に直流電圧を印加する電源と、前記直列接続された３＠
子半導体素子群の一端を構成する１つの３端子半導体素
子の電流制御端子に接続された高周波入力端子と、前記
複数個の３端子半導体素子の電流制御端子に接続された
バイアス回路と、前記直列接続された３ｒＲＡ子半導体
素子群の両端間に接続された出力インピーダンス回路と
を具備することを特徴とするもので、半導体素子を直列
に接続しピーク電圧を上げて高出力化するとともに、電
力利得の向上により電力付加効率の改善をはかるもので
ある。[Problem to be solved by the invention] (Means and effects for solving the problem) In order to achieve the above-mentioned object, the present invention provides a plurality of three-terminal semiconductor devices connected in series so as to share a flow control path in series. , a power supply that applies a DC voltage to both ends of the series-connected 3-terminal semiconductor element group, and the series-connected 3@
a high frequency input terminal connected to a current control terminal of one 3-terminal semiconductor element constituting one end of the child semiconductor element group; a bias circuit connected to the current control terminal of the plurality of 3-terminal semiconductor elements; It is characterized by comprising an output impedance circuit connected between both ends of a group of connected 3rRA semiconductor elements, and the semiconductor elements are connected in series to increase the peak voltage and high output, and also to increase the power gain. The aim is to improve the power addition efficiency by increasing the

（実施例） 以下図面を参照して本発明の実施例を詳細に説明する。(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図は本発明の一実施例を示し、３ｆ）！子牛導体素
子、例えば第１のＦＥＴ２０はソースが接地される。こ
のＦＥＴ２０のゲートには高周波入力端子２５が接続さ
れると共にＲＦ阻止用の高抵抗２６を介してバイアス端
子２７に接続される。このバイアス端子２７にはほぼピ
ンチオフ近傍の電圧−■、が加えられる。前記ＦＥＴ２
０のドレインは第２のＦＥＴ２８のソースに接続され、
ドレインはＲＦチョーク２２を介してＤＣ電源端子２１
に接続されると共に、出力インピーダンス回ＦＩ１１２
３及び負荷２４を介して接地される。前記ＦＥＴ２８の
ゲートは抵抗３０１を介しアースに、又抵抗３０２を介
し電源ラインに接続される。Figure 1 shows an embodiment of the invention, 3f)! The source of the calf conductor element, for example the first FET 20, is grounded. A high frequency input terminal 25 is connected to the gate of this FET 20, and is also connected to a bias terminal 27 via a high resistance 26 for RF blocking. To this bias terminal 27, a voltage of -2, which is approximately in the vicinity of pinch-off, is applied. Said FET2
The drain of 0 is connected to the source of the second FET 28,
The drain is connected to the DC power terminal 21 via the RF choke 22.
is connected to the output impedance circuit FI112.
3 and a load 24. The gate of the FET 28 is connected to ground through a resistor 301 and to the power supply line through a resistor 302.

第１のＦＥＴ２０のゲートはピンチオフ近傍にバイアス
されており、端子２５に印加されたＲＦ入力信号により
駆動され、第１のＦＥＴ２０がスイッチングされる。入
力ＲＦ信号の負の時は第１のＦＥＴ２０はオフとなり、
第１のＦＥＴ２０のトレイン電圧、すなわち第２のＦＥ
Ｔ２８のソース電位２９は高くなる。第２のＦＥＴ２８
のゲートは、ＤＣの電′ａ電圧＋Ｅ′を抵抗３０１，３
０２により分圧して、第１のＦＥＴ２０がオフ時の時ソ
ース電位２９に対してピンチオフ以下になるようにバイ
アスされている。そのため第１のＦＥＴ２０がオフの時
第２のＦＥＴ２８もオフとなり、第１、第２のＦＥＴ２
０．２８から成るスイッチは開放となる。The gate of the first FET 20 is biased near pinch-off and is driven by the RF input signal applied to the terminal 25 to switch the first FET 20. When the input RF signal is negative, the first FET 20 is turned off,
The train voltage of the first FET 20, i.e. the second FE
The source potential 29 of T28 becomes high. Second FET28
The gate of the DC voltage 'a'+E' is connected to the resistors 301 and 301.
02, the first FET 20 is biased so as to be below pinch-off with respect to the source potential 29 when the first FET 20 is off. Therefore, when the first FET 20 is off, the second FET 28 is also off, and the first and second FET 28 are turned off.
The switch consisting of 0.28 is open.

一方、入力ＲＦ信号が正の時には第１のＦＥＴ２０はオ
ンとなり、第１のＦＥＴ２０のドレイン電圧、すなわち
第２のＦＥＴ２８のソース電位２９はほぼ０となる。こ
のため第２のＦＥＴ２８はゲートが順方向にバイアスさ
れるのでオン状態となる。すなわち第１、第２のＦＥＴ
２０，２８から成るスイッチは短絡となる。On the other hand, when the input RF signal is positive, the first FET 20 is turned on, and the drain voltage of the first FET 20, that is, the source potential 29 of the second FET 28 becomes approximately zero. Therefore, the gate of the second FET 28 is biased in the forward direction, so that the second FET 28 is turned on. That is, the first and second FETs
The switch consisting of 20 and 28 becomes a short circuit.

要するに、本実施の回路はＦＥＴの直列回路であるが、
そのスイッチング動作は従来例のＦＥＴ単体のスイッチ
ング動作と全く等価である６本実施例ではＦＥＴを直列
に２個用いているためにスイッチ両端のピーク電圧を従
来の２倍に上げる事ができ高出力１ヒが可能となる。In short, the circuit of this embodiment is a series circuit of FETs,
Its switching operation is completely equivalent to the switching operation of a single FET in the conventional example.6 Since this example uses two FETs in series, the peak voltage across the switch can be doubled compared to the conventional one, resulting in high output. 1 hit is possible.

本実施例の利点は次の通りである。The advantages of this embodiment are as follows.

＜１）’ＦＥＴの直列接続であるためにＦＥＴ間の電流
アンバランスが生ぜず安定な動作が可能となる。<1) 'Since the FETs are connected in series, there is no current imbalance between the FETs and stable operation is possible.

（２）（３）式から分かるようにピーク電圧Ｖが２倍に
なるために基本波インピーダンスＺも２倍となり、より
５０Ωに近づくので５０Ω負荷との整合が容易となる。As can be seen from equations (2) and (3), since the peak voltage V doubles, the fundamental wave impedance Z also doubles and approaches 50Ω, which facilitates matching with a 50Ω load.

この事により電力増幅器の広帯域化、整合回路の小形化
、整合回路損の低減による効率向上が可能となる。This makes it possible to widen the band of the power amplifier, downsize the matching circuit, and improve efficiency by reducing matching circuit loss.

（３）信号入力はＦＥＴ単体を駆動する電力で良いため
に電力利得が２倍に向上する。この結果電力負荷効率が
改善され、例えば前述の８００　ＭＨｚの場合には従来
の電力負荷効率の限界が９０％が９５％にまで向上し、
発熱量は半減する。例えば３Ｗ出力の増幅器では発熱量
が３００ｒｎＷから１５０ｍＷになる。(3) Since the signal input only needs to be the power to drive a single FET, the power gain is doubled. As a result, the power load efficiency is improved, and for example, in the case of the aforementioned 800 MHz, the conventional power load efficiency limit of 90% has been improved to 95%,
The amount of heat generated is halved. For example, in an amplifier with a 3W output, the amount of heat generated will be from 300rnW to 150mW.

以上述べたように本実施例によれば、小形、広帯域、高
効率の高出力電力増幅器が実現できる。As described above, according to this embodiment, a compact, wide-band, highly efficient, high-output power amplifier can be realized.

本実施例の説明ではＦＥＴを例に取ったが、バイポーラ
トランジスタやＳＩＴ等、電力増幅用の半導体を利用で
きる事は当然である。半導体素子の直列接続数も２ｆｌ
！Ｉｔ以上に増やした回路構成も可能である。第２図は
バイポーラトランジスタ３０゜３１．３２を３個直列接
続した本発、明の他の実施例で、４０はトランジスタ３
１．３２のベースバイアス抵抗である。In the explanation of this embodiment, an FET was used as an example, but it is obvious that semiconductors for power amplification such as bipolar transistors and SITs can be used. The number of semiconductor elements connected in series is also 2 fl.
! A circuit configuration with more than It is also possible. Figure 2 shows another embodiment of the present invention, in which three bipolar transistors 30°31.32 are connected in series, and 40 is the transistor 3.
The base bias resistance is 1.32.

尚、Ｅ級動作は出力側のインピーダンス整合回路の条件
が若干具なるが、本発明の基本概念はそのまま適用可能
である。Note that class E operation requires some conditions for the impedance matching circuit on the output side, but the basic concept of the present invention can be applied as is.

「発明の効果］ 以上述べたように本発明によれば、ピーク電流値が少な
く、また基本波出力インピーダンスが高く、かつ電力付
加効率の高い、半導体素子のスイッチング動作による高
効率の電力増幅器を提供することかできる６[Effects of the Invention] As described above, the present invention provides a highly efficient power amplifier using a switching operation of a semiconductor element, which has a small peak current value, a high fundamental wave output impedance, and a high power added efficiency. 6

【図面の簡単な説明】[Brief explanation of the drawing]

第１図本発明の一実施例を示す回路図、第２図は本発明
の池の実施例を示す回路図、第３図は従来の電力増幅器
を説明する為の説明図である。 ２０．２８・・・ＦＥＴ、２２・・・ＲＦチョーク、２
３・・・出力インピーダンス回路、２４・・・負荷、２
５・・・高周波入力端子、２６・・・ＲＦ阻止用の高抵
抗、３０１，３０２・・・ゲートバイアス抵抗。 出願人代理人　弁理士　鈴江武彦 ２糧（２Ｅ′ Ｖｐ 第　１　図 ■し 第２図 −■ｐ（ａ） １１″′Ｘ、・Ｅ （。）　　　　　　（Ｔ林〃辺） 第３図FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the invention, and FIG. 3 is an explanatory diagram for explaining a conventional power amplifier. 20.28...FET, 22...RF choke, 2
3... Output impedance circuit, 24... Load, 2
5... High frequency input terminal, 26... High resistance for RF blocking, 301, 302... Gate bias resistance. Applicant's representative Patent attorney Takehiko Suzue 2E' Vp Figure 1 ■ Figure 2 - ■ p (a) 11'''X,・E (.) (T Hayashi) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 被電流制御路を直列に共有するように直列接続された複
数個の３端子半導体素子と、この直列接続された３端子
半導体素子群の両端に直流電圧を印加する電源と、前記
直列接続された３端子半導体素子群の一端を構成する１
つの３端子半導体素子の電流制御端子に接続された高周
波入力端子と、前記複数個の３端子半導体素子の電流制
御端子に接続されたバイアス回路と、前記直列接続され
た３端子半導体素子群の両端間に接続された出力インピ
ーダンス回路とを具備することを特徴とする電力増幅器
。A plurality of 3-terminal semiconductor devices connected in series so as to share a current controlled path in series, a power supply that applies a DC voltage to both ends of the group of 3-terminal semiconductor devices connected in series, and 1 constituting one end of a 3-terminal semiconductor element group
a high frequency input terminal connected to the current control terminals of the three-terminal semiconductor devices; a bias circuit connected to the current control terminals of the plurality of three-terminal semiconductor devices; and both ends of the series-connected group of three-terminal semiconductor devices. A power amplifier comprising an output impedance circuit connected between the power amplifier and the output impedance circuit.
JP63082470A 1988-04-04 1988-04-04 Power amplifier Pending JPH01254014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63082470A JPH01254014A (en) 1988-04-04 1988-04-04 Power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63082470A JPH01254014A (en) 1988-04-04 1988-04-04 Power amplifier

Publications (1)

Publication Number Publication Date
JPH01254014A true JPH01254014A (en) 1989-10-11

Family

ID=13775395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63082470A Pending JPH01254014A (en) 1988-04-04 1988-04-04 Power amplifier

Country Status (1)

Country Link
JP (1) JPH01254014A (en)

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002023634A3 (en) * 2000-09-15 2002-06-20 Atheros Comm Inc Cmos transceiver having an integrated power amplifier
US7113744B1 (en) 1999-10-21 2006-09-26 Broadcom Corporation Adaptive radio transceiver with a power amplifier
JP2008504745A (en) * 2004-06-23 2008-02-14 ペレグリン セミコンダクター コーポレーション RF front-end integrated circuit
US7518451B2 (en) 2004-12-31 2009-04-14 Cree, Inc. High efficiency switch-mode power amplifier
US7860499B2 (en) 2001-10-10 2010-12-28 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
JP2011041315A (en) * 2004-06-23 2011-02-24 Peregrine Semiconductor Corp Rf front end integrated circuit
WO2012017580A1 (en) * 2010-08-03 2012-02-09 日本電気株式会社 Transmitter and method for controlling same
JP2013502847A (en) * 2009-08-19 2013-01-24 クゥアルコム・インコーポレイテッド Stack amplifier with diode base bias (stacked amplifier)
JP2013106294A (en) * 2011-11-16 2013-05-30 Toshiba Corp Power amplifier
US8729952B2 (en) 2012-08-16 2014-05-20 Triquint Semiconductor, Inc. Switching device with non-negative biasing
US8829967B2 (en) 2012-06-27 2014-09-09 Triquint Semiconductor, Inc. Body-contacted partially depleted silicon on insulator transistor
US8847672B2 (en) 2013-01-15 2014-09-30 Triquint Semiconductor, Inc. Switching device with resistive divider
US8923782B1 (en) 2013-02-20 2014-12-30 Triquint Semiconductor, Inc. Switching device with diode-biased field-effect transistor (FET)
US8977217B1 (en) 2013-02-20 2015-03-10 Triquint Semiconductor, Inc. Switching device with negative bias circuit
US8994452B2 (en) 2008-07-18 2015-03-31 Peregrine Semiconductor Corporation Low-noise high efficiency bias generation circuits and method
US9190902B2 (en) 2003-09-08 2015-11-17 Peregrine Semiconductor Corporation Low noise charge pump method and apparatus
US9203396B1 (en) 2013-02-22 2015-12-01 Triquint Semiconductor, Inc. Radio frequency switch device with source-follower
US9214932B2 (en) 2013-02-11 2015-12-15 Triquint Semiconductor, Inc. Body-biased switching device
US9264053B2 (en) 2011-01-18 2016-02-16 Peregrine Semiconductor Corporation Variable frequency charge pump
US9354654B2 (en) 2011-05-11 2016-05-31 Peregrine Semiconductor Corporation High voltage ring pump with inverter stages and voltage boosting stages
US9379698B2 (en) 2014-02-04 2016-06-28 Triquint Semiconductor, Inc. Field effect transistor switching circuit
US9419565B2 (en) 2013-03-14 2016-08-16 Peregrine Semiconductor Corporation Hot carrier injection compensation
US9608619B2 (en) 2005-07-11 2017-03-28 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9660590B2 (en) 2008-07-18 2017-05-23 Peregrine Semiconductor Corporation Low-noise high efficiency bias generation circuits and method
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10622990B2 (en) 2005-07-11 2020-04-14 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US10790390B2 (en) 2005-07-11 2020-09-29 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US10804892B2 (en) 2005-07-11 2020-10-13 Psemi Corporation Circuit and method for controlling charge injection in radio frequency switches
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US10951210B2 (en) 2007-04-26 2021-03-16 Psemi Corporation Tuning capacitance to enhance FET stack voltage withstand
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5547711A (en) * 1978-10-02 1980-04-04 Hitachi Ltd Amplifying circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5547711A (en) * 1978-10-02 1980-04-04 Hitachi Ltd Amplifying circuit

Cited By (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7113744B1 (en) 1999-10-21 2006-09-26 Broadcom Corporation Adaptive radio transceiver with a power amplifier
US8014719B2 (en) 1999-10-21 2011-09-06 Broadcom Corporation Adaptive radio transceiver with a power amplifier
US7860454B2 (en) 1999-10-21 2010-12-28 Broadcom Corporation Adaptive radio transceiver with a power amplifier
US6850117B2 (en) 2000-09-15 2005-02-01 Atheros Communications, Inc. CMOS transceiver having an integrated power amplifier
KR100823241B1 (en) * 2000-09-15 2008-04-18 애서러스 커뮤니케이션즈 인코포레이티드 A breakdown resistant transistor structure for amplifying communication signals
WO2002023634A3 (en) * 2000-09-15 2002-06-20 Atheros Comm Inc Cmos transceiver having an integrated power amplifier
US6504431B2 (en) 2000-09-15 2003-01-07 Atheros Communications, Inc. CMOS transceiver having an integrated power amplifier
US6504433B1 (en) 2000-09-15 2003-01-07 Atheros Communications, Inc. CMOS transceiver having an integrated power amplifier
US10622993B2 (en) 2001-10-10 2020-04-14 Psemi Corporation Switch circuit and method of switching radio frequency signals
US10790820B2 (en) 2001-10-10 2020-09-29 Psemi Corporation Switch circuit and method of switching radio frequency signals
US7860499B2 (en) 2001-10-10 2010-12-28 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
US10797694B2 (en) 2001-10-10 2020-10-06 Psemi Corporation Switch circuit and method of switching radio frequency signals
US9225378B2 (en) 2001-10-10 2015-12-29 Peregrine Semiconductor Corpopration Switch circuit and method of switching radio frequency signals
US10812068B2 (en) 2001-10-10 2020-10-20 Psemi Corporation Switch circuit and method of switching radio frequency signals
US10965276B2 (en) 2003-09-08 2021-03-30 Psemi Corporation Low noise charge pump method and apparatus
US9190902B2 (en) 2003-09-08 2015-11-17 Peregrine Semiconductor Corporation Low noise charge pump method and apparatus
JP2011041315A (en) * 2004-06-23 2011-02-24 Peregrine Semiconductor Corp Rf front end integrated circuit
US9680416B2 (en) 2004-06-23 2017-06-13 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US11070244B2 (en) 2004-06-23 2021-07-20 Psemi Corporation Integrated RF front end with stacked transistor switch
US9369087B2 (en) 2004-06-23 2016-06-14 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US10715200B2 (en) 2004-06-23 2020-07-14 Psemi Corporation Integrated RF front end with stacked transistor switch
US11588513B2 (en) 2004-06-23 2023-02-21 Psemi Corporation Integrated RF front end with stacked transistor switch
JP2008504745A (en) * 2004-06-23 2008-02-14 ペレグリン セミコンダクター コーポレーション RF front-end integrated circuit
JP4659826B2 (en) * 2004-06-23 2011-03-30 ペレグリン セミコンダクター コーポレーション RF front-end integrated circuit
US7518451B2 (en) 2004-12-31 2009-04-14 Cree, Inc. High efficiency switch-mode power amplifier
US10797691B1 (en) 2005-07-11 2020-10-06 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
USRE48944E1 (en) 2005-07-11 2022-02-22 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETS using an accumulated charge sink
US10818796B2 (en) 2005-07-11 2020-10-27 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US10622990B2 (en) 2005-07-11 2020-04-14 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US10804892B2 (en) 2005-07-11 2020-10-13 Psemi Corporation Circuit and method for controlling charge injection in radio frequency switches
US9608619B2 (en) 2005-07-11 2017-03-28 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US10680600B2 (en) 2005-07-11 2020-06-09 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
US10797172B2 (en) 2005-07-11 2020-10-06 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US10790390B2 (en) 2005-07-11 2020-09-29 Psemi Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US10951210B2 (en) 2007-04-26 2021-03-16 Psemi Corporation Tuning capacitance to enhance FET stack voltage withstand
US9660590B2 (en) 2008-07-18 2017-05-23 Peregrine Semiconductor Corporation Low-noise high efficiency bias generation circuits and method
US8994452B2 (en) 2008-07-18 2015-03-31 Peregrine Semiconductor Corporation Low-noise high efficiency bias generation circuits and method
JP2013502847A (en) * 2009-08-19 2013-01-24 クゥアルコム・インコーポレイテッド Stack amplifier with diode base bias (stacked amplifier)
US8847689B2 (en) 2009-08-19 2014-09-30 Qualcomm Incorporated Stacked amplifier with diode-based biasing
WO2012017580A1 (en) * 2010-08-03 2012-02-09 日本電気株式会社 Transmitter and method for controlling same
JP5725027B2 (en) * 2010-08-03 2015-05-27 日本電気株式会社 Transmitting apparatus and control method thereof
US8923436B2 (en) 2010-08-03 2014-12-30 Nec Corporation Transmitter and method for controlling same
US9413362B2 (en) 2011-01-18 2016-08-09 Peregrine Semiconductor Corporation Differential charge pump
US9264053B2 (en) 2011-01-18 2016-02-16 Peregrine Semiconductor Corporation Variable frequency charge pump
US9354654B2 (en) 2011-05-11 2016-05-31 Peregrine Semiconductor Corporation High voltage ring pump with inverter stages and voltage boosting stages
JP2013106294A (en) * 2011-11-16 2013-05-30 Toshiba Corp Power amplifier
US8829967B2 (en) 2012-06-27 2014-09-09 Triquint Semiconductor, Inc. Body-contacted partially depleted silicon on insulator transistor
US8729952B2 (en) 2012-08-16 2014-05-20 Triquint Semiconductor, Inc. Switching device with non-negative biasing
US8847672B2 (en) 2013-01-15 2014-09-30 Triquint Semiconductor, Inc. Switching device with resistive divider
US9214932B2 (en) 2013-02-11 2015-12-15 Triquint Semiconductor, Inc. Body-biased switching device
US8977217B1 (en) 2013-02-20 2015-03-10 Triquint Semiconductor, Inc. Switching device with negative bias circuit
US8923782B1 (en) 2013-02-20 2014-12-30 Triquint Semiconductor, Inc. Switching device with diode-biased field-effect transistor (FET)
US9203396B1 (en) 2013-02-22 2015-12-01 Triquint Semiconductor, Inc. Radio frequency switch device with source-follower
US9419565B2 (en) 2013-03-14 2016-08-16 Peregrine Semiconductor Corporation Hot carrier injection compensation
US9379698B2 (en) 2014-02-04 2016-06-28 Triquint Semiconductor, Inc. Field effect transistor switching circuit
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US10862473B2 (en) 2018-03-28 2020-12-08 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US11018662B2 (en) 2018-03-28 2021-05-25 Psemi Corporation AC coupling modules for bias ladders
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US11418183B2 (en) 2018-03-28 2022-08-16 Psemi Corporation AC coupling modules for bias ladders
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US11870431B2 (en) 2018-03-28 2024-01-09 Psemi Corporation AC coupling modules for bias ladders
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

Similar Documents

Publication Publication Date Title
JPH01254014A (en) Power amplifier
US7199658B2 (en) Circuits and methods for implementing power amplifiers for millimeter wave applications
US7378912B2 (en) Cascode connection circuit
Kobayashi et al. Current-mode class-D power amplifiers for high-efficiency RF applications
US6784732B2 (en) Class E/F switching power amplifiers
US6750711B2 (en) RF power amplifier stability
US7342457B2 (en) Cross-differential amplifier
US5920230A (en) HEMT-HBT cascode distributed amplifier
JPH0732335B2 (en) High frequency amplifier
JP2001111362A (en) Higher harmonic processing circuit and high power efficiency amplifier circuit using the same
JPH0794974A (en) Highly efficient amplifier circuit
JP2003502896A (en) Transistor amplifier with reduced parasitic oscillation
US7368971B2 (en) High power, high frequency switch circuits using strings of power transistors
JPH11340785A (en) Active low-pass filter
US7135931B2 (en) Negative conductance power amplifier
US4912430A (en) Current source as a microwave biasing element
JPH06232657A (en) High frequency amplifier
JP2003258567A (en) High frequency circuit
US7944304B1 (en) High efficiency millimeter wave field-effect transistor (FET) amplifier with coupled line matching network
JP2994231B2 (en) Semiconductor device
US9190962B2 (en) Reconfigurable power amplifier for improved low-power efficiency
Hoffmann et al. GaN digital outphasing PA
JP2508353B2 (en) High frequency amplifier circuit
JPH0574244B2 (en)
JPH0526827Y2 (en)