JPH01243545A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH01243545A JPH01243545A JP6953888A JP6953888A JPH01243545A JP H01243545 A JPH01243545 A JP H01243545A JP 6953888 A JP6953888 A JP 6953888A JP 6953888 A JP6953888 A JP 6953888A JP H01243545 A JPH01243545 A JP H01243545A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- polyimide film
- wiring
- oxygen
- wiring part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010949 copper Substances 0.000 claims abstract description 64
- 229920001721 polyimide Polymers 0.000 claims abstract description 55
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052802 copper Inorganic materials 0.000 claims abstract description 51
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 10
- 239000000956 alloy Substances 0.000 claims abstract description 10
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 6
- 239000008188 pellet Substances 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 3
- 239000012808 vapor phase Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 abstract description 23
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 14
- 229910052719 titanium Inorganic materials 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 6
- 229910001069 Ti alloy Inorganic materials 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000010410 layer Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 239000010953 base metal Substances 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 5
- 125000002915 carbonyl group Chemical group [*:2]C([*:1])=O 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000002845 discoloration Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GTDPSWPPOUPBNX-UHFFFAOYSA-N ac1mqpva Chemical compound CC12C(=O)OC(=O)C1(C)C1(C)C2(C)C(=O)OC1=O GTDPSWPPOUPBNX-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000004985 diamines Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002798 polar solvent Substances 0.000 description 1
- 229920005575 poly(amic acid) Polymers 0.000 description 1
- 238000007363 ring formation reaction Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 125000006158 tetracarboxylic acid group Chemical group 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ポリイミド膜と銅系配線とを備えた半導体装
置に関し、特に、銅系配線とポリイミド膜との界面にお
けるポリイミド膜の耐熱性向上に適用して有効な技術に
関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device comprising a polyimide film and a copper-based wiring, and in particular, to improving the heat resistance of the polyimide film at the interface between the copper-based wiring and the polyimide film. It relates to techniques that are effective when applied to
近年、半導体装置の高速化に伴い、半導体ペレットや基
板などに使用される配線材料には、その低容量化、低抵
抗化などを実現するために銅（ＣＵ）が使用されつつあ
る。In recent years, as semiconductor devices have become faster, copper (CU) has been increasingly used for wiring materials used in semiconductor pellets, substrates, etc. in order to achieve lower capacitance and lower resistance.
半導体装置に銅系配線が形成された従来技術としては、
例えば、特開昭５７−１５５７３７号記載の発明があり
、グイボンディング部、ワイヤポンディングパッド、ま
たワイヤボンディングに銅（Ｃｕ）が使用された構造の
半導体装置が開示されている。Conventional technology in which copper-based wiring is formed in semiconductor devices includes:
For example, there is an invention described in Japanese Patent Application Laid-Open No. 57-155737, which discloses a semiconductor device having a structure in which copper (Cu) is used for the wire bonding portion, the wire bonding pad, and the wire bonding.
また、近年、銅系配線とその絶縁膜としてポリイミド膜
とが半導体装置に使用されつつあるが、このような半導
体装置においては、銅（Ｃｕ）とポリイミド膜との界面
において、ポリイミド膜の耐熱性が劣化する問題がある
。In addition, in recent years, copper-based wiring and polyimide films are being used as their insulating films in semiconductor devices, but in such semiconductor devices, the heat resistance of the polyimide film is There is a problem of deterioration.
本発明者は、銅（Ｃｕ）とポリイミド膜との界面におけ
るポリイミド膜の耐熱性を向上させる技術について、検
討した。以下は、公知とされた技術ではないが、本発明
者によって検討された技術であり、その概要は次の通り
である。The present inventor studied a technique for improving the heat resistance of a polyimide film at the interface between copper (Cu) and a polyimide film. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.
すなわち、■銅配線を形成した後、その表面に酸素との
結合エネルギーの高いチタン（Ｔｉ）等の金属をメツキ
する。■蒸着法あるいはスパッタリング法などにより、
銅系配線を二層構造にし、二層のうち上層に、酸素との
結合エネルギーの高いチタン（Ｔ１）等の金属を形成す
る。That is, (1) After forming a copper wiring, its surface is plated with a metal such as titanium (Ti), which has a high bonding energy with oxygen. ■By vapor deposition method or sputtering method,
The copper-based wiring has a two-layer structure, and a metal such as titanium (T1), which has a high bonding energy with oxygen, is formed in the upper layer of the two layers.
すなわち、耐熱性の劣化は、ポリイミド膜の構成要素で
あるカルボニル基（Ｃ＝０基）における酸素（０）と銅
（Ｃｕ）との結合エネルギーが弱い、すなわち、該酸素
（０）と銅（Ｃｕ）との結合エネルギーよりも該酸素（
０）と炭素（Ｃ）とのそれのほうが高いため、銅とポリ
イミド膜との密着性が悪化していることによると推定さ
れる。In other words, the deterioration of heat resistance is caused by the weak bonding energy between oxygen (0) and copper (Cu) in the carbonyl group (C=0 group), which is a component of the polyimide film. The bonding energy with the oxygen (Cu)
0) and carbon (C) is higher than that of carbon (C), it is presumed that this is due to deterioration of the adhesion between the copper and the polyimide film.
そこで、上記■あるいは■のようにすれば、ポリイミド
膜を構成するカルボニル基（Ｃ＝０基）における酸素（
０）と銅系配線に形成されたチタン（Ｔｉ）とが結合し
、配線（０）とポリイミド膜との密着性が良好となり、
耐熱性が向上すると推定される。Therefore, if you do as described in ■ or ■ above, oxygen (
0) and the titanium (Ti) formed on the copper-based wiring are combined, and the adhesion between the wiring (0) and the polyimide film is good.
It is estimated that heat resistance is improved.
ところが、上記した銅（Ｃｕ）とポリイミド膜との界面
におけるポリイミド膜の耐熱性を向上させる技術には、
以下のような問題点があることを本発明者は見出した。However, the technology for improving the heat resistance of the polyimide film at the interface between copper (Cu) and the polyimide film described above has
The inventors have discovered that there are the following problems.
すなわち、前記■においては、銅配線を形成した後にチ
タン（Ｔｉ）等をメツキするため、配線の形成時間を大
幅に遅らせてしまう。さらに、配線の形成工程も増加す
るため、半導体装置の製造コストが高価となる等の問題
がある。That is, in the case (2) above, since titanium (Ti) or the like is plated after forming the copper wiring, the time for forming the wiring is significantly delayed. Furthermore, since the number of wiring formation steps is increased, there are problems such as an increase in the manufacturing cost of the semiconductor device.
また、前記■においては、銅系配線形成の時間および工
程が増加する上、しかも、銅系配線の側面においては、
銅が露出しているため、ポリイミド膜の耐熱性が劣化す
る、と考えられる。このように耐熱性の劣化した部分の
ポリイミド膜は、電極接続あるいはパッケージへの封止
などにおけるその後の熱処理に耐えることができず、変
色、さらに、変質劣化してしまう問題がある。In addition, in the above-mentioned (2), the time and process for forming copper-based wiring increases, and furthermore, in terms of copper-based wiring,
It is thought that the heat resistance of the polyimide film deteriorates because the copper is exposed. The polyimide film in the portion where the heat resistance has deteriorated in this way cannot withstand subsequent heat treatment during electrode connection or sealing into a package, causing discoloration and further deterioration in quality.
本発明は、上記問題点に着目してなされたものであり、
その目的は、ポリイミド膜と銅（Ｃｕ）との界面におい
て、ポリイミド膜の耐熱性を向上させ、信頼性の高い半
導体装置を提供することにある。The present invention has been made focusing on the above problems,
The purpose is to improve the heat resistance of the polyimide film at the interface between the polyimide film and copper (Cu), and to provide a highly reliable semiconductor device.
また、本発明の他の目的は、半導体装置の製造時間およ
び製造工程の短縮化を実現することにある。Another object of the present invention is to shorten the manufacturing time and manufacturing process of a semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、明
細書の記載および添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings.
本願において開示される発明のうち代表的なものの４ａ
要を簡単に説明すれば、次の通りである。Representative inventions 4a among the inventions disclosed in this application
A brief explanation of the main points is as follows.
すなわち、半導体ペレット、または、実装基板の少なく
とも一方に銅系配線と銅系配線を絶縁するポリイミド膜
を備えた半導体装置の銅系配線が、酸素との結合エネル
ギーの高い金属と銅との合金からなる銅系配線構造とす
る半導体装置である。In other words, the copper-based wiring of a semiconductor device that has a polyimide film insulating the copper-based wiring and the copper-based wiring on at least one of the semiconductor pellet or the mounting board is made of an alloy of copper and a metal that has a high bonding energy with oxygen. This is a semiconductor device having a copper-based wiring structure.
また、上記銅系配線が、酸素との結合エネルギーの高い
金属と銅とを同時に気相成長させて得た合金膜をパター
ンニングすることによって形成するものである。Further, the copper-based wiring is formed by patterning an alloy film obtained by simultaneous vapor phase growth of a metal having a high bonding energy with oxygen and copper.
上記した手段によれば、ポリイミド膜のカルボニル基（
Ｃ＝０基）における酸素と、銅系配線における酸素との
結合エネルギーの高い金属とが、結合するため、銅系配
線とポリイミド膜との密着性が向上する。このため、ポ
リイミド膜の本来の耐熱性が向上すると推定される。According to the above-mentioned means, the carbonyl group (
Since the oxygen in the C=0 group and the metal with high bonding energy with oxygen in the copper-based wiring bond, the adhesion between the copper-based wiring and the polyimide film is improved. Therefore, it is estimated that the inherent heat resistance of the polyimide film is improved.
また、銅系配線の形成に際し、合金膜が、酸素との結合
エネルギーの高い金属と銅とを同時に気相成長させて得
られることによって、電極配線の形成工程および形成時
間が大幅に短縮化される。In addition, when forming copper-based interconnects, the alloy film is obtained by simultaneously vapor-phase growing a metal with high bonding energy with oxygen and copper, which greatly reduces the process and time required to form electrode interconnects. Ru.
第１図は本発明の一実施例であるポリイミド膜と銅系配
線が形成された半ｒ体ペレ７）の概略部分断面図、第２
図は半導体ペレットを実装する実装基板の概略部分断面
図、第３図は本発明の一実施例である半導体装置の概略
部分断面図である。FIG. 1 is a schematic partial cross-sectional view of a semi-r body plate 7) on which a polyimide film and copper-based wiring are formed, which is an embodiment of the present invention.
The figure is a schematic partial cross-sectional view of a mounting board on which semiconductor pellets are mounted, and FIG. 3 is a schematic partial cross-sectional view of a semiconductor device that is an embodiment of the present invention.
第１図において、半導体ペレット１の所定の回路形成領
域には、ウェハプロセスの常法に従って集積回路（図示
せず）が形成されている。In FIG. 1, an integrated circuit (not shown) is formed in a predetermined circuit forming area of a semiconductor pellet 1 according to a conventional method of wafer processing.
＼
単結晶シリコン基板（以下、Ｓｉ基板という）２の上面
には、例えば二酸化ケイ素からなる５１０２ 膜３が形
成されている。\A 5102 film 3 made of, for example, silicon dioxide is formed on the upper surface of a single crystal silicon substrate (hereinafter referred to as Si substrate) 2.
５ｉＣｈ 膜３の上面において、その所定領域には、例
えば、フォトレジスト／エツチングにより、所定の形状
にパターンニングされた、例えばアルミニウムからなる
Ａｌ配線４が、形成されている。On the upper surface of the 5iCh film 3, in a predetermined region thereof, an Al wiring 4 made of, for example, aluminum and patterned into a predetermined shape by, for example, photoresist/etching is formed.
Ａｌ配線４は、Ｓ】０２膜３の上層に形成された層間絶
縁膜、ポリイミド膜５ａに被覆されている。The Al wiring 4 is covered with an interlayer insulating film, a polyimide film 5a, formed on the S]02 film 3.
このポリイミド膜５ａは、例えば、ジアミンとテトラカ
ルボン酸二無水物とを極性溶媒中で反応させ、ポリアミ
ック酸としたのち、Ａ’Ａ配°線４が形成された５１０
２膜３の上面にスピンナコートし、約２００℃で１時間
程度、次いで、約３５０℃で１時間程度の条件で閉環反
応を行うことにより形成されたものである。This polyimide film 5a is made of, for example, a polyamic acid formed by reacting a diamine and a tetracarboxylic dianhydride in a polar solvent, and then a 510 film is formed on which the A'A wiring 4 is formed.
It was formed by applying spinner coating to the upper surface of the two films 3 and carrying out a ring-closing reaction at about 200° C. for about 1 hour and then at about 350° C. for about 1 hour.
ポリイミド膜５ａの上面には、酸素（○）との結合エネ
ルギーが１７３ｋｃａｆ以上であるチタン（Ｔ１）等と
銅（Ｃｕ）との合金からなる配線６ａが、形成されてい
る。On the upper surface of the polyimide film 5a, a wiring 6a made of an alloy of titanium (T1) or copper (Cu) whose bond energy with oxygen (◯) is 173 kcaf or more is formed.
この配線６ａは、例えば高周波スパッタリング法により
、ポリイミド膜５ａの上面に、Ｍ（Ｃｕ）と、チタン（
Ｔｉ）とを同時に堆積させ合金膜を得た後、この合金膜
を所定のエツチング法によりパターンニングして形成さ
れたものである。This wiring 6a is formed by applying M (Cu) and titanium (
After obtaining an alloy film by simultaneously depositing Ti), this alloy film is patterned by a predetermined etching method.
また、ポリイミド膜５ａの所定の一部分は、フォトレジ
スト／エツチングにより、孔開けされＡ１配線４が露出
しており、この部分において、上記配線６ａとＡｌ配線
４とが電気的に接合している。Further, a predetermined portion of the polyimide film 5a is opened by photoresist/etching to expose the A1 wiring 4, and the wiring 6a and the Al wiring 4 are electrically connected to each other in this portion.
配線６ａは、ポリイミド膜５ａと同材料からなりポリイ
ミド膜５ａの上層に形成された層間絶縁膜、ポリイミド
膜５ｂにより被覆されている。The wiring 6a is made of the same material as the polyimide film 5a and is covered with an interlayer insulating film, the polyimide film 5b, formed on the polyimide film 5a.
ポリイミド膜５ｂの所定の一部分は、フォトレジスト／
エツチングにより孔開けされ、配線６ａが露出しており
、その上面には、半田と密着性のよい金嘱からなる半田
下地金属層７が形成され、さらに、半田下地金属層７の
上面には半田バンプ８が形成されている。A predetermined portion of the polyimide film 5b is coated with photoresist/
A hole is made by etching to expose the wiring 6a, and a solder base metal layer 7 made of gold that has good adhesion to solder is formed on the upper surface of the wiring 6a. Bumps 8 are formed.
一方、第２図に示すように、シリコン（Ｓｉ）からなる
実装基ｖｉ、９０所定領域には、銅（Ｃｕ）とチタン（
Ｔｉ）との合金からなる配線６ｂが形成されている。な
お、配線６ｂは、上記した配線６ａと同じ方法により形
成されている。On the other hand, as shown in FIG. 2, copper (Cu) and titanium (
A wiring 6b made of an alloy with Ti) is formed. Note that the wiring 6b is formed by the same method as the wiring 6a described above.
また、配線６ｂが形成された実装基板９の上面には、層
間絶縁膜としてポリイミド膜５Ｃが形成されている。な
お、ポリイミド膜５Ｃは、ポリイミド膜５ａと同材料で
ある。Furthermore, a polyimide film 5C is formed as an interlayer insulating film on the upper surface of the mounting board 9 on which the wiring 6b is formed. Note that the polyimide film 5C is made of the same material as the polyimide film 5a.
ポリイミド膜５Ｃの一部は、フォトレジスト／エツチン
グにより孔開けされ、配線６ｂが露出しており、その上
面には、半田と密着性のよい金属からなる半田下地金属
層１０が形成されぐさらに半田下地金属層１０の上面に
は半田バンプ１１が形成されている。A hole is made in a part of the polyimide film 5C by photoresist/etching to expose the wiring 6b, and a solder base metal layer 10 made of a metal with good adhesion to solder is formed on the upper surface of the wiring 6b. Solder bumps 11 are formed on the upper surface of base metal layer 10 .
このような実装基板９０半田バンプ１１と上記半導体ペ
レット１の半田バンプ８とが位置合わせされ、リフロー
され、電気的に接続されることで、半導体装置１２ （
第３図）が製造される。The solder bumps 11 of the mounting board 90 and the solder bumps 8 of the semiconductor pellet 1 are aligned, reflowed, and electrically connected, so that the semiconductor device 12 (
Figure 3) is manufactured.
次に本実施例の作用を説明する。Next, the operation of this embodiment will be explained.
ポリイミド膜５ａ〜５ｃにおけるカルボニル基（Ｃ＝０
基）の炭素（Ｃ）と酸素（０）との結合エネルギーは、
１７３ｋｃａｆである。Carbonyl groups (C=0
The bonding energy between carbon (C) and oxygen (0) in group) is
It is 173kcaf.
そこで、本実施例においては、酸素（０）との結合エネ
ルギーが１７３ｋｃａｌ！以上の金属であるチタン（Ｔ
ｉ）を配線に含有させる。Therefore, in this example, the bond energy with oxygen (0) is 173 kcal! Titanium (T
i) is included in the wiring.
すると、チタン（Ｔ１）とポリイミド膜５ａ〜５Ｃの酸
素（０）とが結合し、配線６ａ、６ｂとポリイミド膜５
ａ〜５ｃとの密着性が向上すると考えられる。 。Then, titanium (T1) and oxygen (0) of the polyimide films 5a to 5C combine, and the wirings 6a, 6b and the polyimide film 5
It is thought that the adhesion with a to 5c is improved. .
このため、ポリイミドの本来の耐熱性が向上すると考え
られる。Therefore, it is thought that the inherent heat resistance of polyimide is improved.
また、配線５ａ、５ｂが、チタン（Ｔｌ）と銅（Ｃｕ）
とを同時に合金にして、形成されることによって、配線
５ａ、５ｂの形成工程および形成時間が大幅に短縮化さ
れる。Further, the wirings 5a and 5b are made of titanium (Tl) and copper (Cu).
By forming an alloy at the same time, the process and time for forming the wirings 5a and 5b can be significantly shortened.
このように本実施例によれば以下の効果が得られる。As described above, according to this embodiment, the following effects can be obtained.
（１）、半導体ペレット１と、これを実装する実装基板
９とに形成された配線６ａ、６ｂが、酸素（Ｏ）との結
合エネルギーの高いチタン（Ｔ１）等の金属と銅（Ｃｕ
）との合金からるため、ポリイミド膜５ａ〜５．ｃのカ
ルボニル基（Ｃ＝０基）における酸素とチタン（Ｔｉ）
とが結合し、ポリイミド膜５ａ〜５ｃと配線５ａ、５ｂ
との密着性が向上する。したがって、ポリイミド膜５ａ
〜５ｃと配線６ａ、６ｂとの界面におけるポリイミドの
耐熱性が非常に向上する。(1) The wirings 6a and 6b formed on the semiconductor pellet 1 and the mounting board 9 on which it is mounted are made of metal such as titanium (T1), which has a high bonding energy with oxygen (O), and copper (Cu).
), the polyimide films 5a to 5. Oxygen and titanium (Ti) in the carbonyl group (C=0 group) of c
are combined, and the polyimide films 5a to 5c and the wirings 5a and 5b
Improves adhesion with. Therefore, the polyimide film 5a
The heat resistance of the polyimide at the interface between ~5c and the wirings 6a and 6b is greatly improved.
（２）、上記（１）により、半導体装１の製造において
、その後の熱処理によるポリイミド膜５ａ〜５ｃの変色
、劣化が防止され、さらに、歩留りの低下が確実に防止
される。(2) According to (1) above, in manufacturing the semiconductor device 1, discoloration and deterioration of the polyimide films 5a to 5c due to subsequent heat treatment are prevented, and furthermore, a decrease in yield is reliably prevented.
（３）、配線は、従来のように銅（Ｃｕ）を形成してか
ら酸素との結合エネルギーの高いチタン（Ｔｉ）等を蒸
着あるいはメツキするのではなく、銅（Ｃｕ）とチタン
（Ｔｉ）とを同時に気を目成長させ、形成されるため、
配線５ａ、５ｂの形成工程および形成時間が短縮される
。(3) Instead of forming copper (Cu) and then depositing or plating titanium (Ti), which has a high bonding energy with oxygen, as in the past, wiring is made using copper (Cu) and titanium (Ti). At the same time, the eyes grow and form,
The process and time for forming the wirings 5a and 5b are shortened.
（４）、上記（３）により、半導体装置の製造において
、製造コストの低下、開発期間の短縮化が実現される。(4) According to (3) above, in the manufacture of semiconductor devices, it is possible to reduce the manufacturing cost and shorten the development period.
（５）、 （１）〜（３）により信頼性の高い半導体装
置が得られる。(5), A highly reliable semiconductor device can be obtained by (1) to (3).
（６〕、実装基板９は、シリコン（Ｓｉ）からなるため
、Ｓｉ基板２との熱膨張係数が異ならず、実装基板９お
よびＳｉ基板２の変形等が確実に防止され、信頼性の高
い半導体装置が得られる。(6) Since the mounting board 9 is made of silicon (Si), the coefficient of thermal expansion is not different from that of the Si substrate 2, and deformation of the mounting board 9 and the Si substrate 2 is reliably prevented, resulting in a highly reliable semiconductor. A device is obtained.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
例えば、本実施例においては、ポリイミド膜と配線とが
、半導体ペレットと実装基板との両方に形成されている
場合について述べたが、いずれか一方に形成されている
場合であっても良い。For example, in this embodiment, a case has been described in which the polyimide film and wiring are formed on both the semiconductor pellet and the mounting board, but they may be formed on either one.
また、配線に含有される金属は、酸素との結合エネルギ
ーの高い金属であれば良く、例えばクロム（Ｃｒ）、ア
ルミニウム（ＡＩり等でモ良い。Further, the metal contained in the wiring may be any metal that has a high bonding energy with oxygen, and may be, for example, chromium (Cr), aluminum (AI, etc.).
また、実装基板は、シリコン（Ｓｉ）等に限定されず、
例えばセラミックあるいは合成樹脂などでも良い。Furthermore, the mounting board is not limited to silicon (Si), etc.
For example, ceramic or synthetic resin may be used.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、所定の集積回路が形成された半導体ペレット
と、前記半導体ペレットが実装される実装基板とからな
り、前記半導体ペレット、または、実装基板の少なくと
も一方に銅系配線と前記銅系配線を絶縁するポリイミド
絶縁膜とが形成された半導体装置であって、前記銅系配
線を酸素との結合エネルギーの高い金属と銅との合金で
構°成したことにより、銅系配線とポリイミドとの界面
において、銅系配線とポリイミドとの密着性が向上する
ため、ポリイミド膜の耐熱性が向上し、信頼性の高い半
導体装置が得られる。That is, it consists of a semiconductor pellet on which a predetermined integrated circuit is formed and a mounting board on which the semiconductor pellet is mounted, and the copper-based wiring is insulated from at least one of the semiconductor pellet or the mounting board. A semiconductor device in which a polyimide insulating film is formed, and the copper-based wiring is made of an alloy of copper and a metal with high bonding energy with oxygen, so that at the interface between the copper-based wiring and the polyimide, Since the adhesion between the copper-based wiring and the polyimide is improved, the heat resistance of the polyimide film is improved, and a highly reliable semiconductor device can be obtained.
また、配線が酸素との結合エネルギーの高い金属と銅と
を同時に気相成長させて得られる合金膜をパターンニン
グして形成されるため、配線の形成工程および時間が大
幅に短縮され、半導体装置製造における低コスト化、開
発期間の短縮化が実現される。In addition, since the wiring is formed by patterning an alloy film obtained by simultaneously vapor-growing a metal with high bonding energy with oxygen and copper, the wiring formation process and time are significantly shortened, and semiconductor devices Lower manufacturing costs and shorter development periods will be realized.
第１図はポリイミド膜と電極配線が形成された半導体ペ
レットの略部分断面図、
第２図は半導体ペレットを実装する実装基板の概略断面
図、
第３図は本発明の一実施例である半導体装置の概略部分
図である。
１・・・半導体ペレット、２・・・単結晶シリコン基板
、３・・・Ｓｉｎ、膜、４・・・Ａｌ配線、５ａ〜５ｃ
・・・ポリイミド膜、６ａ、６ｂ・・・配線（銅系配線
）、７・・・半田下地金属層、８・・・半田バンブ、９
・・・実装基板、ｌＯ・・・半田下地金属層、１１・・
・半田バンプ、１２・・・半導体装置。
代理人 弁理士 小 川 勝 男
第１図
第２図
Ｏ
第３図Fig. 1 is a schematic partial cross-sectional view of a semiconductor pellet on which a polyimide film and electrode wiring are formed, Fig. 2 is a schematic cross-sectional view of a mounting board on which the semiconductor pellet is mounted, and Fig. 3 is a semiconductor that is an embodiment of the present invention. FIG. 2 is a schematic partial diagram of the device. DESCRIPTION OF SYMBOLS 1... Semiconductor pellet, 2... Single crystal silicon substrate, 3... Sin, film, 4... Al wiring, 5a-5c
...Polyimide film, 6a, 6b... Wiring (copper-based wiring), 7... Solder base metal layer, 8... Solder bump, 9
... Mounting board, lO... Solder base metal layer, 11...
-Solder bump, 12... semiconductor device. Agent Patent Attorney Katsoo Ogawa Figure 1 Figure 2 O Figure 3
Claims (1)
記半導体ペレットが実装される実装基板とからなり、前
記半導体ペレット、または、実装基板の少なくとも一方
に銅系配線と前記銅系配線を絶縁するポリイミド膜とが
形成された半導体装置であって、前記銅系配線が酸素と
の結合エネルギーの高い金属と銅との合金からなること
を特徴とする半導体装置。 ２、銅系配線が酸素との結合エネルギー１７３ｋｃａｌ
以上を有する金属と銅との合金からなることを特徴とす
る請求項１記載の半導体装置。 ３、酸素との結合エネルギーが高い金属と、銅とを同時
に気相成長させて得た合金膜をパターンニングして、銅
系配線を形成することを特徴とする請求項１記載の半導
体装置の製造方法。[Claims] 1. Consists of a semiconductor pellet on which a predetermined integrated circuit is formed and a mounting board on which the semiconductor pellet is mounted, and at least one of the semiconductor pellet or the mounting board has a copper-based wiring and the mounting board. 1. A semiconductor device in which a polyimide film is formed to insulate a copper-based wiring, the copper-based wiring being made of an alloy of copper and a metal having high bonding energy with oxygen. 2. Copper-based wiring has a bonding energy of 173 kcal with oxygen.
2. The semiconductor device according to claim 1, wherein the semiconductor device is made of an alloy of copper and a metal having the above properties. 3. The semiconductor device according to claim 1, wherein the copper-based wiring is formed by patterning an alloy film obtained by simultaneously vapor-phase growing a metal having a high bonding energy with oxygen and copper. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6953888A JPH01243545A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6953888A JPH01243545A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01243545A true JPH01243545A (en) | 1989-09-28 |
Family
ID=13405595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6953888A Pending JPH01243545A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01243545A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013238863A (en) * | 2009-08-28 | 2013-11-28 | Samsung Display Co Ltd | Flexible display device and method of manufacturing the same |
-
1988
- 1988-03-25 JP JP6953888A patent/JPH01243545A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013238863A (en) * | 2009-08-28 | 2013-11-28 | Samsung Display Co Ltd | Flexible display device and method of manufacturing the same |
| US9623633B2 (en) | 2009-08-28 | 2017-04-18 | Samsung Display Co., Ltd. | Flexible display and method for manufacturing the same |
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