JPH01241864A - Solid-state image sensing device - Google Patents
Solid-state image sensing deviceInfo
- Publication number
- JPH01241864A JPH01241864A JP63068144A JP6814488A JPH01241864A JP H01241864 A JPH01241864 A JP H01241864A JP 63068144 A JP63068144 A JP 63068144A JP 6814488 A JP6814488 A JP 6814488A JP H01241864 A JPH01241864 A JP H01241864A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- diode
- storage diode
- pixel electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003860 storage Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000003384 imaging method Methods 0.000 claims description 9
- 238000010574 gas phase reaction Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 12
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 5
- 239000005360 phosphosilicate glass Substances 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 35
- 206010047571 Visual impairment Diseases 0.000 description 10
- 238000001444 catalytic combustion detection Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000002496 gastric effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012789 electroconductive film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 210000001525 retina Anatomy 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、信号電荷蓄積部および読み出し部が形成され
た半導体素子チップ上ｌこ光電変換部としての光４電膜
が積層された積層型固体撮像装置Ｚこ関する。Detailed Description of the Invention [Objective of the Invention] (Industrial Field of Application) The present invention provides a photovoltaic film as a photoelectric conversion section on a semiconductor element chip in which a signal charge storage section and a readout section are formed. The present invention relates to a stacked stacked solid-state imaging device Z.
（従来の技術）
従来の積層型固体撮像装置の一例を第２図１こ示す。ｐ
型Ｓｉ基板１には、？型層２からなる蓄積ダイオードが
マトリクス配列されて形成され、またこの蓄積ダイオー
ドの信号電荷を読み読み出す垂ｉＮ ＣＣＤが、各蓄積
ダイオード列に＠接して形成されている。垂＠ ＣＣＤ
は、ｎ＋型層３により形成された埋込みチャネル十（こ
ゲート絶縁膜を介して転送ゲート４１ 、４２を形成し
て構成されている。転送ゲート４１は、蓄積ダイオード
の信号電荷を垂直ＣＣＤチャネルへ転送するためのゲー
ト電極を兼ねている。６はチャネルストッパ層である。(Prior Art) An example of a conventional stacked solid-state imaging device is shown in FIG. p
Type Si substrate 1 contains ? Storage diodes made of a type layer 2 are formed in a matrix arrangement, and a vertical iN CCD for reading signal charges of the storage diodes is formed in contact with each storage diode column. Taru @ CCD
The transfer gate 41 is configured by forming a buried channel formed by an n+ type layer 3 (transfer gates 41 and 42 via a gate insulating film). The transfer gate 41 transfers the signal charge of the storage diode to the vertical CCD channel. It also serves as a gate electrode for transfer. 6 is a channel stopper layer.
このような蓄積ダイオードと垂Ｍ ＣＣＤが形成された
半導体素子チップ（ＣＣＤ走査チップ）の表面はＨＰＳ
ＧなどのＣＶＤ絶縁膜５（こより平滑化され、これにコ
ンタクト孔が開けられて各蓄積ダイオードに接続される
第１の画素電極７が前記ＣＶＴ）絶縁膜５を被う様にし
て形成されている。この第１の画累電袷７は、例えばｎ
型多結晶／リコン膜（こ、より形成されている。第１の
画素電極７が形成されたチップ表面は更ｌこＢＰＳＧ等
のＣＶＤ絶縁膜８１ζより平滑化され、これにコンタク
ト孔が開けられて第１の画素電極７１こ後続される第２
の画素ｉｌＩ極１０が形成されている。第２の画素電極
１０はＡ７やＭｏ又はＴｉなとの金網膜により形成され
ている。The surface of a semiconductor element chip (CCD scanning chip) on which such storage diodes and vertical M CCDs are formed is HPS.
A CVD insulating film 5 such as G (the first pixel electrode 7 which is smoothed and connected to each storage diode by making a contact hole therein) is formed so as to cover the CVT insulating film 5. There is. This first picture book board 7 is, for example, n
The chip surface on which the first pixel electrode 7 is formed is smoothed with a CVD insulating film 81ζ such as BPSG, and a contact hole is formed in this. The first pixel electrode 71 is followed by the second pixel electrode 71.
A pixel ilI pole 10 is formed. The second pixel electrode 10 is formed of gold retina such as A7, Mo, or Ti.
この様なＣＣＤ走査チップ上ｌこ、光°電変換部として
の光導電膜１１が積層形成されている。この例では光導
電１１ｉ！１１は、正孔阻止層である１型のアモルファ
スＳｉＣ膜１１１、光電変換を行なうｉ型水索化アモル
ファスＳｔ膜１１２および電子阻止層であるｐ型アモル
ファスＳｉＣ膜１１３の複合膜により構成している。こ
の光導電膜１１上ζこは上部電極として透明４電膜１２
が形成されてＧ）る。A photoconductive film 11 as a photoelectric conversion section is laminated on such a CCD scanning chip. In this example photoconductive 11i! 11 is composed of a composite film of a type 1 amorphous SiC film 111 which is a hole blocking layer, an i type water-wired amorphous St film 112 which performs photoelectric conversion, and a p type amorphous SiC film 113 which is an electron blocking layer. . On this photoconductive film 11, a transparent 4-electroconductive film 12 is placed as an upper electrode.
G) is formed.
この様な積層型ＣＣＤ ＠像装置−こ垂面ＣＣＤ領域上
も光電変換部として利用できるため基本的に開口率が大
きいという利点を有するが、−万、残像が大きいという
問題がある。Such a stacked CCD (image device) basically has the advantage of a large aperture ratio because the vertical CCD area can also be used as a photoelectric conversion section, but it has the problem of a large afterimage.
残像には、光４を膜に起因する光導電性残像と王ｆと素
子構造ｌと起因する容量性残像がある。先導電性残像は
光４Ｍ！膜として局在準位密度の大きいアモルファス材
料を用いる限り、ある程度宿命的なものである。−万、
容量性残像は第３図１こ示す等価回路の各容量成分ｌこ
起因している。０は光導電膜０１）の容量、Ｃ８は蓄積
ダイオード（２）の容量、Ｃｐは第１の画素電極（７）
と転送電極（４）との奇怪容量を示す。前述の容量の和
を全容量とすると胃性容量は約３０％ζこも及び極めて
大きなものである。積層型ＣＣＤは構造的にはほぼ確立
されており、残像低減には、各要因を総体的ｌこ低減す
ることが必要であるが、この内で比較的低減容易なもの
は、奇怪容ｋｒ（Ｃｐ）の低減である。これば；Ｓ檀ダ
イオードと画素電極を接続する構造−こ依っている。第
２図では第１０１！Ｉ７素電極（７）が転送電極（４）
を被う様な構造のため奇怪Ｗｉｋが大きくなっている。Afterimages include photoconductive afterimages caused by the light 4 film and capacitive afterimages caused by the element structure. The leading conductive afterimage is 4M light! As long as an amorphous material with a large localized level density is used as the film, this is a certain degree of fate. Ten thousand,
The capacitive afterimage is caused by each capacitive component of the equivalent circuit shown in FIG. 0 is the capacitance of the photoconductive film 01), C8 is the capacitance of the storage diode (2), and Cp is the first pixel electrode (7).
This shows the strange capacitance between the transfer electrode (4) and the transfer electrode (4). If the sum of the above-mentioned capacities is taken as the total capacity, the gastric capacity is approximately 30%, which is extremely large. The structure of stacked CCDs is almost established, and in order to reduce afterimages, it is necessary to reduce each factor as a whole, but among these factors, the one that is relatively easy to reduce is the strange phenomenon (kr). Cp). This depends on the structure that connects the S diode and the pixel electrode. In Figure 2, it is number 101! The I7 elementary electrode (7) is the transfer electrode (4)
The strange Wik is large because of the structure that covers it.
これを改善するために、蓄積ダイオード（２）の真上に
立柱電極を形成することが知られている。In order to improve this, it is known to form a vertical column electrode directly above the storage diode (2).
この様な構造では、転送室１給と画素電極の距離が長く
なるために胃性容量が低減される。現在のところ、立柱
電極の材料としてはポリシリコン電極が用いられている
。この方法で問題となるのは平担化の方法である。即ち
、通常この方法ではポリシリコンの立柱１！極を形成し
てから、例えば、ＢＰＳＧ膜を塗布して平担化する方法
が採られる。In such a structure, the distance between the transfer chamber 1 supply and the pixel electrode becomes long, so that the gastric capacity is reduced. At present, polysilicon electrodes are used as the material for the vertical pillar electrodes. The problem with this method is the leveling method. That is, in this method, the polysilicon pillar 1! After the electrode is formed, a method is adopted in which, for example, a BPSG film is applied and flattened.
実際問題として、ポリシリコン立柱を極の茜さとほぼ同
じ高さに平担化するのは極めて難しい。無論平滑増の篩
さの方が、ポリシリコン立柱電極よりも市いことが必須
条件であるが、その差異がありすぎるので画素電極を接
続するためのコンタクトホールを形成する場合、コンタ
クトホールの端部が急俊となり、断線する場合がある。As a practical matter, it is extremely difficult to flatten the polysilicon pillars to approximately the same height as the poles. Of course, it is an essential condition that the sieve of the smooth increase is better than that of the polysilicon vertical pillar electrode, but since the difference is too large, when forming a contact hole to connect the pixel electrode, it is necessary to There are times when the department becomes sudden and disconnected.
これは黒キズの原因となる。また端部で電界集中が起り
易すく暗電流の増加をきたす。従って可能な限り、画素
電極と立柱電極の接続は滑らかに行なう必要がある。こ
の様な改善策の一方法として機械的に研磨を行なりこと
が考えられでいる。然しなからこの様な方法では研磨精
度が悪いので、デバイスを破壊する可能性があり、有効
な方法とは言えない。この様に、いずれの場合も立柱電
極構造の電極を形成する場合、プロセス的に問題がある
。This causes black scratches. Furthermore, electric field concentration tends to occur at the edges, resulting in an increase in dark current. Therefore, it is necessary to connect the pixel electrode and the vertical column electrode as smoothly as possible. Mechanical polishing has been considered as one such improvement measure. However, such a method has poor polishing accuracy and may destroy the device, so it cannot be said to be an effective method. As described above, in either case, there are problems in terms of process when forming electrodes having a vertical column electrode structure.
（発明が解決しようとする課題）
以上の様に奇怪容量に起因する容量性残像を低減するた
めに、蓄積ダイオードと画素電極を接続する接合電極の
構造として蓄積ダイオード上Ｉこ垂直に立柱化する方法
が考えられている。然しなから、従来の方法では最初（
こ電極を立柱化してから平滑層を構成するので平和性が
悪いので、キズ。(Problem to be Solved by the Invention) As described above, in order to reduce the capacitive afterimage caused by the strange capacitance, the structure of the junction electrode that connects the storage diode and the pixel electrode is made into a column vertically above the storage diode. A method is being considered. However, in the conventional method, the first (
Since this electrode is made into a vertical pillar and then a smooth layer is formed, it is not peaceful, so there are scratches.
暗電流増加の原因となり易すい欠点を有する。It has the disadvantage of easily causing an increase in dark current.
本発明は、この様な間組を解決したす「シい立柱構造の
接続電極構造を有する積層型の固体撮像装置を提供する
ものである。The present invention provides a stacked solid-state imaging device having a connection electrode structure with a vertical pillar structure that solves this problem.
本発明では立柱電極構造として、最初−こ蓄積ダイオー
ド上ｌこ薄いｎ千ポリシリコン＊極を形成し、次にその
上（こタングステン金属を槓１＃シた２重電極構造を採
用する。タングステンは選択気相反応で形成する。この
方法ｌこ依ればコンタクトホールは垂直に形成しても良
く、また選択気相反応のため、画素１１ｔ極と滑らかｌ
こ接続することが可能で、キズ、暗電流の増加を抑える
ことができる。In the present invention, as a vertical electrode structure, a double electrode structure is adopted in which a thin polysilicon electrode is first formed on the storage diode, and then a layer of tungsten metal is placed on top of it. is formed by a selective gas phase reaction. According to this method, the contact hole can be formed vertically, and due to the selective gas phase reaction, the contact hole can be formed smoothly with the pixel 11t pole.
This connection can suppress scratches and increase in dark current.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図は一実施例ζこよる積層型ＣＣＤ撮像装置を示す
要部断面図である。第２図と対応する部分には、第３図
と同一符号を付して畦細な説明は省く。FIG. 1 is a sectional view of essential parts of a stacked CCD imaging device according to an embodiment ζ. Components corresponding to those in FIG. 2 are given the same reference numerals as in FIG. 3, and detailed description thereof will be omitted.
この実施例では、画素電極ｆ１１と、蓄積ダイオード（
２）を接続する両極αつが♂型のポリシリコン電極Ｑ３
とその上に選択気相成長法で形成された金属膜Ｉの積層
＊造となっている。具体的にはこの実施例では金属膜α
滲として、ＷＦ６ガスの還元反応を利用したＷ膜を用い
ている。Ｗ膜α４と蓄積ダイオード（３）間にポリシリ
コン電極α３を用いる理由は以下の第４図の製造工程を
参照して説明する。In this embodiment, the pixel electrode f11 and the storage diode (
2) Polysilicon electrode Q3 with one of the two poles connecting
and a metal film I formed thereon by selective vapor deposition. Specifically, in this example, the metal film α
As the effluent, a W film utilizing the reduction reaction of WF6 gas is used. The reason why the polysilicon electrode α3 is used between the W film α4 and the storage diode (3) will be explained with reference to the manufacturing process shown in FIG. 4 below.
４−ａ図は、ＣＣＤ走査チップの蓄積ダイオード部（２
）にｆ型のポリシリコン電極αＪを約０５μｍ程、所定
の形状に形成する。４−ｂ図は平担化層（８）としてＥ
ＰＳＧ （ボロンフォスホシリケートガラス〕を約３μ
ｍ程堆積してメルトフローを行って平担化し、次に接続
電極を形成するために、反応性イオンエツチングによっ
てコンタクトホールを形成した図を示す。このときｎ型
ポリシリコン電極圓は、反応性イオンエツチングによる
イオンダメージを緩和させる役目を果たす。ｎ生型ポリ
シリコン０３がない場合は、直接に蓄積ダイオード（２
）にダメージを与えるので、後で接続電極ａ９１こ助成
した場合暗電流成分の増加させる現象が起こる。従って
ｎ＋ポリシリコン電極α謙は、暗電流成分の抑制に必要
な緩和電極である。Figure 4-a shows the storage diode section (2) of the CCD scanning chip.
), an f-type polysilicon electrode αJ is formed in a predetermined shape with a thickness of about 0.5 μm. Figure 4-b shows E as a flattening layer (8).
Approximately 3μ of PSG (boron phosphosilicate glass)
The figure shows a case in which a layer of about 100 m thick was deposited, flattened by melt flow, and then a contact hole was formed by reactive ion etching to form a connection electrode. At this time, the n-type polysilicon electrode circle serves to alleviate ion damage caused by reactive ion etching. If n-type polysilicon 03 is not available, directly connect the storage diode (2
), so if the connection electrode a91 is later supported, a phenomenon will occur in which the dark current component increases. Therefore, the n+ polysilicon electrode α is a relaxation electrode necessary for suppressing the dark current component.
４−ａ図はｎ＋ポリシリコン電極上に選択気相成長法で
Ｗ膜α（を成長させた図を示す。Ｗ膜の選択気相成長は
ＷＦ とＡｒの混合ガスを用い、♂ポリシリコン電極
（２）上に選択的に堆積する。堆積条件は、全圧力０．
１ ｔｏｒｒ 、基板温度４５０℃とした。このとき、
次式の反応によってＷ膜は多結晶シリコン膜上にのみ成
長する。Figure 4-a shows a W film α grown on an n+ polysilicon electrode by selective vapor phase epitaxy.The selective vapor phase growth of the W film uses a mixed gas of WF and Ar. (2) selectively deposited on top.Deposition conditions were total pressure 0.
1 torr and a substrate temperature of 450°C. At this time,
The W film grows only on the polycrystalline silicon film by the following reaction.
ＷＦ６（ｇＪ＋ （３／ ２ ） Ｓ １（ｓ）−＋Ｗ
（ｓ）＋ （３／２ ）Ｓ ｉＦ’、 （ｇ）こ
こで括弧内のｇ ｒ ｓはそれぞれ気相、固相状態を示
す。ｉ料ガスとしてＷＦ −Ａｒの組合せを用いるの
は、堆積条件を変えても、ＢＰＳＧ膜（８）上（こＷ膜
が堆積することがないためである。WF6(gJ+ (3/2) S 1(s)-+W
(s)+(3/2)S iF', (g) where gr s in parentheses indicate gas phase and solid phase states, respectively. The reason why the combination of WF and Ar is used as the I source gas is that no W film is deposited on the BPSG film (8) even if the deposition conditions are changed.
ＷＦ６＋Ｈ！を原料ガスとするＷ膜成長は、ＷＦ６濃度
が高くなると選択性が破れ、絶縁膜上にもＷ膜が堆積さ
れるので、本発明ではＷＦ ＋Ａｒを用いることか好
ましい。このときＷ膜の比抵抗は約１００ｍと、バルク
とほぼ等しくなる。またＷ膜■の多結晶シリコン膜α３
とのコンタクト抵抗も非常に小さい。WF6+H! In the case of W film growth using WF 2 as a raw material gas, the selectivity is broken when the WF6 concentration becomes high, and the W film is also deposited on the insulating film. Therefore, in the present invention, it is preferable to use WF + Ar. At this time, the specific resistance of the W film is approximately 100 m, which is approximately equal to that of the bulk. In addition, the polycrystalline silicon film α3 of the W film ■
The contact resistance is also very small.
この選択気相反応を用いれば、Ｗ膜Ｑ４１はＢＰＳＧ膜
（８）のコンタクトホールを完全に平担化して埋めるこ
とか可能で、従来例のごとくコンタクトホール端で急使
な段差が出来ないため、キズ及び暗電流の増加を防ぐこ
とができる。By using this selective gas phase reaction, the W film Q41 can completely flatten and fill the contact hole of the BPSG film (8), and unlike the conventional example, there is no sudden step at the edge of the contact hole. , scratches and an increase in dark current can be prevented.
４−ｄ図及び４−ｅ図は第２図の従来例と同様な工程で
、画素電極α１及び光４電膜αυ、透明４′＃Ｌ膜ａＺ
の形成を経て本発明の撮像装置を得る。4-d and 4-e show the same process as the conventional example shown in FIG.
The imaging device of the present invention is obtained through the formation of.
さて、この様にして得られた撮像装置では、奇怪容ｆＣ
ｐの値として従来例では１画素当り０．００２ＰＦだっ
たものが、０．０００８ＰＦと減した。この結果信号を
流２００ ｎＡで３フイール目の容量性に伴なう残像他
成分は、従来１％であったものが０７％まを有する積層
型ＣＯＤは従来例に見られた様なキズ又は暗電流の増加
を抑えることが可能であるとともに容性容量に伴なう残
像成分の低減に有効である。Now, with the imaging device obtained in this way, the strange image fC
The value of p was 0.002PF per pixel in the conventional example, but it was reduced to 0.0008PF. As a result, when the signal current is 200 nA, the afterimage and other components associated with the capacitance of the 3rd film were 1% in the past, but the multilayer COD, which has up to 0.7%, is free from scratches and other components like those seen in the conventional example. It is possible to suppress an increase in dark current and is effective in reducing afterimage components associated with capacitance.
第１図は本発明の図、第２図は従来例を示す図、第３図
は積層型ＣＯＤの等価回路を示す図、第４図は木兄Ｆｉ
Ａ構造のＦｆｔ層ｆｆｉ Ｃ’ＣＤを形成する際の要素
工程図を示す図である。
２・・蓄積ダイオード、１０ ・画素電極、１５・・・
接続電極、１３・・ｎポリシリコン電極、１４・・タン
グステン金属、Ｃａ −ｊＹ−導電膜、Ｃｓ・・蓄積容
量、ｃｐ ・転送電極ＣＦ”ＳＧ）と画素電極間の奇怪
容量、ＩＴＤ・・透明２４電膜。Fig. 1 is a diagram of the present invention, Fig. 2 is a diagram showing a conventional example, Fig. 3 is a diagram showing an equivalent circuit of a stacked COD, and Fig. 4 is a diagram of the Kinoi Fi
FIG. 6 is a diagram showing an element process diagram when forming an Fft layer ffi C'CD of A structure. 2... Storage diode, 10 - Pixel electrode, 15...
Connection electrode, 13...n polysilicon electrode, 14...tungsten metal, Ca-jY-conductive film, Cs...storage capacitance, cp, bizarre capacitance between transfer electrode CF"SG) and pixel electrode, ITD...transparent 24 electric membrane.
Claims (2)
おいて、光導電膜が積層される画素電極と走査素子の蓄
積ダイオードを電気的に接続する接続電極の構造か、蓄
積ダイオード上垂直に配置され且つ接続電極の構成か蓄
積ダイオード側よりｎ＾＋ポリシリコン電極と金属電極
の２重構成になっていることを特徴とする固体撮像装置
。(1) In a solid-state imaging device in which a photoconductive film is laminated on a scanning element, the structure of the connecting electrode that electrically connects the pixel electrode on which the photoconductive film is laminated and the storage diode of the scanning element is vertically placed on the storage diode. What is claimed is: 1. A solid-state imaging device characterized in that the connection electrode has a double structure of an n^+ polysilicon electrode and a metal electrode from the storage diode side.
れたタングステンであることを特徴とする請求項１記載
の固体撮像装置。(2) The solid-state imaging device according to claim 1, wherein the metal electrode is tungsten formed by selective gas phase reaction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068144A JPH01241864A (en) | 1988-03-24 | 1988-03-24 | Solid-state image sensing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068144A JPH01241864A (en) | 1988-03-24 | 1988-03-24 | Solid-state image sensing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01241864A true JPH01241864A (en) | 1989-09-26 |
Family
ID=13365255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63068144A Pending JPH01241864A (en) | 1988-03-24 | 1988-03-24 | Solid-state image sensing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01241864A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2012176390A1 (en) * | 2011-06-23 | 2015-02-23 | パナソニック株式会社 | Solid-state imaging device |
-
1988
- 1988-03-24 JP JP63068144A patent/JPH01241864A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2012176390A1 (en) * | 2011-06-23 | 2015-02-23 | パナソニック株式会社 | Solid-state imaging device |
| US9768226B2 (en) | 2011-06-23 | 2017-09-19 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device |
| US10084008B2 (en) | 2011-06-23 | 2018-09-25 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device |
| US10553639B2 (en) | 2011-06-23 | 2020-02-04 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device |
| US10879301B2 (en) | 2011-06-23 | 2020-12-29 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3031756B2 (en) | Photoelectric conversion device | |
| JPS63244879A (en) | Solid-state image sensing device | |
| JPH01241864A (en) | Solid-state image sensing device | |
| US7279729B2 (en) | Photodetector array | |
| JPH10154805A (en) | Solid-state imaging element and manufacture thereof | |
| JP2525780B2 (en) | Stacked solid-state imaging device | |
| JPH03270177A (en) | Semiconductor photodetection device and its manufacture | |
| JPS6322074B2 (en) | ||
| JPH04343472A (en) | Solid-state image pickup element | |
| JP2509592B2 (en) | Stacked solid-state imaging device | |
| JPH0669483A (en) | Picture element of solid-state image pickup and its operation and production | |
| US20230225139A1 (en) | Image sensor and manufacturing method thereof | |
| US20220165895A1 (en) | Image sensor and manufacturing method thereof | |
| JPS6320384B2 (en) | ||
| JPS61182240A (en) | Manufacture of semiconductor device | |
| JPS63275170A (en) | Manufacture of solid image pick-up device | |
| JPS631067A (en) | Charge coupled device | |
| JPS6392056A (en) | Manufacture of solid-state image sensor | |
| JPS589363A (en) | Solid state image pickup element | |
| JPS61129858A (en) | Semiconductor device | |
| JPH0548067A (en) | Solid-state image sensing element | |
| JPS639147A (en) | Laminated solid-state image pickup device | |
| JPH03171769A (en) | Solid state image sensing device and manufacture thereof | |
| JPS60167366A (en) | Manufacture of solid-state image pickup device | |
| JPS581597B2 (en) | Kotai Satsuzou Sochi |