JPH01241622A - Multiplying device - Google Patents
Multiplying deviceInfo
- Publication number
- JPH01241622A JPH01241622A JP63070016A JP7001688A JPH01241622A JP H01241622 A JPH01241622 A JP H01241622A JP 63070016 A JP63070016 A JP 63070016A JP 7001688 A JP7001688 A JP 7001688A JP H01241622 A JPH01241622 A JP H01241622A
- Authority
- JP
- Japan
- Prior art keywords
- partial product
- register
- input
- multiplier
- input adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009825 accumulation Methods 0.000 claims description 4
- 230000001186 cumulative effect Effects 0.000 abstract description 17
- 238000010586 diagram Methods 0.000 description 10
- 238000004364 calculation method Methods 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は符号付きの乗算を行う乗算装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplication device that performs signed multiplication.
従来の技術
従来の乗算回路としては、例えば［インブルーブト ア
プローチ トウ ザ ユーズ オプ プＩし〒ス マル
チプリケージ苫ン アルゴリズム」アイ・ビー・エム
テクニカル ディスクロジャブレティン ２７巻１１号
１９８６年４月（”Ｉｍｐｒｏｖｅｄ ａｐｐｒｏａｃ
ｈ ｔｏ ｔｈｅ ｕｓｅ ｏｆ Ｂｏｏｔｈ’ｓｍｕ
ｌｔｉｐｌｉｃａｔｉｏｎ ａｌｇｏｒｉｔｈｍ”、Ｉ
ＢＭ ＴｅｃｈｎｉｃａｌＤｉｓｃｌｏｓｕｒｅ Ｂｕ
ｌｌｅｔｉｎ Ｖｏｌ、２７４１１ Ａｐｒｉ１１９８
５）に示されている。Conventional technology Conventional multiplication circuits include, for example, the ``In Blueprint Approach to the Use of Optional Algorithms'' published by IBM.
Technical Disclosure Bulletin Volume 27, No. 11, April 1986
h to the use of Booth'smu
ltiplication algorithm”, I
BM Technical Disclosure Bu
lletin Vol, 27411 Apri1198
5).
第６図はこの従来の乗算回路のブロック図を示すもので
あり、１は被乗数レジスタ、３は乗数レジスタ、１１は
累算された部分積の上位を保持する上位積レジスタ、１
゛２は下位積レジスタ、１３は演算回路、１４は演算と
演算回路のＢ入力を制御する演算制御回路、４は乗数２
ビツト右シフトする乗数シック、１４は演算回路の出力
を２ビツト右シフトする上位累算部分積シフタ、１５は
上位累算部分積シフタ１４の桁あふれを左からキャリ入
力して下位積レジスタ１２を２ビツト右シフトする下位
累算部分積シフタ、６は乗数シフタ４の桁あふれを保持
するキャリフラグ、１６は披乗数の２倍値を得るための
２倍回路、１７は選択回路である。FIG. 6 shows a block diagram of this conventional multiplication circuit, in which 1 is a multiplicand register, 3 is a multiplier register, 11 is an upper product register that holds the upper part of the accumulated partial product, and 1 is a multiplier register.
2 is a lower product register, 13 is an arithmetic circuit, 14 is an arithmetic control circuit that controls the arithmetic operation and the B input of the arithmetic circuit, and 4 is a multiplier 2.
14 is an upper cumulative partial product shifter that shifts the output of the arithmetic circuit to the right by 2 bits; 15 is a carry input of the overflow of the upper cumulative partial product shifter 14 from the left to input the lower product register 12. A lower cumulative partial product shifter for right-shifting by 2 bits, 6 a carry flag for holding overflow of the multiplier shifter 4, 16 a doubling circuit for obtaining the double value of the multiplier, and 17 a selection circuit.
以上のように構成された従来の乗算回路について、以下
にその動作を説明する。The operation of the conventional multiplication circuit configured as described above will be described below.
始めに、被乗数ならびに乗数をそれぞれ被乗数レジスタ
１と乗数レジスタ３に入力するとともに、上位積レジス
タ１１と下位積レジスタ１２およびキャリフラグ６を零
にクリアする。First, a multiplicand and a multiplier are input into multiplicand register 1 and multiplier register 3, respectively, and upper product register 11, lower product register 12, and carry flag 6 are cleared to zero.
演算回路１３の演算およびＢ入力は乗数レジスタ３の下
位２ビツトとキャリアラグ５とから決定され、演算回路
１３の出力は第４図において演算の欄がＡ”ならば八入
力をそのｔｔ、”Ａ−１−Ｂ”ならば八入力とＢ入力の
加算結果、’Ａ−Ｂ”ならば八入力からＢ入力の減算結
果となる。またＢ入力は選択回路１７において６×”な
らば被乗数レジスタ１が、２×”ならば２倍回路１６の
出力が選択される。演算後、乗数シフタ４、上位累算部
分積シフタ１４および下位累算部分積シフタ１６はいず
れも右に算術シフトし、それぞれ所定のレジスタにシフ
ト結果を格納する。The calculation and B input of the calculation circuit 13 are determined from the lower two bits of the multiplier register 3 and the carrier lag 5, and the output of the calculation circuit 13 is 8 inputs if the calculation column is A" in FIG. If it is "A-1-B", it will be the result of addition of 8 inputs and B input, and if it is 'A-B', it will be the result of subtraction of B input from 8 inputs. Further, for the B input, the selection circuit 17 selects the multiplicand register 1 if it is 6×'', and selects the output of the doubling circuit 16 if it is 2×”. After the calculation, the multiplier shifter 4, the upper cumulative partial product shifter 14, and the lower cumulative partial product shifter 16 all perform an arithmetic shift to the right, and store the shift results in respective predetermined registers.
以上の演算およびシフトは、乗数が偶数ビット長のとき
は乗数のビット長÷２回、乗数が奇数ビット長のときは
（乗数のビット長＋１）÷２回繰り返される。The above operations and shifts are repeated twice when the multiplier has an even bit length, and (multiplier bit length+1)÷2 times when the multiplier has an odd bit length.
乗算結果は上位積レジスタ１１と下位積レジスタ１２に
上位と下位に別れて保持される。The multiplication results are held in an upper product register 11 and a lower product register 12 separately into upper and lower parts.
また、全部分積を求めて加算する乗算器は例えば’ＬＳ
Ｉ化が進む並列演算方式による乗算器の回路方式を見る
”日経ニレ１９７８ 、５ 、２９Ｐ、７６ に示され
る。Also, a multiplier that calculates and adds total partial products is, for example, 'LS
A look at multiplier circuit systems based on the parallel operation system, which is becoming more and more integrated," Nikkei Nire 1978, 5, 29P, 76.
発明が解決しようとする課題
しかしながら上記のような構成では、部分積が１つしか
生成されないため、ｎビットの乗数を２ビツトのブース
（Ｂｏｏｔｈ）のアルゴリズムで処理する場合ｎ／２
サイクル必要であるという問題点を有していた。Problems to be Solved by the Invention However, in the above configuration, only one partial product is generated, so when an n-bit multiplier is processed by a 2-bit Booth algorithm, n/2
This method had the problem of requiring cycles.
また、全部分積を求めて累算する乗算器では非常に多く
のハードウェアを必要とするという課題を有していた。Another problem is that a multiplier that calculates and accumulates total partial products requires a large amount of hardware.
本発明はかかる点に濫み、少ないハードウェアの増加で
２つの部分積を同時に生成し、３入力加算器を用いて累
算処理を行う高速乗算装置を提供することを目的とする
。SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed multiplication device that simultaneously generates two partial products with a small increase in hardware and performs accumulation processing using a three-input adder.
課題を解決するための手段
本発明は累算処理に用いる３入力加算器と、前記３入力
加算器の出力を保持し再び前記３入力加算器に入力する
累算部分積レジスタと、被乗数から上位部分積を生成し
前記３入力加算器に入力する上位部分積生成回路と、被
乗数から下位部分積を生成し前記３入力加算器に入力す
る下位部分積生成回路と、乗数から前記上位部分積生成
回路と前記上位部分積生成回路を制御する生成回路とを
備えた乗算装置である。Means for Solving the Problems The present invention provides a 3-input adder used for accumulation processing, an accumulated partial product register that holds the output of the 3-input adder and inputs it again to the 3-input adder, and a an upper partial product generation circuit that generates a partial product and inputs it to the 3-input adder; a lower partial product generation circuit that generates a lower partial product from the multiplicand and inputs it to the 3-input adder; and a lower partial product generation circuit that generates the upper partial product from the multiplier. A multiplication device includes a circuit and a generation circuit that controls the upper partial product generation circuit.
作 用
本発明は前記した構成により、２つの部分積を同時に生
成し、３入力加算器で累算部分積を求めるため、１サイ
クルで２倍の処理ができ、高速乗算が可能となる。Effects According to the present invention, with the above-described configuration, two partial products are generated simultaneously and the cumulative partial product is determined by a three-input adder, so that double processing can be performed in one cycle, and high-speed multiplication is possible.
実施例
第１図は本発明の実施例における乗算装置のブロック図
を示すものである。１は乗算開始時に被乗数を入力し、
演算処理中は左に４ビツトずつシフトされた被乗数を保
持する被乗数レジスタ、２は被乗数レジスタ１に保持さ
れた数値を左に４ビツトシフトする被乗数シフタ、３は
乗算開始時に乗数を入力して演算処理中は４ビツトずつ
右シフトされた乗数が保持される乗数レジスタ、４は乗
数レジスタ３に保持された数値を４ビツト右シフトする
乗数シフタ、６は乗数レジスタ３に保持された数値を右
シフトしたときの桁あぶれを保持するキャリアラグ、７
は被乗数レジスタ１に保持された数値Ｘから±４Ｘ、±
８ｘを出力する上位部分積生成回路、８は被乗数レジス
タ１に保持された数値Ｘから±Ｘ、±２ｘを出力する下
位部分積生成回路、６は乗数レジスタ３の下位４ビツト
とキャリフラグ６を入力し、上位部分積生成回路７と下
位部分積生成回路８を制御する制御回路、９は演算処理
中は累算された部分積を保持する累算部分積レジスタ、
１０は上位部分積生成回路７の出力と下位部分積生成回
路８の出力と累算部分積レジスタ９に保持された数値を
入力し３入力の加算を行い、結果を累算部分積レジスタ
９に格納する３入力加算器である。また、第３図は上位
部分積生成回路７及び下位部分積生成回路８の詳細図を
、第４図は３入力加算器１ｏの詳細図を示すものである
。Embodiment FIG. 1 shows a block diagram of a multiplication device in an embodiment of the present invention. 1 inputs the multiplicand at the start of multiplication,
During arithmetic processing, the multiplicand register holds the multiplicand shifted 4 bits to the left. 2 is a multiplicand shifter that shifts the value held in multiplicand register 1 by 4 bits to the left. 3 inputs the multiplier at the start of multiplication and performs arithmetic processing. Inside is a multiplier register that holds the multiplier shifted to the right by 4 bits, 4 is a multiplier shifter that shifts the number held in multiplier register 3 to the right by 4 bits, and 6 is a multiplier shifter that shifts the number held in multiplier register 3 to the right. Carrier lugs that keep the digits out of order, 7
is ±4X from the numerical value X held in multiplicand register 1, ±
8 is a lower partial product generation circuit that outputs ±X, ±2x from the numerical value X held in multiplicand register 1, 6 is a circuit that outputs the lower 4 bits of multiplier register 3 and carry flag 6. a control circuit that inputs the input and controls the upper partial product generation circuit 7 and the lower partial product generation circuit 8; 9 is an accumulated partial product register that holds the accumulated partial products during arithmetic processing;
10 inputs the output of the upper partial product generation circuit 7, the output of the lower partial product generation circuit 8, and the numerical value held in the cumulative partial product register 9, performs addition of the three inputs, and stores the result in the cumulative partial product register 9. This is a 3-input adder that stores data. Further, FIG. 3 shows a detailed diagram of the upper partial product generating circuit 7 and the lower partial product generating circuit 8, and FIG. 4 shows a detailed diagram of the three-input adder 1o.
以上のように構成された本実施例の乗算回路について、
以下にその動作を説明する。Regarding the multiplication circuit of this embodiment configured as above,
The operation will be explained below.
まず、累算部分積レジスタ９にゼロを、被乗数レジスタ
１に被乗数を、乗数レジスタ３に乗数をそれぞれ格納す
る。被乗数レジスタ１に保持されている数値をｘ（！。First, zero is stored in the cumulative partial product register 9, a multiplicand is stored in the multiplicand register 1, and a multiplier is stored in the multiplier register 3, respectively. The value held in multiplicand register 1 is x(!.
、ｘｌ、・・・・・・ｘｎ−４）、乗数レジスタ３に保
持されている数値をＹ （ｙ□ ＋ ７１ ＋・・・・
・・ｙｎｌ）とする。,xl,...xn-4), and the numerical value held in multiplier register 3 as Y (y□ + 71 +...
...ynl).
本実施例では２ビツトのブースのアルゴリズムに基づい
て説明する。This embodiment will be explained based on a 2-bit Booth algorithm.
Ｏ）乗数レジスタ３の下位４ビツト（Ｖ ｎ４ ＋７ｎ
−３＋７ｎ−２ｊ’ｎ−１）とＣ（キャリフラグ）を制
御回路６に入力し、上位部分積生成回路７゜下位部分積
生成回路８を制御する。下位部分積生成回路７と下位部
分積生成回路８では、第２図に示すデータを出力する。O) Lower 4 bits of multiplier register 3 (V n4 +7n
-3+7n-2j'n-1) and C (carry flag) are input to the control circuit 6 to control the upper partial product generation circuit 7 and the lower partial product generation circuit 8. The lower partial product generation circuit 7 and the lower partial product generation circuit 8 output the data shown in FIG.
（２３入力加算器１ｏにおいて、上位部分積生成回路７
．下位部分積生成回路８の出力及び累算部分積レジスタ
９に保持されている数値の間で加算を行い、結果を累算
部分積レジスタ９に格納する。一方、被乗数レジスタ１
は被乗数シフタ２で左に４ピツトシフトして再び被乗数
レジスタ１に格納される。また、乗数レジスタ３は乗数
シフタ４で右に４ビツトシフトされ、再び乗算レジスタ
３に格納される。(In the 23-input adder 1o, the upper partial product generation circuit 7
．． Addition is performed between the output of the lower partial product generation circuit 8 and the numerical value held in the cumulative partial product register 9, and the result is stored in the cumulative partial product register 9. On the other hand, multiplicand register 1
is shifted 4 pits to the left by multiplicand shifter 2 and stored in multiplicand register 1 again. Further, the multiplier register 3 is shifted to the right by 4 bits by the multiplier shifter 4, and then stored in the multiplier register 3 again.
（１）（２）の操作をｎビットの乗数の場合ｎ／４ サ
イクル繰り返すことにより乗算結果が累算部分積レジス
タ９に保持されることになる。By repeating operations (1) and (2) for n/4 cycles in the case of an n-bit multiplier, the multiplication result is held in the cumulative partial product register 9.
ここで、第３図に示すように上位部分積生成回路７は左
２又は３ビツトシフタと２の補数生成回路、下位部分積
生成回路８は左０又は１ピツトノフタと２の補数生成回
路を用いて構成することができる。また、第４図に示す
ように、３入力加算器は２入力加算器にＣ３Ａを付加す
るだけで実現することができる。Here, as shown in FIG. 3, the upper partial product generation circuit 7 uses a left 2 or 3 bit shifter and a 2's complement generation circuit, and the lower partial product generation circuit 8 uses a left 0 or 1 pit shifter and a 2's complement generation circuit. Can be configured. Further, as shown in FIG. 4, a three-input adder can be realized by simply adding C3A to a two-input adder.
以上のように、本実施例によれば、少ないハードウェア
の増加で乗数の下位４ピツトとキャリフラグから上位部
分積と下位部分積を生成し３入力加算器で演算するとい
う構成により、ｎビットの乗数の場合ｎ／４ サイクル
で実行できる。As described above, according to the present embodiment, with a configuration in which the upper partial product and the lower partial product are generated from the lower 4 pits of the multiplier and the carry flag and are operated by the 3-input adder with a small increase in hardware, n-bit For a multiplier of , it can be executed in n/4 cycles.
なお、この実施例においてはブースのアルゴリズムを用
いたが、本発明はブースのアルゴリズム以外の方法でも
実現することが可能であることは言うまでもなく、通常
の２倍の速度で乗算を実行することができる。Although Booth's algorithm was used in this embodiment, it goes without saying that the present invention can be implemented using methods other than Booth's algorithm, and multiplication can be performed at twice the normal speed. can.
発明の詳細
な説明したように、本発明によれば乗算器のような大き
なハードウェアを用いることなく、従来の乗算回路に対
して少ないハードウェアの増加で、従来の乗算処理時間
の半分の処理時間で乗算が実行でき、その実用的効果は
大きい。As described in detail, according to the present invention, without using large hardware such as a multiplier, with a small increase in hardware compared to a conventional multiplication circuit, the processing time can be reduced by half of the conventional multiplication processing time. Multiplication can be performed in time, and its practical effects are great.
第１図は本発明の一実施例の乗算装置のブロック図、第
２図は同実施例における制御回路の制御テーブル図、第
３図は同実施例における上位部分積生成回路および下位
部分積生成回路８の詳細な構成を示すブロック図、第４
図は同実施例における３入力加算器の詳細な構成を示す
回路図、第６図は従来の乗算装置のブロック図、第６図
は同装置の演算制御回路の制御テーブル図である。
１・・・・・・被乗数レジスタ、２・・・・・・被乗数
シフト、３・・・・・・乗数レジスタ、４・・・・・・
乗数シフタ、６・・・・・・キャリフラグ、６・・・・
・・制御回路、７・・・・・・上位部分積生成回路、８
・・・・・・下位部分積生成回路、９・・・・・・累算
部分積レジスタ、１０・・・・・・３入力加算器、１１
・・・・・・上位積レジスタ、１２・・・・・・下位積
レジスタ、１３・・・・・・演算回路、１４・・・・・
・上位累算部分積シフタ、１６・・・・・・下位累算部
分積シフタ、１６・・・・・・２倍回路、１７・・・・
・・選択回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第 ２ 図
ＩＱ）
第３図Fig. 1 is a block diagram of a multiplication device according to an embodiment of the present invention, Fig. 2 is a control table diagram of a control circuit in the embodiment, and Fig. 3 is an upper partial product generation circuit and a lower partial product generation circuit in the embodiment. Block diagram showing the detailed configuration of circuit 8, No. 4
FIG. 6 is a circuit diagram showing a detailed configuration of a three-input adder in the same embodiment, FIG. 6 is a block diagram of a conventional multiplication device, and FIG. 6 is a control table diagram of an arithmetic control circuit of the same device. 1... Multiplicand register, 2... Multiplicand shift, 3... Multiplicand register, 4...
Multiplier shifter, 6... Carry flag, 6...
...Control circuit, 7... Upper partial product generation circuit, 8
...Lower partial product generation circuit, 9...Accumulated partial product register, 10...3-input adder, 11
...Upper product register, 12...Lower product register, 13...Arithmetic circuit, 14...
・Upper cumulative partial product shifter, 16...Lower cumulative partial product shifter, 16...2x circuit, 17...
...Selection circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure IQ) Figure 3
Claims (1)
出力を保持し再び前記３入力加算器に入力する累算部分
積レジスタと、被乗数から上位部分積を生成し前記３入
力加算器に入力する上位部分積生成回路と、被乗数から
下位部分積を生成し前記３入力加算器に入力する下位部
分積生成回路と、乗数から前記上位部分積生成回路と前
記下位部分積生成回路を制御する制御回路とを備え、２
つの部分積を同時に生成し、前記３入力加算器で累算部
分積を求めることを特徴とする乗算装置。a 3-input adder used for accumulation processing, an accumulation partial product register that holds the output of the 3-input adder and inputs it again to the 3-input adder, and the 3-input adder that generates an upper partial product from the multiplicand. A lower partial product generation circuit that generates a lower partial product from the multiplicand and inputs it to the three-input adder, and controls the upper partial product generation circuit and the lower partial product generation circuit from the multiplier. 2.
A multiplication device characterized in that two partial products are simultaneously generated, and the three-input adder calculates an accumulated partial product.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63070016A JPH01241622A (en) | 1988-03-24 | 1988-03-24 | Multiplying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63070016A JPH01241622A (en) | 1988-03-24 | 1988-03-24 | Multiplying device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01241622A true JPH01241622A (en) | 1989-09-26 |
Family
ID=13419393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63070016A Pending JPH01241622A (en) | 1988-03-24 | 1988-03-24 | Multiplying device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01241622A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03114887U (en) * | 1990-03-07 | 1991-11-26 | ||
| JPH0474219A (en) * | 1990-07-17 | 1992-03-09 | Toshiba Corp | High speed multiplier |
-
1988
- 1988-03-24 JP JP63070016A patent/JPH01241622A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03114887U (en) * | 1990-03-07 | 1991-11-26 | ||
| JPH0474219A (en) * | 1990-07-17 | 1992-03-09 | Toshiba Corp | High speed multiplier |
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