JPH0123940B2 - - Google Patents
Info
- Publication number
- JPH0123940B2 JPH0123940B2 JP16408584A JP16408584A JPH0123940B2 JP H0123940 B2 JPH0123940 B2 JP H0123940B2 JP 16408584 A JP16408584 A JP 16408584A JP 16408584 A JP16408584 A JP 16408584A JP H0123940 B2 JPH0123940 B2 JP H0123940B2
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- nitride film
- connection hole
- mesa groove
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- 239000011521 glass Substances 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特
に露出したPN接合部分を被覆する製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device for covering an exposed PN junction.
従来、半導体装置、例えばトランジスタの製造
方法には第２図ａ乃至ｇに示すようなものがあつ
た。すなわち、同図ａに示すように、コレクタと
なるＰ型層２と、ベースとなるＮ型層４とからな
るPN接合基体６を製造し、Ｎ型層４の主表面８
の各所定位置にそれぞれエミツタとなるＰ型層１
０を形成する。そして、主表面８の全域を酸化膜
１２によつて被覆する。次に同図ｂに示すよう
に、Ｐ型層１０の上方等の酸化膜１２の所定位置
の部分を除去して接続孔（コンタクトホール）１
４を形成する。なお、接続孔１４は層４，１０と
電極（図示せず）とを接続するためのものであ
る。そして、同図ｃに示すように、主表面８側か
ら基体６の内部側に向うメサ溝１６を形成する。
なお、メサ溝１６は、基体６上の各トランジスタ
を１個づつ独立させるためのものである。そし
て、同図ｄに示すように、メサ溝１６を被覆する
ように金属酸化物を主成分にするガラスペースト
１８を塗布する。このとき、接続孔１４にもガラ
スペースト１８が塗布される。そして、同図ｅに
示すようにガラスペースト１８を焼成する。１９
が焼成したガラスである。次に、同図ｆに示すよ
うに接続孔１４を除いて、酸化膜１２及び焼成し
たガラス１９をフオトレジスト２０により被覆す
る。最後に同図ｇに示すようにフツ酸と塩酸とを
混合したエツチング液によつて接続孔１４上の焼
成したガラス１９を除去する。
Conventionally, there have been methods for manufacturing semiconductor devices, such as transistors, as shown in FIGS. 2a to 2g. That is, as shown in FIG.
P-type layer 1 serving as an emitter at each predetermined position of
form 0. Then, the entire main surface 8 is covered with an oxide film 12. Next, as shown in FIG.
form 4. Note that the connection hole 14 is for connecting the layers 4, 10 and an electrode (not shown). Then, as shown in FIG. 3C, a mesa groove 16 is formed from the main surface 8 side toward the inside of the base body 6.
Note that the mesa groove 16 is for making each transistor on the base 6 independent one by one. Then, as shown in FIG. 4D, a glass paste 18 containing metal oxide as a main component is applied to cover the mesa groove 16. At this time, the glass paste 18 is also applied to the connection hole 14. Then, the glass paste 18 is fired as shown in FIG. 19
is fired glass. Next, as shown in FIG. 5F, the oxide film 12 and the fired glass 19 are covered with a photoresist 20, except for the connection holes 14. Finally, the fired glass 19 on the connecting hole 14 is removed using an etching solution containing a mixture of hydrofluoric acid and hydrochloric acid, as shown in FIG.
しかしながら、上記の方法では、接続孔１４上
の焼成したガラス１９を除去するため、不要部分
をフオトレジスト２０で被覆したうえでエツチン
グをしなければならない。従つて、フオトレジス
トのパターニングを正確にしなければならなかつ
た。しかもエツチング液はフツ酸と塩酸とを混合
したものであるので、フオトレジスト２０も腐食
され、予定よりも多くの部所が除去されることが
あつた。従つて、小さな接続孔、例えば30μm以
下の大きさの接続孔１４を形成することが困難で
あるという問題点があつた。
However, in the above method, in order to remove the fired glass 19 on the connection hole 14, it is necessary to cover unnecessary portions with the photoresist 20 and then perform etching. Therefore, the patterning of the photoresist had to be accurate. Moreover, since the etching solution was a mixture of hydrofluoric acid and hydrochloric acid, the photoresist 20 was also corroded, and more parts than expected were removed. Therefore, there is a problem in that it is difficult to form a small connection hole, for example, a connection hole 14 having a size of 30 μm or less.
上記の問題点を解決するための手段は、PN接
合基体の一方の主表面上に形成した酸化膜の一部
を除去して接続孔を形成する段階と、上記酸化膜
及び接続孔上に窒化膜を形成する段階と、上記主
表面側から上記基体内部側に向うメサ溝を形成す
る段階と、上記窒化膜及びメサ溝上にガラス状物
質を塗布する段階と、上記ガラス状物質を焼成す
る段階と、上記窒化膜及びその上のガラス状物質
を除去する段階とを備えるものである。
The means to solve the above problem consists of the steps of removing a part of the oxide film formed on one main surface of the PN junction substrate to form a contact hole, and nitriding the oxide film and the contact hole. a step of forming a film, a step of forming a mesa groove from the main surface side toward the inside of the substrate, a step of applying a glassy substance on the nitride film and the mesa groove, and a step of firing the glassy substance. and removing the nitride film and the glassy substance thereon.
この実施例は、まず第１図ａに示すように従来
のものと同様に、Ｐ型層２２とＮ型層２４とから
なるPN接合基体２６を形成し、そのＮ型層２４
の主表面２８側の各所定位置にそれぞれＰ型層２
９を形成し、主表面２８を酸化膜３０によつて被
覆する。そして、予め定めた位置の酸化膜３０を
それぞれ除去して接続孔３２を形成する。
In this embodiment, as shown in FIG.
A P-type layer 2 is provided at each predetermined position on the main surface 28 side of the
9 is formed, and the main surface 28 is covered with an oxide film 30. Then, the oxide film 30 at predetermined positions is removed to form the connection hole 32.
次に同図ｂに示すように、酸化膜３０及び接続
孔３２上をそれぞれ窒化膜３４によつて被覆す
る。 Next, as shown in FIG. 3B, the oxide film 30 and the connection hole 32 are each covered with a nitride film 34.
そして同図ｃに示すように、主表面２８から基
体２６の内側に向かうメサ溝３６を形成し、各ト
ランジスタをそれぞれ独立させる。 Then, as shown in FIG. 3C, a mesa groove 36 is formed extending from the main surface 28 toward the inside of the base 26, thereby making each transistor independent.
そして、同図ｄに示すようにメサ溝３６にガラ
スペースト３８を塗布する。この塗布は、例えば
ガラスペースト３８を主表面２８側にたらし、こ
れをナイフブレードなどで掃くことによつてメサ
溝３６内にガラスペースト３８を埋め、余分なガ
ラスペースト３８をふきとる方法や、電気泳動法
によつてなされる。このとき、窒化膜３４上にガ
ラスペースト３８が残留することは避けられな
い。 Then, a glass paste 38 is applied to the mesa groove 36 as shown in FIG. d. This application can be done, for example, by dropping the glass paste 38 onto the main surface 28 side, sweeping it with a knife blade or the like to fill the mesa groove 36 with the glass paste 38, and then wiping off the excess glass paste 38, or by applying electricity. It is done by the electrophoresis method. At this time, it is inevitable that the glass paste 38 remains on the nitride film 34.
次に、同図ｅに示すようにガラスペースト３８
を焼成する。４０が焼成したガラスを示す。 Next, as shown in the figure e, the glass paste 38
to be fired. 40 indicates the fired glass.
最後に、同図ｆに示すようにプラズマエツチン
グ等により、窒化膜３４と共にその上の焼成した
ガラス４０を除去する。 Finally, as shown in FIG. 5F, the nitride film 34 and the fired glass 40 thereon are removed by plasma etching or the like.
上記の実施例では、この発明をトランジスタの
製造方法に実施したが、他にサイリスタやダイオ
ードの製造方法にも実施できる。また、メサ溝３
６は主表面２８の片側だけに設けたが、主表面２
８とこれと反対側の主表面との双方からメサ溝を
設けてもよい。 In the above embodiments, the present invention is applied to a method of manufacturing a transistor, but it can also be applied to a method of manufacturing a thyristor or a diode. Also, mesa groove 3
6 was provided only on one side of the main surface 28, but
Mesa grooves may be provided from both the main surface 8 and the main surface opposite thereto.
以上述べたように、この発明による半導体装置
の製造方法によれば、窒化膜を形成した後に、ガ
ラスペーストを塗布、焼成し、その後に不要部分
の窒化膜及びその上のガラスを除去している。従
つてフオトレジストやエツチング液が不要であ
り、小型で正確な接続孔を形成できる。
As described above, according to the method of manufacturing a semiconductor device according to the present invention, after forming a nitride film, a glass paste is applied and fired, and then unnecessary portions of the nitride film and the glass thereon are removed. . Therefore, no photoresist or etching solution is required, and a small and accurate connection hole can be formed.
第１図ａ乃至ｆはこの発明による半導体装置の
製造方法の１実施例の各段階を示す図、第２図ａ
乃至ｇは従来の半導体装置の製造方法の各段階を
示す図である。
２６……PN接合基体、２８……主表面、３０
……酸化膜、３２……接続孔、３４……窒化膜、
３６……メサ溝、３８……ガラス状物質、４０…
…焼成したガラス。
Figures 1a to 1f are diagrams showing each step of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and Figure 2a
1 to 7g are diagrams showing each stage of a conventional method for manufacturing a semiconductor device. 26... PN bonded substrate, 28... Main surface, 30
... Oxide film, 32 ... Connection hole, 34 ... Nitride film,
36... Mesa groove, 38... Glassy substance, 40...
...fired glass.
Claims (1)
化膜の一部を除去して接続孔を形成する段階と、
上記酸化膜及び接続孔上に窒化膜を形成する段階
と、上記主表面側から上記基体内部側に向うメサ
溝を形成する段階と、上記窒化膜及びメサ溝上に
ガラス状物質を塗布する段階と、上記ガラス状物
質を焼成する段階と、上記窒化膜及びその上のガ
ラス状物質を除去する段階とを備える半導体装置
の製造方法。1. removing a part of the oxide film formed on one main surface of the PN bonding substrate to form a connection hole;
forming a nitride film on the oxide film and the connection hole; forming a mesa groove from the main surface side toward the inside of the base; and applying a glassy substance on the nitride film and the mesa groove. . A method of manufacturing a semiconductor device, comprising the steps of firing the glassy material, and removing the nitride film and the glassy material thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16408584A JPS6142144A (en) | 1984-08-03 | 1984-08-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16408584A JPS6142144A (en) | 1984-08-03 | 1984-08-03 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6142144A JPS6142144A (en) | 1986-02-28 |
| JPH0123940B2 true JPH0123940B2 (en) | 1989-05-09 |
Family
ID=15786491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16408584A Granted JPS6142144A (en) | 1984-08-03 | 1984-08-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142144A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3007734B2 (en) * | 1991-11-15 | 2000-02-07 | シャープ株式会社 | Solar cell manufacturing method |
| US5882986A (en) * | 1998-03-30 | 1999-03-16 | General Semiconductor, Inc. | Semiconductor chips having a mesa structure provided by sawing |
-
1984
- 1984-08-03 JP JP16408584A patent/JPS6142144A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6142144A (en) | 1986-02-28 |
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