JPH01238207A - Temperature compensating and amplifying circuit - Google Patents
Temperature compensating and amplifying circuitInfo
- Publication number
- JPH01238207A JPH01238207A JP63063581A JP6358188A JPH01238207A JP H01238207 A JPH01238207 A JP H01238207A JP 63063581 A JP63063581 A JP 63063581A JP 6358188 A JP6358188 A JP 6358188A JP H01238207 A JPH01238207 A JP H01238207A
- Authority
- JP
- Japan
- Prior art keywords
- current
- temperature
- circuit
- amplifier
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims abstract description 23
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 23
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、主として磁気記録再生装［（ＶＴＲ）に用い
られる温度補償増幅回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates primarily to a temperature-compensated amplifier circuit used in a magnetic recording/reproducing device (VTR).
（従来の技術）
従来の増幅回路例を第２図に示す０図において１は入力
端子であり、ＮＰＮトランジスタ６のベースに接続して
いる。このＮＰＮ トランジスタ６゜ベースに定電圧源
５が接続されたＮＰＮトランジスタ７、および抵抗８は
、正電源端子２と接地端子３の間に直列接続されてカス
コード増幅器を構成している。差動増幅器１４の反転入
力端子には前記カスコード増幅器の出力が、非反転入力
端子には定電圧源１５がそれぞれ接続され、該差動増幅
器１４の出力を出力端子４とし、且つ、差動増幅器１３
の反転入力端子に接続する。差動増幅器１３の非反転入
力端子には定電圧源１２を接続し、その出力を抵抗９，
１０を介してＮＰＮ）−ランジスタロのベースに接続し
、抵抗９，１０の接続点には他端接地の容ｆｆ１ｌｌを
接続する。前記カスコード増幅器の増幅度は、フィード
バックされて決定される回路電流１１と負荷抵抗値Ｒ工
により１次式で示される。(Prior Art) An example of a conventional amplifier circuit is shown in FIG. An NPN transistor 7 having a constant voltage source 5 connected to the base of the NPN transistor 6°, and a resistor 8 are connected in series between the positive power supply terminal 2 and the ground terminal 3 to form a cascode amplifier. The output of the cascode amplifier is connected to the inverting input terminal of the differential amplifier 14, and the constant voltage source 15 is connected to the non-inverting input terminal, and the output of the differential amplifier 14 is connected to the output terminal 4. 13
Connect to the inverting input terminal of A constant voltage source 12 is connected to the non-inverting input terminal of the differential amplifier 13, and its output is connected to a resistor 9,
It is connected to the base of the NPN)-rangistaro through the resistor 10, and the capacitor ff1ll whose other end is grounded is connected to the connection point of the resistors 9 and 10. The amplification degree of the cascode amplifier is expressed by a linear equation using the circuit current 11 determined by feedback and the load resistance value R.
Ｇ、＝２Ｏｆｌｏｇ （−１−ＸＩ、ＸＲ，） ・
・・■Ｔ
通常、増幅度を確定させるため、定電圧源１２の電圧値
と出力端子の電位が等しい時に、差動増幅器１４の面入
力端子電位が等しくなるように構成されている。この場
合、カスコード増幅器の増幅度は、電源電圧をｖｏとし
て、定電圧源１５の電圧値をｖｌ、で表わすと、次式で
示される。G, = 2Oflog (-1-XI, XR,) ・
... ■T Usually, in order to determine the degree of amplification, when the voltage value of the constant voltage source 12 and the potential of the output terminal are equal, the surface input terminal potential of the differential amplifier 14 is made equal. In this case, the amplification degree of the cascode amplifier is expressed by the following equation, where the power supply voltage is vo and the voltage value of the constant voltage source 15 is vl.
Ｇ １＝ ２０Ｑｏｇ （−ニー（Ｖｌｌｌｌ−Ｖｌ、
）） ・・・ ■Ｔ
ここでｑは電子電荷、Ｔは絶対温度、ｋはボルツマン定
数である。G 1 = 20Qog (-knee (Vlll-Vl,
)) ... ■T Here, q is the electron charge, T is the absolute temperature, and k is the Boltzmann constant.
最終出力増幅度は、差動増幅器１４の増幅度を０２とす
れば１次式で示される。The final output amplification degree is expressed by a linear equation, assuming that the amplification degree of the differential amplifier 14 is 02.
Ｇ＝Ｇ１＋Ｇ、 ・・・■ここ
では、Ｇの値に温度特性はないものとする。G=G1+G,... ■Here, it is assumed that the value of G has no temperature characteristics.
交流的なフィードバックは、容量ｌｌで交流接地されて
いるため行なわれない。AC feedback is not performed because it is AC grounded with a capacity 11.
（発明が解決しようとする課題）
しかしながら、第２図に示した回路構成では０式に示し
たように、温度変化に対し、増幅度が変化する。このた
めＶＴＲのヘッド出力再生においては、後段に自動増幅
度制御回路を用いて、この温度変化に対する増幅度の変
化を吸収しているが。(Problems to be Solved by the Invention) However, in the circuit configuration shown in FIG. 2, as shown in equation 0, the degree of amplification changes with respect to temperature changes. For this reason, in VTR head output reproduction, an automatic amplification control circuit is used in the latter stage to absorb changes in amplification due to temperature changes.
他要因のばらつきも含めて、制御範囲を広くとらなけれ
ばならない。また、ハイファイオーディオヘッド出力再
生においては、通常、自動増幅度制御回路を信号処理以
前に設けないので、増幅度は湿度変化に大きく影響され
る。The control range must be wide enough to include variations in other factors. Furthermore, in high-fidelity audio head output reproduction, an automatic amplification degree control circuit is usually not provided before signal processing, so the amplification degree is greatly affected by changes in humidity.
本発明は、この増幅度の温度変化を補償し、安定な再生
出力を得ることのできる増幅回路を提供するものである
。The present invention provides an amplifier circuit that can compensate for temperature changes in the degree of amplification and obtain stable reproduction output.
（ｉｌｌ１題を解決するための手段）
本発明は、第１のＮＰＮトランジスタのベースを入力信
号端子とし、正電源端子と接地間に抵抗、第２のＮＰＮ
トランジスタおよび前記第１のＮＰＮトランジスタを直
列接続して構成されるカスコード増幅器の出力を、その
出力を増幅回路の出力端子とする差動増幅器の反転入力
端子に接続し、その増幅度を確定する非反転入力端子の
電位を、電源電圧に接続した抵抗に、複数のＮＰＮトラ
ンジスタで構成したいわゆるカレントミラー回路と複数
のＰＮＰトランジスタで構成されたカレントミラー回路
の各電路を接続して得られる電流を流すことにより与え
るようにした構成の温度補償増幅回路である。(Means for Solving Problem 1) In the present invention, the base of the first NPN transistor is used as the input signal terminal, and a resistor is connected between the positive power supply terminal and the ground.
The output of a cascode amplifier configured by connecting a transistor and the first NPN transistor in series is connected to an inverting input terminal of a differential amplifier whose output is used as an output terminal of an amplifier circuit, and a non-conductor is used to determine the amplification degree. A current obtained by connecting the electric potential of the inverting input terminal to a resistor connected to the power supply voltage through a so-called current mirror circuit made up of multiple NPN transistors and a current mirror circuit made up of multiple PNP transistors is passed. This is a temperature-compensated amplifier circuit configured to provide the following characteristics.
（作 用）
ＮＰＮトランジスタで構成されたカレントミラー回路と
ＰＮＰ トランジスタで構成されたカレントミラー回路
を交差接続させ、ＰＮＰトランジスタのカレントミラー
回路のミラー比を１とすると、回路電流にｋＴ／（Ｉの
温度特性を持たせることができる。この回路電流で差動
増幅器の基準電圧をつくることにより、カスコード増幅
器で生じたｑ／ｋＴの温度特性を持つ増幅度の温度変化
を補償することができる。(Function) If a current mirror circuit composed of NPN transistors and a current mirror circuit composed of PNP transistors are cross-connected, and the mirror ratio of the current mirror circuit of PNP transistors is 1, the circuit current will be kT/(I of By using this circuit current to create a reference voltage for the differential amplifier, it is possible to compensate for the temperature change in the amplification factor that occurs in the cascode amplifier and has a temperature characteristic of q/kT.
（実施例）
以下、本発明の温度補償増幅回路の一実施例を第１図に
基づいて説明する。差動増幅器１４の反転入力端子にＮ
ＰＮトランジスタ６のベースを入力信号端子１とし電源
電圧端子２と接地３間にＮＰＮトランジスタ６．７と負
荷抵抗８を直列接続して構成したカスコード増幅器の出
力を接続し、その増幅度を確定する非反転入力端子の電
位を、電源電圧に接続した抵抗２６に、ＮＰＮトランジ
スタ１９、２１．２３で構成されたカレントミラー回路
とＰＮＰトランジスタ２４．２５で構成されるカレント
ミラー回路の各電路を接続して得られる電流を流すこと
で、前記問題点の温度変化に対する増幅度変動を補償す
る回路構成となっている。(Embodiment) Hereinafter, one embodiment of the temperature compensation amplifier circuit of the present invention will be described based on FIG. 1. N to the inverting input terminal of the differential amplifier 14
The base of the PN transistor 6 is used as the input signal terminal 1, and the output of a cascode amplifier configured by connecting the NPN transistor 6.7 and the load resistor 8 in series is connected between the power supply voltage terminal 2 and the ground 3, and the amplification degree is determined. The potential of the non-inverting input terminal is connected to the resistor 26 connected to the power supply voltage, and each electric path of the current mirror circuit consisting of the NPN transistors 19 and 21.23 and the current mirror circuit consisting of the PNP transistors 24.25 is connected. The circuit is configured to compensate for the amplification variation due to temperature change, which is the problem mentioned above, by flowing a current obtained by the above-described current.
次に、第１図の実施例について動作説明する。Next, the operation of the embodiment shown in FIG. 1 will be explained.
第１図において、抵抗２２の値をＲ３とし、ＮＰＮトラ
ンジスタ２１のエミッタ面積をＮＰＮトランジスタ１９
およびｚ３のｎ倍とする。ＰＮＰ）−ランジスタ２４．
２５で構成されたカレントミラーのミラー比を１とすれ
ば、この組合せはバンドギャップリファレンス回路を構
成し、回路電流は次式で示される。In FIG. 1, the value of the resistor 22 is R3, and the emitter area of the NPN transistor 21 is the NPN transistor 19.
and n times z3. PNP) - transistor 24.
If the mirror ratio of the current mirror made up of 25 is 1, this combination constitutes a bandgap reference circuit, and the circuit current is expressed by the following equation.
この電流をカレントミラーで、差動増幅器１４の非反転
入力端子と電源電圧の間に接続された抵抗２６に流し、
増幅度を確定する電圧を与える。その電圧値ｖＡは、抵
抗２６の値をＲ１とすれば、次式で示される。This current is passed through a resistor 26 connected between the non-inverting input terminal of the differential amplifier 14 and the power supply voltage using a current mirror.
Give a voltage to determine the degree of amplification. The voltage value vA is expressed by the following equation, assuming that the value of the resistor 26 is R1.
差動増幅器１４の面入力端子電位を等しくなるように直
流フィードバックをかけるため、差動増幅器１３の非反
転入力端子の電位にも、■式で示される回路電流を抵抗
１６に流し、温度変化を持たせる。In order to apply DC feedback so that the surface input terminal potentials of the differential amplifier 14 are equalized, a circuit current shown by the formula Have it.
この状態で、電源電圧に接続されたカスコード増幅器の
負荷抵抗８の両端電位差と、同じく電源電圧に接続され
た抵抗２６の両端電位差は等しくなる。In this state, the potential difference across the load resistor 8 of the cascode amplifier connected to the power supply voltage becomes equal to the potential difference across the resistor 26, which is also connected to the power supply voltage.
すなわち、
Ｒ□Ｉ、＝Ｒ，Ｉ２ ・・・■と
なる。That is, R□I,=R,I2...■.
■式と■式および０式より、この回路構成でのカスコー
ド増幅器の増幅度は次式で示される。From equations (1), (2), and (0), the amplification degree of the cascode amplifier in this circuit configuration is expressed by the following equation.
第１図に示した実施例の温度補償増幅回路は、■式で示
すように温度変化の項を、カスコード増幅器の増幅度の
式を含まず、湿度変化のない安定な再生増幅出力を得る
ことができる。The temperature-compensated amplifier circuit of the embodiment shown in FIG. 1 does not include the temperature change term and the amplification degree equation of the cascode amplifier, as shown in equation (2), and can obtain a stable regenerative amplification output without humidity changes. Can be done.
回路図中のＮＰＮ トランジスタ１８と定電圧源１５は
、バンドギャップリファレンス回路のスタート回路であ
り、安定動作に入るとＮＰＮトランジスタ１８はＯＦＦ
するように、定電圧源１５の値と抵抗２０の値は設定さ
れる。The NPN transistor 18 and constant voltage source 15 in the circuit diagram are the start circuit of the bandgap reference circuit, and when stable operation begins, the NPN transistor 18 is turned off.
The value of constant voltage source 15 and the value of resistor 20 are set so that.
（発明の効果）
本発明によれば、ＶＴＲのヘッド出力等の微小信号の再
生において、再生増幅器の増幅度の温度変化を解消する
ことができるものである。(Effects of the Invention) According to the present invention, temperature changes in the amplification degree of the reproducing amplifier can be eliminated in reproducing minute signals such as the head output of a VTR.
第１図は本発明の一実施例における温度補償増幅回路の
回路図、第２図は従来例における増幅回路の回路例であ
る。
１・・・入力端子、２・・・電源電圧端子、３・・・接
地端子、４・・・出力端子、５．１２．１５・・・定電
圧源、６ 、７ 、１８．１９．２１．２３・・・ＮＰ
Ｎトランジスタ、８ 、９ 、１０．１６．２０゜２２
、２６・・・抵抗、１１・・・容量、１３．１４・・・
差動増幅器、１７．２４．２５−Ｐ Ｎ Ｐ トランジ
スタ。FIG. 1 is a circuit diagram of a temperature compensated amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a circuit example of a conventional amplifier circuit. 1... Input terminal, 2... Power supply voltage terminal, 3... Ground terminal, 4... Output terminal, 5.12.15... Constant voltage source, 6, 7, 18.19.21 .23...NP
N transistor, 8, 9, 10.16.20°22
, 26...Resistance, 11...Capacity, 13.14...
Differential amplifier, 17.24.25-PNP transistor.
Claims (1)
、正電源端子と接地間に抵抗、第２のＮＰＮトランジス
タおよび前記第１のＮＰＮトランジスタを直列接続して
構成されるカスコード増幅器の出力を、その出力を増幅
回路の出力端子とする差動増幅器の反転入力端子に接続
し、その増幅度を確定する非反転入力端子の電位を、電
源電圧に接続した抵抗に、複数のＮＰＮトランジスタで
構成したカレントミラー回路と複数のＰＮＰトランジス
タで構成されたカレントミラー回路の各電路を接続して
得られる電流を流すことにより与えるようにしたことを
特徴とする温度補償増幅回路。The output of a cascode amplifier is configured by using the base of the first NPN transistor as an input signal terminal, connecting a resistor between the positive power supply terminal and ground, and connecting the second NPN transistor and the first NPN transistor in series. is connected to the inverting input terminal of the differential amplifier, which serves as the output terminal of the amplifier circuit, and the potential of the non-inverting input terminal, which determines the degree of amplification, is connected to the resistor connected to the power supply voltage. 1. A temperature-compensated amplifier circuit, characterized in that a current is applied by connecting a circuit and each electric path of a current mirror circuit composed of a plurality of PNP transistors and causing a current to flow therethrough.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63063581A JPH01238207A (en) | 1988-03-18 | 1988-03-18 | Temperature compensating and amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63063581A JPH01238207A (en) | 1988-03-18 | 1988-03-18 | Temperature compensating and amplifying circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01238207A true JPH01238207A (en) | 1989-09-22 |
Family
ID=13233374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63063581A Pending JPH01238207A (en) | 1988-03-18 | 1988-03-18 | Temperature compensating and amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01238207A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04217104A (en) * | 1990-12-18 | 1992-08-07 | Sanyo Electric Co Ltd | Signal amplifier circuit |
| JPH05167355A (en) * | 1991-12-19 | 1993-07-02 | Japan Radio Co Ltd | Input impedance stabilizing circuit |
-
1988
- 1988-03-18 JP JP63063581A patent/JPH01238207A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04217104A (en) * | 1990-12-18 | 1992-08-07 | Sanyo Electric Co Ltd | Signal amplifier circuit |
| JPH05167355A (en) * | 1991-12-19 | 1993-07-02 | Japan Radio Co Ltd | Input impedance stabilizing circuit |
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