JPH01238130A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01238130A
JPH01238130A JP6495688A JP6495688A JPH01238130A JP H01238130 A JPH01238130 A JP H01238130A JP 6495688 A JP6495688 A JP 6495688A JP 6495688 A JP6495688 A JP 6495688A JP H01238130 A JPH01238130 A JP H01238130A
Authority
JP
Japan
Prior art keywords
chip
bonding
guide
die
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6495688A
Other languages
Japanese (ja)
Inventor
Kaoru Takahashi
薫 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP6495688A priority Critical patent/JPH01238130A/en
Publication of JPH01238130A publication Critical patent/JPH01238130A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/75303—Shape of the pressing surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the displacement of a chip at the time of die.bonding by conducting die.bonding to a bonding section through a chip.guide. CONSTITUTION:When die.bonding is performed to a lead.frame, a chip 2 is carried up to the upper section of a bonding section 5 by a collet 3. The chip 2 is bonded with the bonding section 5 to which a chip.guide 1 is formed through machining by previous etching. Likewise, even when die.bonding is executed to a printed board, the chip.guide is shaped previously to the bonding section through cutting, and the chip is bonded with the bonding section for the printed board. Accordingly, die.bonding is conducted to the bonding section through the chip.guide, thus preventing the displacement of the chip, thereby improving yield.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はダイｅボンディングを行う半導体装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device that performs die e-bonding.

〔従来の技術〕[Conventional technology]

従来のダイ・ボンディングを行う半導体装置の製造方法
は、ボンディング部にチップ番ガイドを介さずにそのま
まダイ・ボンディングするものであった。In the conventional method of manufacturing a semiconductor device using die bonding, die bonding is directly performed without using a chip number guide at the bonding portion.

〔発明が解決し、ようとする課題〕[Problem to be solved by the invention]

しかし、前４の従来技術ではダイ・ボンディング時にボ
ンディング部でチップがズレ、後の工程（例えばりイヤ
・ボンディング）ができず、歩留りが悪くなるという問
題点を存する。However, the fourth prior art has the problem that the chip shifts at the bonding part during die bonding, making it impossible to perform subsequent steps (for example, ear bonding), and resulting in poor yield.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところはダイ・ボンディング時にチップが
ズレないようにする半導体装置の＃Ａ遣方法を提供する
ところにある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a #A method for semiconductor devices that prevents chips from shifting during die bonding.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、ダイ・ボンディング
において、ボアディング部にチップｅガイドを介してグ
イ自ポンデイ／グを行うことを特徴とする。The method for manufacturing a semiconductor device according to the present invention is characterized in that during die bonding, self-bonding is performed on the bored portion via a chip e-guide.

〔実施例〕〔Example〕

以下、本弁明を実施例に基づいて詳細に説明する。 Hereinafter, this defense will be explained in detail based on examples.

第１図は本発明によるリード自フレームへのダイ・ボン
ディング工程を示す図である。１はチップ・ガイド、２
はチップ、３はコレット、４はリード、５はボンディン
グ部である。まず周知の方法によりチップ２をコレット
３でボンディング部５上方まで運ぶ。それから、例えば
、あらかじめエツチングにより加工してチ・ツブ・ガイ
ド１をイ・１けた１ｃノディング部５に、チップ２を周
知の方法でボンディングする。FIG. 1 is a diagram showing the process of die bonding a lead to its own frame according to the present invention. 1 is the tip guide, 2
3 is a chip, 3 is a collet, 4 is a lead, and 5 is a bonding part. First, the chip 2 is carried above the bonding part 5 by the collet 3 using a well-known method. Then, for example, the chip 2 is bonded to the A-1 digit 1c nodding part 5 of the chip guide 1 which has been processed by etching in advance by a well-known method.

第２図は本発明によるリード・フレームへのダイ・ボン
ディング完了後の図である。ｌはチップ・ガイド、２は
チップ、６はリード番フレームである。FIG. 2 is a diagram after completion of die bonding to a lead frame according to the present invention. 1 is a chip guide, 2 is a chip, and 6 is a lead number frame.

同様に、ブリット基板へのダイ争ボンディングの際も、
例えば切削によりボンディング部にチップ・ガイドを作
っておき、チップをプリント基板のボンディング部にボ
ンディングする。Similarly, when performing die bonding to a bullet board,
For example, a chip guide is made in the bonding part by cutting, and the chip is bonded to the bonding part of the printed circuit board.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明の半導体装置の製造方法によれ
ば、ボンディング部にチ・ツブ・ガイドを介してグイ・
ボンディングを行うことによりチップがズレなくなり、
歩留りが向上できるという効果を有する。As described above, according to the method of manufacturing a semiconductor device of the present invention, the guide is attached to the bonding portion via the chip guide.
Bonding prevents the chip from slipping,
This has the effect of improving yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の半導体装置のａ２遣方法の一実施例を
示す主要断面図。 第２図は完成された半導体装置の平面図。 １１．チップ自ガイド ２・・・チップ ３・・・コレット ４・・・リード ５・・・ボンディング部 ６・・・リード−フレーム 以　　上 出願人　セイフーエブソン株式会社FIG. 1 is a main sectional view showing an embodiment of the a2 sending method for a semiconductor device of the present invention. FIG. 2 is a plan view of the completed semiconductor device. 11. Chip self-guide 2...Chip 3...Collet 4...Lead 5...Bonding part 6...Lead-frame and above Applicant Seifu Ebson Corporation

Claims (1)

【特許請求の範囲】[Claims] （１）ダイ・ボンディングにおいて、ボンディング部に
チップ・ガイドを介して、ダイ・ボンディングを行うこ
とを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, characterized in that in die bonding, die bonding is performed via a chip guide at a bonding portion.
JP6495688A 1988-03-18 1988-03-18 Manufacture of semiconductor device Pending JPH01238130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6495688A JPH01238130A (en) 1988-03-18 1988-03-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6495688A JPH01238130A (en) 1988-03-18 1988-03-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01238130A true JPH01238130A (en) 1989-09-22

Family

ID=13273003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6495688A Pending JPH01238130A (en) 1988-03-18 1988-03-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01238130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977940B1 (en) 2000-04-28 2005-12-20 Switchcore, Ab Method and arrangement for managing packet queues in switches

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977940B1 (en) 2000-04-28 2005-12-20 Switchcore, Ab Method and arrangement for managing packet queues in switches

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