JPH01232828A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPH01232828A JPH01232828A JP63058900A JP5890088A JPH01232828A JP H01232828 A JPH01232828 A JP H01232828A JP 63058900 A JP63058900 A JP 63058900A JP 5890088 A JP5890088 A JP 5890088A JP H01232828 A JPH01232828 A JP H01232828A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- voltage signal
- input
- bias voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002347 injection Methods 0.000 claims abstract description 6
- 239000007924 injection Substances 0.000 claims abstract description 6
- 230000010355 oscillation Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 abstract description 14
- 238000001514 detection method Methods 0.000 description 14
- 230000001360 synchronised effect Effects 0.000 description 10
- 238000012544 monitoring process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009499 grossing Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電源交流の検出信号などの周波数変動の少な
い周波数信号を入力信号とするＰＬＬ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL circuit whose input signal is a frequency signal with little frequency fluctuation, such as a detection signal of an AC power source.
従来、電力設備の電源監視用計測装置においては、変成
器などから出力された電源交流の検出信号をサンプリン
グし、電源交流の電圧、電流の波形解析などをデジタル
的に行っている。BACKGROUND ART Conventionally, a measuring device for monitoring power supply of electric power equipment samples a detection signal of AC power supply output from a transformer or the like, and digitally performs waveform analysis of voltage and current of the AC power supply.
ところで、電源交流に同期した前記検出信号のサンプリ
ングパルスの作成などに用いられる基準信号は、従来、
第３図に示す一般的なＰＬＬ回路で形成される。By the way, the reference signal used for creating the sampling pulse of the detection signal synchronized with the power supply AC has conventionally been
It is formed by a general PLL circuit shown in FIG.
そして、第３図のＰＬＬ回路の動作を説明すると、前記
検出信号が入力端子（１）を介して位相比較器（２）に
入力され、比較器（２）により、入力端子（１）の検出
信号と電圧制御発振器（３）の出力信号又は該信号の分
周信号とが位相比較され、比較器（２）からループフィ
ルタ（４）に、検出信号を基準にして、■Ｃ０（３１の
出力信号の位相の進み、遅れに応じて周波数変化する位
相差の信号が出力される。To explain the operation of the PLL circuit shown in FIG. 3, the detection signal is input to the phase comparator (2) via the input terminal (1), and the comparator (2) detects The signal and the output signal of the voltage controlled oscillator (3) or the frequency-divided signal of the signal are compared in phase, and from the comparator (2) to the loop filter (4), based on the detection signal, A phase difference signal whose frequency changes according to the phase advance or delay of the signal is output.
さらに、フィルタ（４）の積分平滑により、比較器（２
）の位相差の信号が当該信号の周波数変化に応じてレベ
ル変化する直流の制御電圧信号に変換され、該制御電圧
信号がＶ ＣＯｆ３＋に供給される。Furthermore, due to the integral smoothing of the filter (4), the comparator (2
) is converted into a DC control voltage signal whose level changes according to the frequency change of the signal, and the control voltage signal is supplied to V COf3+.
そして、制御電圧信号の電圧によってＶ ＣＯ（３＋の
発振周波数が可変制御され、Ｖ ＣＯ（３１の出力信号
が入力端子（１）の検出信号の周波数に同期するように
フィードバック制御される。The oscillation frequency of V CO (3+) is variably controlled by the voltage of the control voltage signal, and feedback control is performed so that the output signal of V CO (31) is synchronized with the frequency of the detection signal of the input terminal (1).
なお、フィルタ（４）の積分平滑によってノイズ成分な
どの不要な高調波成分が除去されるとともに、フィルタ
（４）の時定数によって同期引込み特性及び過渡特性が
定まり、通常、フィルタ（４）の時定数は、過渡特性を
考慮して比較的小さく設定されている。Note that the integral smoothing of the filter (4) removes unnecessary harmonic components such as noise components, and the time constant of the filter (4) determines the synchronization pull-in characteristics and transient characteristics. The constant is set relatively small in consideration of transient characteristics.
また、Ｖ ＣＯｆ３＋の出力信号又は該信号の分周信号
がＰＬＬ回路の出力信号として出力される。Further, the output signal of V COf3+ or the frequency-divided signal of the signal is output as the output signal of the PLL circuit.
ところで、検出信号の入力前、すなわち入力端子Ｈ１に
入力信号が入力される前は、いわゆる開ループ状態とな
ってフィルタ（４）の制御電圧信号が０に保持され、Ｖ
ＣＯ＋ａ＋が発振停止状態に保持される。By the way, before the detection signal is input, that is, before the input signal is input to the input terminal H1, the control voltage signal of the filter (4) is held at 0 in a so-called open loop state, and V
CO+a+ is maintained in an oscillation stopped state.
そして、入力端子（１）に入力信号が入力され始めるこ
とにより、開ループ状態から周波数引込み過程に移行し
、比較器（２）の出力信号にもとづき、フィルタ（４）
の制御電圧信号が同期引込み特性で増加し、Ｖ ＣＯ（
３＋の発振周波数が入力信号に同期した周波数に引込ま
れる。Then, when an input signal starts to be input to the input terminal (1), the open loop state shifts to the frequency pull-in process, and the filter (4)
The control voltage signal of increases with the synchronous pull-in characteristic, and V CO (
The 3+ oscillation frequency is pulled to a frequency synchronized with the input signal.
さらに、Ｖ ＣＯ（３＋の発振周波数が入力信号の周波
数に完全に引込まれて同期が確立されたときに、位相同
期過程に移行し、このとき、ＰＬＬ回路の出力信号が安
定な信号になる。Furthermore, when the oscillation frequency of the VCO (3+) is completely pulled into the frequency of the input signal and synchronization is established, the phase synchronization process begins, and at this time, the output signal of the PLL circuit becomes a stable signal.
ところで、電源交流の周波数は事故などが生じない限り
安定しており、しかも、たとえば系統間の周波数差も少
ない。By the way, the frequency of power source alternating current is stable unless an accident occurs, and there is also little difference in frequency between systems, for example.
一方、前記計測装置により、たとえば複数の系統の電源
交流の監視を周期的に監視電源を切換えて行う場合、Ｐ
ＬＬ回路の入力信号、すなわち入力端子（１）の検出信
号も監視電源の切換えにしたがって切換わる。On the other hand, when using the measurement device to monitor power supply AC of multiple systems by periodically switching the monitoring power supply, for example, P
The input signal of the LL circuit, that is, the detection signal of the input terminal (1) is also switched in accordance with the switching of the monitoring power supply.
そして、入力信号が切換わると、入力信号の断によって
ＰＬＬ回路が開ループ状態になるとともに、入力信号が
入力され始めたときに、開ループ状態から前述の周波数
引込み過程を介して位相同期過程に移行し、切換えられ
た入力信号にＰＬＬ回路の出力信号が同期する。When the input signal is switched, the PLL circuit enters an open loop state due to the disconnection of the input signal, and when the input signal starts to be input, the PLL circuit changes from the open loop state to the phase locking process via the frequency pull-in process described above. The output signal of the PLL circuit is synchronized with the switched input signal.
このとき、前記従来のＰＬＬ回路では、入力信号の周波
数が切換え前、後でほとんど変わらないにもかかわらず
、Ｖ ＣＯ（３１の発振停止状態から同期引込みが行わ
れ、周波数引込み過程に時間を要し、同期の確立が迅速
に行えず、とくに、電源交流の検出信号のような周波数
の低い周波数信号を入力信号とするときには、同期の確
立に長時間を要する問題点がある。At this time, in the conventional PLL circuit, synchronization is performed from the oscillation stopped state of the VCO (31) even though the frequency of the input signal is almost the same before and after switching, and the frequency pull-in process takes time. However, there is a problem in that synchronization cannot be established quickly, and it takes a long time to establish synchronization, especially when a low frequency signal such as a detection signal of an AC power source is used as an input signal.
本発明は、電源交流の検出信号のような周波数変動の少
ない周波数信号を入力信号とするＰＬＬ回路において、
周波数引込み過程の時間を矧縮し、迅速に同期を確立す
ることを目的とする。The present invention provides a PLL circuit that uses as an input signal a frequency signal with little frequency fluctuation, such as a detection signal of power supply alternating current.
The purpose is to shorten the time required for the frequency pull-in process and quickly establish synchronization.
前記目的を達成するだめの手段を、実施例に対応する第
１図を参照して以下に説明する。Means for achieving the above object will be explained below with reference to FIG. 1, which corresponds to an embodiment.
本発明は、周波数変動の少ない入力信号にもとづき、電
圧制御発振器、すなわちＶ ＣＯ（３１の発振周波数を
フィードバック制御するＰＬＬ回路において、
前記入力信号と前記Ｖ ＣＯｆ３１の出力信号の位相差
の信号を出力する位相比較器（２）と、前記比較器（２
１の出力信号を積分平滑して前記ＶＣＯｆ３１の制御電
圧信号を出力するル−プフィルタ（４）と、
前記制御電圧信号に加算される所定レベルのバイアス電
圧信号を出力するバイアス注入回路の出力端子＋５１と
を備えるという技術的手段を講じている。The present invention provides a PLL circuit that performs feedback control of the oscillation frequency of a voltage controlled oscillator, that is, V CO (31), based on an input signal with little frequency fluctuation, and outputs a signal with a phase difference between the input signal and the output signal of the V CO (31). a phase comparator (2), and a phase comparator (2)
a loop filter (4) that integrates and smoothes the output signal of VCOf31 and outputs a control voltage signal of the VCOf31; and an output terminal +51 of a bias injection circuit that outputs a bias voltage signal of a predetermined level to be added to the control voltage signal. We are taking technical measures to prepare for this.
したがって、比較器＋２１に入力信号が入力されない開
ループ状態のときにも、出力端子（５）のバイアス電圧
信号によってＶ ＣＯｆ３１が発振し、このときバイア
ス電圧信号の所定レベルにもとづき、発振周波数が同期
確立時の周波数の近傍の周波数になる。Therefore, even in an open loop state where no input signal is input to comparator +21, V COf31 oscillates due to the bias voltage signal at the output terminal (5), and at this time, the oscillation frequency is synchronized based on the predetermined level of the bias voltage signal. The frequency will be close to the frequency at the time of establishment.
そして、比較器（２）に入力信号が入力され始めると、
フィルタ〔４）の制御電圧信号とバイアス電圧信号の加
算電圧信号によってＶ ＣＯｆ３１の発振周波数が入力
信号に同期した周波数に引込まれ、このとき、発振周波
数が既にほぼ同期した周波数に達しているだめ、発振周
波数の引込みが短時間で終了し、周波数引込み過程が短
縮されて迅速に同期が確立する。Then, when the input signal starts to be input to the comparator (2),
The oscillation frequency of V COf31 is pulled into the frequency synchronized with the input signal by the addition voltage signal of the control voltage signal and the bias voltage signal of the filter [4], and at this time, since the oscillation frequency has already reached the almost synchronized frequency, The oscillation frequency pull-in is completed in a short time, the frequency pull-in process is shortened, and synchronization is quickly established.
つぎに、本発明を、そのｌ実施例を示した第１図及び第
２図とともに詳細に説明する。Next, the present invention will be explained in detail with reference to FIGS. 1 and 2 showing an embodiment thereof.
第１図において、第３図と同一記号は同一もしくは相当
するものを示し、異なる点は、所定レベルのバイアス電
圧信号（直流）を出力するバイアス注入回路を設け、そ
の出力端子Ｃ５１のバイアス電圧信号をフィルタ（４）
の制御電圧信号に加算してＶＣＯｒ３＋に供給した点で
ある。In FIG. 1, the same symbols as those in FIG. 3 indicate the same or equivalent parts. Filter (4)
This is the point where it is added to the control voltage signal of and supplied to VCOr3+.
そして、バイアス注入回路は、たとえば定電圧電源回路
からなり、バイアス電圧信号の所定レベルは第２図のレ
ベルＶｄ 、すなわち発振周波数が電源交流の規定周波
数に同期したときにＶ ＣＯｆ３１に印加される電圧よ
り少い電圧に設定されている。The bias injection circuit is composed of, for example, a constant voltage power supply circuit, and the predetermined level of the bias voltage signal is the level Vd in FIG. 2, that is, the voltage applied to V COf31 when the oscillation frequency is synchronized with the specified frequency of the power source It is set to a lower voltage.
そのため、監視電源の切換えにもとづく入力端子（１）
の検出信号の切換えによシ、入力信号の断状態になって
も、Ｖ ＣＯ（３１にバイアス電圧信号が供給され、Ｖ
ＣＯｆ３＋が同期確立時の周波数の近傍の周波数で発
振を持続する。Therefore, the input terminal (1) based on the switching of the monitoring power supply
By switching the detection signal of
COf3+ continues to oscillate at a frequency near the frequency when synchronization is established.
そして、入力端子（１）に検出信号が入力され始めると
、周波数引込み過程に移行し、比較器（２）の位相差の
信号にもとづき、フイｌレタ（４）から制御電圧信号が
出力される。Then, when a detection signal starts to be input to the input terminal (1), the process moves to a frequency pull-in process, and a control voltage signal is output from the filter (4) based on the phase difference signal of the comparator (2). .
このとき、Ｖ ＣＯｆ３＋に制御電圧信号とバイアス電
圧信号とを加算した電圧が印加され、制御電圧信号によ
υ、バイアス電圧信号にもとづく周波数のずれがフィー
ドバック制御で補正されて発振周波数が電源交流に同期
した周波数に引込まれる。At this time, a voltage that is the sum of the control voltage signal and the bias voltage signal is applied to V COf3+, and the frequency shift based on the control voltage signal υ and the bias voltage signal is corrected by feedback control, and the oscillation frequency is changed to the power supply AC. Drawn to a synchronized frequency.
そして、発振周波数の引込みが終了して同期が確立され
ると、位相同期過程に移行し、以降は、電源交流の周波
数変動にもとづく検出信号の周波数変化により、制御電
圧信号のレベルが変化して発振周波数がフィードバック
制御される。When the oscillation frequency pull-in is completed and synchronization is established, the phase synchronization process begins. From then on, the level of the control voltage signal changes due to the frequency change of the detection signal based on the frequency fluctuation of the power supply AC. The oscillation frequency is feedback controlled.
したがって、周波数引込み過程の間には、バイアス電圧
信号にもとづくほぼ同期確立時の周波数から発振周波数
を引込めばよく、この場合、周波数引込み過程の時間’
ｒａは第２図に示すように、従来の周波数引込み過程の
時間Ｔｂより著しく短縮される。Therefore, during the frequency pull-in process, it is sufficient to pull the oscillation frequency from the frequency at which synchronization is approximately established based on the bias voltage signal.
As shown in FIG. 2, ra is significantly shorter than the time Tb of the conventional frequency pull-in process.
そのため、従来のＰＬＬ回路より迅速に同期が確立され
、監視電源の切換えから矧時間で、安定した基準信号を
出力することができる。Therefore, synchronization can be established more quickly than in conventional PLL circuits, and a stable reference signal can be output within a short period of time after switching the monitoring power supply.
なお、前記実施例では、電源交流の検出信号を入力信号
としだが、周波数変動が少なく、引込み周波数が既知の
種々の周波数信号を入力信号として、同様の効果が得ら
れるのは勿論である。In the above embodiments, the detection signal of the power supply AC is used as the input signal, but it goes without saying that the same effect can be obtained by using various frequency signals with small frequency fluctuations and known pull-in frequencies as the input signal.
以上のように、本発明のＰＬＬ回路によると、バイアス
注入回路のバイアス電圧信号を電圧制御発振器に供給し
、入力信号のないときにも、バイアス電圧信号によって
発振器を同期確立時の周波数に近い周波数で発振したこ
とによシ、発振周波数の同期引込みに要する周波数引込
み過程の時間を短縮し、迅速に同期を確立することがで
きるものである。As described above, according to the PLL circuit of the present invention, the bias voltage signal of the bias injection circuit is supplied to the voltage controlled oscillator, and even when there is no input signal, the oscillator is operated by the bias voltage signal at a frequency close to the frequency at the time of synchronization establishment. By oscillating the oscillation frequency, it is possible to shorten the time required for the frequency pull-in process to pull the oscillation frequency into synchronization, and to quickly establish synchronization.
第１図は本発明のＰＬＬ回路の１実施例のブロック図、
第２図は第１図の同期引込み特性の説明図、第３図は従
来のＰＬＬ回路のブロック図である。
（１）・・・入力端子、ｆ２＋・・・位相比較器、（３
）・・・ｖＣＯｌ（４）・・・〜−プフィルタ、（５）
・・・バイアス注入回路の出力端子。FIG. 1 is a block diagram of one embodiment of the PLL circuit of the present invention,
FIG. 2 is an explanatory diagram of the synchronization pull-in characteristic of FIG. 1, and FIG. 3 is a block diagram of a conventional PLL circuit. (1)...Input terminal, f2+...Phase comparator, (3
)...vCOl(4)...～-pfilter, (5)
...Output terminal of the bias injection circuit.
Claims (1)
御発振器の発振周波数をフィードバック制御するＰＬＬ
回路において、 前記入力信号と前記発振器の出力信号の位相差の信号を
出力する位相比較器と、 前記比較器の出力信号を積分平滑して前記発振器の制御
電圧信号を出力するループフィルタと、前記制御電圧信
号に加算される所定レベルのバイアス電圧信号を出力す
るバイアス注入回路とを備えたことを特徴とするＰＬＬ
回路。(1) PLL that feedback controls the oscillation frequency of a voltage controlled oscillator based on an input signal with little frequency fluctuation
The circuit includes: a phase comparator that outputs a signal representing a phase difference between the input signal and the output signal of the oscillator; a loop filter that integrates and smooths the output signal of the comparator and outputs a control voltage signal for the oscillator; A PLL comprising a bias injection circuit that outputs a bias voltage signal of a predetermined level to be added to a control voltage signal.
circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63058900A JPH01232828A (en) | 1988-03-12 | 1988-03-12 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63058900A JPH01232828A (en) | 1988-03-12 | 1988-03-12 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01232828A true JPH01232828A (en) | 1989-09-18 |
Family
ID=13097680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63058900A Pending JPH01232828A (en) | 1988-03-12 | 1988-03-12 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01232828A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06197014A (en) * | 1992-12-25 | 1994-07-15 | Mitsubishi Electric Corp | Phase locked loop circuit |
| JP2007189638A (en) * | 2006-01-16 | 2007-07-26 | Nec Corp | Phase-locked loop |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57145440A (en) * | 1981-03-04 | 1982-09-08 | Mitsubishi Electric Corp | Phase synchronizing circuit |
| JPS61270918A (en) * | 1985-05-27 | 1986-12-01 | Canon Inc | Phase locked loop device |
| JPS623528A (en) * | 1985-06-28 | 1987-01-09 | Casio Comput Co Ltd | Pll oscillator |
-
1988
- 1988-03-12 JP JP63058900A patent/JPH01232828A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57145440A (en) * | 1981-03-04 | 1982-09-08 | Mitsubishi Electric Corp | Phase synchronizing circuit |
| JPS61270918A (en) * | 1985-05-27 | 1986-12-01 | Canon Inc | Phase locked loop device |
| JPS623528A (en) * | 1985-06-28 | 1987-01-09 | Casio Comput Co Ltd | Pll oscillator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06197014A (en) * | 1992-12-25 | 1994-07-15 | Mitsubishi Electric Corp | Phase locked loop circuit |
| JP2007189638A (en) * | 2006-01-16 | 2007-07-26 | Nec Corp | Phase-locked loop |
| JP4654919B2 (en) * | 2006-01-16 | 2011-03-23 | 日本電気株式会社 | Phase synchronization circuit |
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