JPH01232792A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH01232792A JPH01232792A JP5910388A JP5910388A JPH01232792A JP H01232792 A JPH01232792 A JP H01232792A JP 5910388 A JP5910388 A JP 5910388A JP 5910388 A JP5910388 A JP 5910388A JP H01232792 A JPH01232792 A JP H01232792A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electric circuit
- semiconductive material
- insulating layer
- polymer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 25
- 229920000620 organic polymer Polymers 0.000 claims abstract description 18
- 239000011247 coating layer Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229920000642 polymer Polymers 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000011888 foil Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000003973 paint Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野）
本発明は、電子装置などの電気回路形成用として使用し
得る回路基板並びにその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a circuit board that can be used for forming electric circuits in electronic devices and the like, and a method for manufacturing the same.
〔従来技術］
最近の電子装置の小型化に伴い、各種の部品、たとえば
抵抗、コンデンサ、トランジスタ等を混成して一つの基
板上に設置し、電子的機能を実現しようとする所謂ハイ
プリントＩＣが重視されている。[Prior Art] With the recent miniaturization of electronic devices, so-called high-print ICs, which combine various components such as resistors, capacitors, transistors, etc. and install them on a single substrate to realize electronic functions, have become popular. is considered important.
従来、ハイブリッドＩＣとして、その絶縁層がアルミナ
を主体とするセラミック板製のものが主として使用され
てきたが、セラミック板は割れ易いために大サイズのも
のの製造が困難であり、また金属ヒートシンクとの接着
も工程的に複雑であるので、最近ではセラミック板に代
わってポリイミド樹脂やエポキシ樹脂等の絶縁性有機高
分子を採用する傾向にある。これら絶縁性有機高分子は
、フィルム化および金属材との接着が容易であるので、
絶縁性有機高分子フィルムの片面にヒートシンクとなる
金属材層を、残る片面に電気回路層を接着した構造等で
使用される。Conventionally, hybrid ICs made of ceramic plates whose insulating layers are mainly made of alumina have been mainly used, but ceramic plates are easily broken, making it difficult to manufacture large-sized ones, and they are difficult to manufacture with metal heat sinks. Since adhesion is also a complicated process, there has recently been a trend to use insulating organic polymers such as polyimide resins and epoxy resins instead of ceramic plates. These insulating organic polymers are easy to form into films and adhere to metal materials, so
It is used in a structure in which a metal material layer serving as a heat sink is adhered to one side of an insulating organic polymer film, and an electric circuit layer is adhered to the remaining side.
ところで回路基板の電気回路層は、予め銅、ニッケル等
の導電性金属の箔からこれを別工程で所望の回路に切断
等して仕上げたものを単に接着して形成する場合もある
が、大量生産の場合には絶縁性有機高分子フィルムの上
に導電性金属の箔を接着し、この箔層につきエンチング
処理を施して所望の形状の電気回路に仕上げる方法が採
用されている。何れの方法を採用するにせよ、電気回路
層は導電性金属箔の厚さ分だけ絶縁層表面から浮きあが
っており、即ちこの箔厚骨に対応する側面を有し、この
側面上端部、即ちエツジにおける集中電界によってコロ
ナが生じ易い構造となっている。しかも有機高分子絶縁
層は、従来のセラミック絶縁層と比較して耐コロナ性が
低い欠点があり、ために有機高分子絶縁の回路基数はコ
ロナ破壊し易い問題を孕んでいる。By the way, the electrical circuit layer of a circuit board is sometimes formed by simply gluing foil of conductive metal such as copper or nickel, which is cut into the desired circuit in a separate process and finished. In production, a method is adopted in which a conductive metal foil is adhered onto an insulating organic polymer film, and this foil layer is subjected to an etching treatment to form an electrical circuit in the desired shape. Regardless of which method is adopted, the electric circuit layer is raised from the surface of the insulating layer by the thickness of the conductive metal foil, that is, it has a side surface corresponding to the thickness of the foil, and the upper end of this side surface, i.e. The structure is such that corona is likely to occur due to concentrated electric fields at the edges. Moreover, the organic polymer insulating layer has a drawback of having lower corona resistance than the conventional ceramic insulating layer, and therefore the organic polymer insulating circuit board has the problem of being susceptible to corona destruction.
本発明は上記の問題に鑑みて、有機高分子の絶縁層を有
しながらしかも耐電圧強度の改善された回路基板並びに
その製造方法を提供することを目的とするものである。SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a circuit board having an organic polymer insulating layer and improved voltage strength, and a method for manufacturing the same.
即ち本発明は、金属基層の上に有機高分子絶縁層を有し
、更にその上に電気回路層を有する回路基板において、
当該電気回路層のエツジが半導電性材料により被覆され
ており、更に当該半導電性材料の被覆層上に有機高分子
絶縁層を有することを特徴とする回路基板に関するもの
である。That is, the present invention provides a circuit board having an organic polymer insulating layer on a metal base layer and further having an electric circuit layer thereon.
The present invention relates to a circuit board characterized in that the edges of the electric circuit layer are covered with a semiconductive material, and further includes an organic polymer insulating layer on the coating layer of the semiconductive material.
（作用並びに効果〕
電気回路層のエツジを半導電性材料により被覆すること
でその部分における電界の集中を緩和し、更に当該半導
電性材料の被覆層上に有機高分子絶縁層を設けることに
よりエツジ部の耐電圧強度を高めることによって高電圧
下での使用に際してもコロナが発生が抑えられ、このた
めに本発明の回路基板は従来品と比較して耐電圧強度が
高くなる。(Functions and Effects) By covering the edges of the electric circuit layer with a semiconductive material, the concentration of electric field in that part is alleviated, and by further providing an organic polymer insulating layer on the covering layer of the semiconductive material. By increasing the withstand voltage strength of the edge portion, the generation of corona can be suppressed even when used under high voltage, and therefore the circuit board of the present invention has a higher withstand voltage strength compared to conventional products.
第１図は、本発明の実施例の断面図を示す。第１図の実
施例において、金属基層ｌの上に有機高分子絶縁層２が
、更にその上に電気回路層３が設けられている。各層間
は、周知の接着剤を用いて接着されていても良く、ある
いは有機高分子絶縁層２を電着塗装により形成する場合
には電着塗装層がＢステージにある間に金属基層ｌ又は
電気回路層３を電着塗装層上に重ねて加熱・加圧して電
着塗装層のＣステージ化と層間接着とを同時に達成せし
めても良い。FIG. 1 shows a cross-sectional view of an embodiment of the invention. In the embodiment shown in FIG. 1, an organic polymer insulating layer 2 is provided on the metal base layer 1, and an electric circuit layer 3 is further provided thereon. The layers may be bonded using a well-known adhesive, or when the organic polymer insulating layer 2 is formed by electrodeposition coating, the metal base layer 1 or The electric circuit layer 3 may be placed on the electrodeposition coating layer and heated and pressurized to simultaneously achieve C stage formation of the electrodeposition coating layer and interlayer adhesion.
電気回路層３のエツジ部３１及び側面３２は、半導電性
材料からなる被覆層４により被覆されており、被覆層４
の上には有機高分子絶縁層５が被覆されている０本発明
においては、エツジ部３１の全体を充分に被覆層４並び
に絶縁層５にて被覆することが肝要である。これをなす
には、電気回路層３の表面３３の一部並びに側面３２の
一部をもエツジ部３１と一緒にそれら層４．５にて被覆
することが望ましい。更にエツジ部３１上の半導電性材
料からなる被覆層４は、図示する通り断面が半径Ｒを有
する円弧状あるいはそれに近い形状であることが望まし
く、その場合の半径Ｒの大きさは、少な（とも５μｌ、
特にｌＯμ端とすることが望ましい。The edge portion 31 and side surface 32 of the electric circuit layer 3 are covered with a covering layer 4 made of a semiconductive material.
In the present invention, it is important that the entire edge portion 31 is sufficiently covered with the coating layer 4 and the insulating layer 5. To accomplish this, it is desirable to cover part of the surface 33 and part of the side surface 32 of the electrical circuit layer 3 together with the edge 31 with the layer 4.5. Further, it is preferable that the covering layer 4 made of a semiconductive material on the edge portion 31 has a cross section having a radius R, as shown in the figure, or a shape close to the arc, and in this case, the size of the radius R is small ( Both 5μl,
In particular, it is desirable to set it to the lOμ end.
本発明においては、電気回路層３のエツジ部３１を順次
半導電性材料被覆層４及びａｍ、高分子絶縁層５にて被
覆することが肝要であって、電気回路層３の側面３２の
それら材料による被覆は、必ずしも必要ではないが、図
示する通りに当該部分も被覆するほうがよく、その場合
、側面３２と半導電性材料被覆層４との界面、特に側面
３２の根部にボイドが残存しがちであるので、ボイドフ
リーとなるように半導電性材料被覆層４にて側面３２の
全面を被覆することが望ましい。In the present invention, it is important to sequentially cover the edge portion 31 of the electric circuit layer 3 with the semiconductive material coating layer 4 and am, and the polymer insulating layer 5, and Covering with the material is not necessarily required, but it is better to cover the part as shown in the figure. In that case, voids may remain at the interface between the side surface 32 and the semiconductive material coating layer 4, especially at the root of the side surface 32. Therefore, it is desirable to cover the entire surface of the side surface 32 with the semiconductive material coating layer 4 so as to be void-free.
被１ｉＪｉ！ｉ４の形成に使用される半導電性材料とし
ては、体積抵抗率が１０’−１０’Ωｃｍ程度の半導電
性のもの、特に耐コロナ性に優れたものであれば種々の
化学材料を制限なく使用することができるが、エツジ部
並びに電気回路層３の側面３２をボイドフリーに能率良
くそれの層４を形成するには常温で１００〜１０．００
０ ｃｐｓ、特には５００〜５，０００ｃｐｓの範囲の
粘度を有する硬化性の液体を用いることが好ましい。そ
のような液体としてはカーボンブランク、導電性金属粉
末等を配合して半導電性化されたエポキシ樹脂、各種の
紫外線硬化性塗料、ソルダーレジスト等が挙げられる。Covered 1iJi! The semiconductive material used to form i4 may be any semiconductive material with a volume resistivity of about 10'-10' Ωcm, and various chemical materials may be used without limitation, as long as they have excellent corona resistance. However, in order to efficiently form the layer 4 of the edge portion and the side surface 32 of the electric circuit layer 3 void-free, the temperature is 100 to 10.00 at room temperature.
It is preferred to use a curable liquid having a viscosity in the range of 0 cps, especially in the range of 500 to 5,000 cps. Examples of such liquids include carbon blanks, epoxy resins made semiconductive by blending conductive metal powder, various ultraviolet curable paints, and solder resists.
それらの液体は、耐コロナ性改善のためにアルミナ、ジ
ルコニヤ等の無機わ）末を含んでいても良い。These liquids may contain inorganic powders such as alumina and zirconia to improve corona resistance.
絶縁層５の形成に使用される有機高分子絶縁材料として
は、体積抵抗率にして１０９０ｃｍ以上の高電気抵抗性
のもの、好ましくはさらに耐コロす性をも備えたもので
あれば種々の化学材料を制限なく使用することができる
。たとえばエポキシ樹脂、各種の紫外線硬化性塗料、ソ
ルダーレジスト等が挙げられる。それらの液体は、耐コ
ロナ性改善のためにアルミナ、ジルコニヤ等の無機粉末
を含んでいても良い。The organic polymer insulating material used for forming the insulating layer 5 may be one having high electrical resistance with a volume resistivity of 1090 cm or more, and preferably one having corrosion resistance as well. Materials can be used without restriction. Examples include epoxy resins, various types of ultraviolet curable paints, solder resists, and the like. These liquids may contain inorganic powders such as alumina and zirconia to improve corona resistance.
以下、本発明を具体例をもってより詳細に説明するが、
本発明はこれら具体例によって同等限定されるものでは
ない。Hereinafter, the present invention will be explained in more detail with specific examples.
The present invention is not equally limited by these specific examples.
具体例１
両面に厚さ１５μｍの接着剤層を有するポリイミドフィ
ルム（厚さ：２５μｍ）を厚さ２．０１のアルミニウム
板の上に置き、更にその上に厚さ３５μ＋ｎのＬＥ ｆ
ｔａを重ねて１７０°Ｃ１６０分、３０ｋ（４７ｃｍ”
の条件で熱プレスし、回路基板材を得た。この回路基板
材から１００＆１角片を採取し、次いでその銅箔層をエ
ツチング処理して１００ｍｍ角片の中央に３０ｍｍ角の
部分のみに銅箔層を残した多数の模擬回路基板を得た。Specific example 1 A polyimide film (thickness: 25 μm) having adhesive layers with a thickness of 15 μm on both sides is placed on an aluminum plate with a thickness of 2.01, and an LE f with a thickness of 35 μm + n is placed on top of the aluminum plate with a thickness of 2.01 μm.
160 minutes at 170°C, 30k (47cm)
A circuit board material was obtained by heat pressing under the following conditions. 100mm square pieces were taken from this circuit board material, and the copper foil layers thereof were then etched to obtain a large number of simulated circuit boards in which the copper foil layer was left only in a 30mm square part in the center of the 100mm square pieces.
各模擬回路基板試ｔ４の銅箔層のエッジ部並びに金側面
を常温における粘度が１０００ｃｐｓのエポキシ樹脂に
アセチレンブランクを混合した常温における体積抵抗率
が約１０Ωｃｍの半導電性組成物を用いて被覆し、加熱
硬化して半導電性層を形成した。当該半導電性層によっ
て被覆された銅箔層表面端部の幅は約０．２閣であり、
半導電性層のエツジ部上における断面は半径が約４μ―
の円弧に近い形状であった。また銅箔層の側面上の半導
電性層の厚さは約２０μｍであった。The edge part of the copper foil layer and the gold side surface of each simulated circuit board test T4 were coated with a semiconductive composition having a volume resistivity of approximately 10 Ωcm at room temperature, which was prepared by mixing an acetylene blank with an epoxy resin having a viscosity of 1000 cps at room temperature. , and was heated and cured to form a semiconductive layer. The width of the surface edge of the copper foil layer covered with the semiconductive layer is about 0.2 mm,
The cross section on the edge of the semiconducting layer has a radius of approximately 4μ.
The shape was close to a circular arc. Further, the thickness of the semiconductive layer on the side surface of the copper foil layer was about 20 μm.
ついでこの半導電性層の上に常温における体積抵抗率が
約１０′４Ωｃｍのエポキシ樹脂絶縁塗料を塗布し、加
熱硬化して第１図の絶縁層５のような断面図形状の絶縁
層を形成した。エツジ部上における断面円弧状の半導電
性層の上に形成された絶縁層の厚みは、約０．Ｏ１薗で
あった。Next, an epoxy resin insulating paint having a volume resistivity of about 10'4 Ωcm at room temperature is applied onto this semiconductive layer and cured by heating to form an insulating layer having a cross-sectional shape as insulating layer 5 in FIG. did. The thickness of the insulating layer formed on the semiconductive layer having an arcuate cross section on the edge portion is about 0. It was O1 Sono.
具体例２
実施例１で用いたエポキシ樹脂ヘースの半導電性組成物
の代わりに常温における粘度が４００ｃｐｓのソルダー
レジストにカーボンブランクを混合した常温における体
積抵抗率が約１０”Ωｃｍの半導電性組成物を用い、ま
たエポキシ樹脂絶縁塗料の代わりに常温における粘度及
び体積抵抗率がそれぞれ４００ｃｐｓ、約１０′２Ωｃ
ｍのソルダーレジストを使用して具体例１と同様の構造
の回路基板を得た。ただし、当該半導電性層によって被
覆された銅箔層表面端部の幅は約０．３ｍｍであり、半
導電性層のエツジ部上における断面は半径が約５μｍの
円弧に近い形状であった。また銅箔層の側面上の半導電
性層の厚さは約２０μｍであった。Specific Example 2 Instead of the semiconductive composition of epoxy resin haze used in Example 1, a semiconductive composition with a volume resistivity of about 10''Ωcm at room temperature was prepared by mixing a carbon blank with a solder resist having a viscosity of 400 cps at room temperature. The viscosity and volume resistivity at room temperature are 400 cps and about 10'2 Ωc, respectively, instead of the epoxy resin insulating paint.
A circuit board having a structure similar to that of Example 1 was obtained using a solder resist of No. m. However, the width of the surface edge of the copper foil layer covered by the semiconductive layer was about 0.3 mm, and the cross section on the edge of the semiconductive layer was close to an arc with a radius of about 5 μm. . Further, the thickness of the semiconductive layer on the side surface of the copper foil layer was about 20 μm.
具体例３
具体例１と同様の材料並びに構造のものであるが、半導
電性層によって被覆された銅箔層表面端部の幅は約０．
３＋ｎｍであり、半導電性層のエツジ部上における断面
は、厚みが約３μｍの非円弧形状であった。Specific Example 3 The material and structure are similar to those of Specific Example 1, but the width of the surface edge of the copper foil layer covered with the semiconductive layer is approximately 0.
3+nm, and the cross section on the edge portion of the semiconductive layer had a non-circular arc shape with a thickness of about 3 μm.
比較例１
具体例３とは、半導電性層および絶縁層がない点におい
て相違し、他は同一構造の回路基板を得た。Comparative Example 1 A circuit board was obtained which differed from Specific Example 3 in that it did not have a semiconductive layer and an insulating layer, but otherwise had the same structure.
具体例１〜３、比較例１の各試料につき、アルミニウム
板と銅箔層との間に常温、空気中でＡＣ２ｋＶ （６０
Ｈｚ）を課電し、絶縁破壊が生じるまでの時間即ち課電
寿命（し、単位：時間）を測定した。またその際コロナ
開始電圧（ＣＶ、単位：■）も測定した。課電寿命並び
にコロナ開始電圧の平均値（Ａｖ）および標準偏差（σ
）についての測定結果を下表に示す。For each sample of Specific Examples 1 to 3 and Comparative Example 1, AC 2 kV (60
A voltage (Hz) was applied, and the time until dielectric breakdown occurred, that is, the charging life (unit: hour) was measured. At that time, the corona onset voltage (CV, unit: ■) was also measured. Average value (Av) and standard deviation (σ
) measurement results are shown in the table below.
表table
第１図は、本発明の実施例の断面図を示す。 ｌ 金属基層 ２ 有機高分子絶縁層 ３ 電気回路層 ３１ 電気回路層３のエッジ部 ３２ を気回路層３の側面 ４ 半導電性材料からなる被覆層 ５ 有機高分子絶ｊ１層 第１図 □Ｉ FIG. 1 shows a cross-sectional view of an embodiment of the invention. l Metal base layer 2 Organic polymer insulation layer 3 Electric circuit layer 31 Edge part of electric circuit layer 3 32 side of air circuit layer 3 4 Coating layer made of semiconductive material 5 1 layer of organic polymer Figure 1 □I
Claims (1)
電気回路層を有する回路基板において、当該電気回路層
のエッジが半導電性材料により被覆されており、更に当
該半導電性材料の被覆層上に有機高分子絶縁層を有する
ことを特徴とする回路基板。In a circuit board having an organic polymer insulating layer on a metal base layer and further having an electric circuit layer thereon, an edge of the electric circuit layer is covered with a semiconductive material, and the edge of the electric circuit layer is coated with a semiconductive material. 1. A circuit board comprising an organic polymer insulating layer on a coating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5910388A JP2607906B2 (en) | 1988-03-11 | 1988-03-11 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5910388A JP2607906B2 (en) | 1988-03-11 | 1988-03-11 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01232792A true JPH01232792A (en) | 1989-09-18 |
| JP2607906B2 JP2607906B2 (en) | 1997-05-07 |
Family
ID=13103654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5910388A Expired - Lifetime JP2607906B2 (en) | 1988-03-11 | 1988-03-11 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2607906B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5194933A (en) * | 1990-10-05 | 1993-03-16 | Fuji Electric Co., Ltd. | Semiconductor device using insulation coated metal substrate |
| US5329068A (en) * | 1992-06-10 | 1994-07-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US5527604A (en) * | 1993-08-06 | 1996-06-18 | Mitsubishi Denki Kabushiki Kaisha | Metal base board and electronic equipment using the same |
| JP2020080379A (en) * | 2018-11-13 | 2020-05-28 | マイクロクラフト株式会社 | Device and method for forming film |
-
1988
- 1988-03-11 JP JP5910388A patent/JP2607906B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5194933A (en) * | 1990-10-05 | 1993-03-16 | Fuji Electric Co., Ltd. | Semiconductor device using insulation coated metal substrate |
| US5329068A (en) * | 1992-06-10 | 1994-07-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US5527604A (en) * | 1993-08-06 | 1996-06-18 | Mitsubishi Denki Kabushiki Kaisha | Metal base board and electronic equipment using the same |
| US5578367A (en) * | 1993-08-06 | 1996-11-26 | Mitsubishi Denki Kabushiki Kaisha | Metal base board and electronic equipment using the same |
| US5670241A (en) * | 1993-08-06 | 1997-09-23 | Mitsubishi Denki Kabushiki Kaisha | Metal base board and electronic equipment using the same |
| US5820972A (en) * | 1993-08-06 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Metal base board and electronic equipment using the same |
| US5834101A (en) * | 1993-08-06 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Metal base board and electronic equipment using the same |
| DE4427994C2 (en) * | 1993-08-06 | 2000-10-26 | Mitsubishi Electric Corp | Metal core substrate, especially for use in electronic circuits |
| JP2020080379A (en) * | 2018-11-13 | 2020-05-28 | マイクロクラフト株式会社 | Device and method for forming film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2607906B2 (en) | 1997-05-07 |
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