JPH01222497A - Multilayer printed wiring board and manufacture thereof - Google Patents
Multilayer printed wiring board and manufacture thereofInfo
- Publication number
- JPH01222497A JPH01222497A JP4843788A JP4843788A JPH01222497A JP H01222497 A JPH01222497 A JP H01222497A JP 4843788 A JP4843788 A JP 4843788A JP 4843788 A JP4843788 A JP 4843788A JP H01222497 A JPH01222497 A JP H01222497A
- Authority
- JP
- Japan
- Prior art keywords
- prepreg
- thickness
- printed wiring
- base material
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000463 material Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 abstract description 31
- 239000011229 interlayer Substances 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 5
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 239000004744 fabric Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000007731 hot pressing Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 239000011889 copper foil Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、必要な特性インピーダンスを効率良く実現で
きる多層プリント配線板およびその＠進方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multilayer printed wiring board that can efficiently realize a required characteristic impedance, and a method thereof.
（従来の技術）
近年、特にプリント配線板が多層化する一方、高密度化
され、搭載される素子も低消費電力、信号の高速化が行
なわれてきているため、伝送線路の特性インピーダンス
の整合が非常に重要になってきている。すなわち、この
特性インピーダンスが設計値より高い場合、入力信号は
反射を起こし、雑音として回路に悪影響を与える。逆に
設計値よりも低い場合には素子の破壊に繋がる。(Prior art) In recent years, printed wiring boards have become more multi-layered, have higher density, and are equipped with lower power consumption and faster signal speeds, so it is becoming increasingly important to match the characteristic impedance of transmission lines. is becoming extremely important. That is, if this characteristic impedance is higher than the designed value, the input signal will be reflected, which will adversely affect the circuit as noise. On the other hand, if it is lower than the design value, it will lead to destruction of the element.
従来は、高周波信号あるいはパルス信号を扱うプリント
配線板では、信号導体の特性インピーダンスをできるだ
け均一にして信号の反射を防止することにより、伝送特
性の劣化に対処していた。Conventionally, in printed wiring boards that handle high-frequency signals or pulse signals, deterioration in transmission characteristics has been dealt with by making the characteristic impedance of the signal conductor as uniform as possible to prevent signal reflection.
すなわち、高周波線路でのプリント配線板は、その伝送
線路構造に２種類の構造型式があり、第２図で示すマイ
クロストリップ線路と、第３図で示すストリップ線路で
あり、これらいずれの線路においても特性インピーダン
スは導体幅Ｗ、導体厚みｔ、絶縁体厚みり、実効比誘電
率εｒｅにより決定され、第２図で示すマイクロストリ
ップ線路では、この特性インピーダンスＺｏは
で与えられ、第３図のストリップ線路における特性イン
ピーダンスＺｏは
で与えられる。In other words, printed wiring boards for high-frequency lines have two types of transmission line structures: the microstrip line shown in Figure 2 and the strip line shown in Figure 3. The characteristic impedance is determined by the conductor width W, the conductor thickness t, the insulator thickness, and the effective relative permittivity εre.In the microstrip line shown in FIG. 2, this characteristic impedance Zo is given by, and in the strip line shown in FIG. The characteristic impedance Zo at is given by.
このようなものとして、特開昭４９−６８２６４号公報
に開示されているように、配線ラインの幅が、ライン上
の負荷の間隔または負荷の大きざに応じて変化せしめら
れ、その見かけ上の特性インピーダンスが一様になるよ
うにする。技術、または、実開昭５２−２１５３号公報
に開示されているように、接地層の片側に二層以上の信
号層がある場合に、それぞれの層の導体幅を変え、特性
インピーダンスが一定になるようにする技術が知られて
いる。As disclosed in Japanese Patent Application Laid-Open No. 49-68264, the width of the wiring line is changed depending on the interval between the loads on the line or the size of the loads, so that the apparent Ensure that the characteristic impedance is uniform. As disclosed in Japanese Utility Model Application Publication No. 52-2153, when there are two or more signal layers on one side of the ground layer, the conductor width of each layer is changed to keep the characteristic impedance constant. There are known techniques to make this happen.
（発明が解決しようとする問題点）
しかしながら、現状ではこの特性インピーダンスは設定
値通りに実現させることができず、最も好ましい場合で
も平均誤差±２０％が生じる。(Problems to be Solved by the Invention) However, under the present circumstances, this characteristic impedance cannot be realized according to the set value, and even in the most preferable case, an average error of ±20% occurs.
この要因としては、導体幅Ｗのバラツキと、絶縁体厚み
ｈのバラツキが考えられる。例えば、第３図で示すスト
リップ線路においては、例えば特性インピーダンスの設
定値Ｚｏ ＝５５ （Ω）に対して、導体幅Ｗの±１０
％の変化により±５（Ω）の特性インピーダンスの変化
が表われる。Possible causes of this include variations in the conductor width W and variations in the insulator thickness h. For example, in the strip line shown in FIG.
A change in characteristic impedance of ±5 (Ω) appears due to a change in %.
また、層間厚みの±１０％の変化が同様のストリップ線
路における特性インピーダンスＺｏに±６（Ω）の変化
を生じさせることがシミュレーションの結果判明した。Furthermore, the simulation results revealed that a ±10% change in interlayer thickness causes a ±6 (Ω) change in the characteristic impedance Zo of a similar strip line.
従って、特性インピーダンスを整合させるために、導体
幅ヲｏ、 ２０１１１１１１． 層間厚みを０．６０ｍ
ｍに設定した場合、ライン幅のバラツキは０．２０±０
．０２ｍｍ、また、ｍｌ厚みのバラツキは０゜６０±０
．０６ｍ１ｌ１以内に抑えることが必要であるにもかか
わらず、現状の製造工程を考えると、この誤差範囲内で
多層プリント配線板を製作することは極めて困難であっ
た。Therefore, in order to match the characteristic impedance, the conductor width is 20111111. Interlayer thickness 0.60m
When set to m, the variation in line width is 0.20±0
．． 02mm, and the variation in ml thickness is 0°60±0
．． Although it is necessary to suppress the error within this error range, considering the current manufacturing process, it is extremely difficult to manufacture a multilayer printed wiring board within this error range.
本発明は上記問題点を解決するためになされ、必要な特
性インピーダンスを効率良く実現できる多層プリント配
線板とその製造方法に関するものである。The present invention was made to solve the above-mentioned problems, and relates to a multilayer printed wiring board that can efficiently realize the required characteristic impedance, and a method for manufacturing the same.
（課題を解決するための手段）
本発明の第１の請求項は電源層と、銅張基材に形成され
た信号層との間にプリプレグを介在させた多層プリント
配線板において、
前記銅張基材およびプリプレグのトータル厚みの３分の
２以上を銅張基材により占有させたことを特徴とする多
層プリント配線板である。(Means for Solving the Problems) A first aspect of the present invention provides a multilayer printed wiring board in which a prepreg is interposed between a power supply layer and a signal layer formed on a copper-clad base material, wherein the copper-clad base material and the prepreg A multilayer printed wiring board characterized in that two-thirds or more of the total thickness of the board is occupied by a copper-clad base material.
本発明の第２の請求項は銅張基材に形成された信号層の
有効ライン幅として、導体の上片幅寸法を基準としたこ
とを特徴とする第１の請求項の多層プリント配線板の製
造方法である。The second claim of the present invention is the production of the multilayer printed wiring board according to the first claim, wherein the effective line width of the signal layer formed on the copper-clad base material is based on the upper width dimension of the conductor. It's a method.
第１の請求項は、一定の特性インピーダンスＺＯを整合
させるために、層間距離の２／３以上を銅張積層板で形
成すること、言替えれば、プリプレグの厚さを可能な限
り薄く、好ましくは０．１〜０．０５＋１１（ＩＩにす
ることにより、層間厚みのバラツキを少なくするという
ものである。この際、層間プリプレグ厚さを薄クシたた
め、ボイドの発生が考えられるが、これを避けるため、
層間接着には真空プレスを使用すれば、層間距離の一層
の安定を図ることが可能となる。第２の請求項において
は、第１の請求項の多層プリント配線板を製造する際に
、導体ライン幅の管理、すなわちフォトマスク等の治工
具設計の基準を導体の上辺幅寸法にとることである。The first claim is that, in order to match a certain characteristic impedance ZO, 2/3 or more of the interlayer distance is formed of a copper-clad laminate, in other words, the thickness of the prepreg is preferably made as thin as possible. is 0.1 to 0.05 + 11 (II) to reduce the variation in interlayer thickness.At this time, since the interlayer prepreg thickness is thinned, voids may occur, but this should be avoided. For,
If a vacuum press is used for interlayer adhesion, it is possible to further stabilize the interlayer distance. In the second claim, when manufacturing the multilayer printed wiring board of the first claim, it is possible to manage the conductor line width, that is, to take the upper side width dimension of the conductor as the standard for designing jigs such as photomasks. be.
一般に多層プリント配線板において、導体ライン幅は第
４図のｂ値（導体１の下辺幅寸法）を基準としているが
、エツチングにはアンダーカットが常に発生するため、
仕上りライン幅としてｂ値を基準にとると、ライン幅の
バラツキが大きくなる。そこでｂ値に対応させる意味で
、導体１の上辺幅寸法をａ値とした場合、例えば、５０
μｍの銅箔でライン幅０．２０ｍ１ｌをエツチング処理
して回路を作成すれば、ｂ値はσ＝０．０２、ａ値はσ
＝０．０１ （ｎ−１００）となり、ｂ値はａ値の２倍
のバラツキがある。Generally, in multilayer printed wiring boards, the conductor line width is based on the b value (lower side width dimension of the conductor 1) shown in Fig. 4, but since undercuts always occur during etching,
If the b value is used as the standard for the finished line width, the variation in line width will increase. Therefore, in order to correspond to the b value, if the upper side width dimension of the conductor 1 is set as the a value, for example, 50
If a circuit is created by etching a line width of 0.20ml with μm copper foil, the b value is σ = 0.02 and the a value is σ
=0.01 (n-100), and the b value has twice the variation as the a value.
従って、ａ値を導体１のライン幅の基準にとれば、理論
値との極端な特性インピーダンスＺｏの差異がなくなり
、また、フォトマスク等の治工具も容易に設計しやすく
なる。Therefore, if the a value is taken as the standard for the line width of the conductor 1, there will be no extreme difference in the characteristic impedance Zo from the theoretical value, and it will also be easier to design jigs and tools such as photomasks.
次に、（作用）
第１の請求項においては、特性インピーダンスＺｏに大
きく影響を与える層間厚ざについては、一般に、多層プ
リント配線板においては、層間接着にガラス布基材にエ
ポキシ樹脂やポリイミド樹脂を含浸させたプリプレグを
使用し、加熱加圧により多層化しているが、この際使用
するプリプレグは積層プレス時のボイド発生防止から０
．２０〜０．３０１１１ｍ以上の厚さが適当とされてい
た。ところが、プリプレグの厚さがＯ； ２０〜０．３
０ｍｍ以上になると、積層プレス時の樹脂流れのバラツ
キにより、設定値の±１０％の公差が許容されてしまう
のである（ ＩＰＣ−ＭＬ−９１０）が、本発明によっ
て、層間プリプレグ厚さを薄クシ、層間厚ざは銅張積層
板で確保する（層間のトータル厚みの３分の２以上）こ
とにより、層間厚ざの積層プレス時での変化率を極力抑
えることができ、一定の特性インピーダンスを実現する
上に非常に有効となる。Next, (Function) In the first claim, regarding the interlayer thickness which greatly affects the characteristic impedance Zo, in general, in multilayer printed wiring boards, epoxy resin or polyimide resin is used on the glass cloth base material for interlayer adhesion. The prepreg impregnated with
．． A thickness of 20 to 0.30111 m or more was considered appropriate. However, the thickness of the prepreg is O; 20~0.3
If the thickness exceeds 0 mm, a tolerance of ±10% of the set value is allowed due to variations in resin flow during lamination pressing (IPC-ML-910), but with the present invention, the thickness of the interlayer prepreg can be reduced by thinning. By ensuring the interlayer thickness difference with copper-clad laminates (2/3 or more of the total interlayer thickness), the rate of change in interlayer thickness during lamination pressing can be suppressed as much as possible, and a constant characteristic impedance can be maintained. This will be very effective in achieving this.
また、第２の請求項の製造方法によって、本発明による
多層プリント配線板は、信号層の有効ライン幅として、
導体の上片幅寸法を基準としたため、特性インピーダン
スとともに導体抵抗の上限値をも管理することが可能と
なる。Further, according to the manufacturing method of the second claim, the multilayer printed wiring board according to the present invention has an effective line width of the signal layer.
Since the upper width dimension of the conductor is used as the standard, it is possible to manage the upper limit value of the conductor resistance as well as the characteristic impedance.
（実施例の説明）
以下、本発明に係る多層プリント配線板の実施例につい
て、添付図面を参照しながら詳細に説明する。本発明の
実施例としては、１４層多層プリント配線板で、信号層
が６層、ストリップ構造をとるタイプのものに適用し、
第１図はその要部断面図を示すものである。(Description of Examples) Hereinafter, examples of the multilayer printed wiring board according to the present invention will be described in detail with reference to the accompanying drawings. As an embodiment of the present invention, it is applied to a 14-layer multilayer printed wiring board with 6 signal layers and a strip structure,
FIG. 1 shows a sectional view of the main part thereof.
すなわち、本例の多層プリント配線板１０は、電源層１
１−グラウンド層、１１間に２層の信号層１２を有し、
この多層プリント配線板１０の特性インピーダンスＺｏ
の要求値は５５±１０％（Ω）であり、全板厚は２．６
４ｍｍである。That is, the multilayer printed wiring board 10 of this example has a power supply layer 1
1-ground layer, 11 has two signal layers 12 between them,
Characteristic impedance Zo of this multilayer printed wiring board 10
The required value is 55 ± 10% (Ω), and the total plate thickness is 2.6
It is 4mm.
さらに、電源層（グラウンド層）１１間に積層される基
材１３として、厚み０．２ｍｍの両面銅張板例えばＭＣ
Ｌ−Ｅ−６７（日立化成工業（株）製造）を使用し、信
号層１２としての銅箔の厚みは５０μｍに形成されてお
り、かつ、この信号層１２のライン幅は第４図中ａで示
す導体の上片幅を基準としている。すなわち、この信号
層１２の上片のネガ値は０．２４±Ｑ、Ｑ２ｍｍ、 工
ｙチング後のａ値は０．２０±０．０２ＩＩＩＩ１１ニ
ナルヨウニサブトラトク法で内層回路を形成する。その
後、信号層１２としての銅箔表面の酸化処理を行ない、
第１図で示す基材１３を積層プレス加工を行なう。Furthermore, as a base material 13 laminated between the power supply layers (ground layers) 11, a double-sided copper clad plate with a thickness of 0.2 mm, for example, MC.
L-E-67 (manufactured by Hitachi Chemical Co., Ltd.) is used, the thickness of the copper foil as the signal layer 12 is 50 μm, and the line width of the signal layer 12 is a in FIG. The width of the top half of the conductor shown in is the standard. That is, the negative value of the upper piece of this signal layer 12 is 0.24±Q, Q2mm, and the a value after machining is 0.20±0.02. The inner layer circuit is formed by the subtractive method. After that, the surface of the copper foil as the signal layer 12 is oxidized,
The base material 13 shown in FIG. 1 is laminated and pressed.
このとき、電源層（グラウンド層）１１に挟まれる構造
のストリップ線路の層間厚ざＡを０．６層ｍｍに設定し
、かつ基材１３，１３＝の厚みを前述したように０．２
０ｍｍ、信号１１１２の銅箔厚みを０．０５順にそれぞ
れ設定し、層間接着用プリプレグ１４として、ＧＥＡ−
６７Ｎ （日立化成工業（株）製造）を使用する。なお
、このプリプレグ１４の厚みは０．０５順である。At this time, the interlayer thickness A of the strip line sandwiched between the power supply layer (ground layer) 11 is set to 0.6 mm, and the thickness of the base materials 13 is set to 0.2 mm as described above.
0 mm, and the copper foil thickness of signal 1112 was set in order of 0.05, and GEA-
67N (manufactured by Hitachi Chemical Co., Ltd.) is used. Note that the thickness of this prepreg 14 is in the order of 0.05.
なお、基材１３の積層プレス工法として、真空プレス工
法を使用するが、加工条件としては、３０Ｔｏｒｒの減
圧下において、１７０℃、１，５ｈｒの条件で行なう。Note that a vacuum press method is used as the lamination press method for the base material 13, and the processing conditions are 170° C. and 1.5 hours under a reduced pressure of 30 Torr.
この真空プレス法によりプリプレグ１４にボイドの発生
は見られず、ざらに基材１３の厚さは０．２０±０．０
２ｍｍで仕上がっており、積層後のプリプレグ１４の厚
さは０．１±ｏ、ｏｉｍｍ範囲内でバランいてはいるも
のの、トータル層間厚さのバラツキは０．６０±０．０
５ｍｍ以内に抑えることが可能となった。Due to this vacuum pressing method, no voids were observed in the prepreg 14, and the thickness of the base material 13 was roughly 0.20±0.0.
The thickness of the prepreg 14 after lamination is 0.1±o, and although it is balanced within the oimm range, the variation in the total interlayer thickness is 0.60±0.0.
It became possible to suppress the distance to within 5 mm.
そして、基材１３の積層後は、通常の多層配線板の工程
と同様に、穴明は工程、メツキ工程、外層回路形成工程
、外形加工工程を行ない最終製品を得る。After the base material 13 is laminated, the final product is obtained by performing a drilling process, a plating process, an outer layer circuit forming process, and an external shaping process in the same manner as in the process of ordinary multilayer wiring boards.
本例の多層プリント配線板１０の１フイートのライン長
の特性インピーダンスＺｏの測定ラインを設け、実際、
電源層（グラウンド層）１１の特性インピーダンスＺｏ
＠ＴＤＲ（丁ｔｍｅ ｏｏｍａｔｎ ｔｔｅｆｌｅｃｔ
ｌｌｌｅｔｅｒ）（横河ヒューレットパッカード社製造
）で測定した結果、本例の特性インピーダンスの要求値
５５（Ω）±１０％に対して、総測定数ｎ＝６（層）Ｘ
１６（ロット筒数）Ｘ２００ ＣＰＮ数）＝１９２００
本において、特性インピーダンスＺｏ ＝５０〜６０Ω
以内であることを確認した。A line for measuring the characteristic impedance Zo of 1 foot line length of the multilayer printed wiring board 10 of this example is provided, and in fact,
Characteristic impedance Zo of power layer (ground layer) 11
@TDR (Dingtme oomatn tteflect
lleter) (manufactured by Yokogawa Hewlett-Packard), the total number of measurements n = 6 (layers)
16 (number of cylinders in lot) x 200 number of CPN) = 19200
In the book, characteristic impedance Zo = 50~60Ω
It was confirmed that it was within the range.
（効果）
以上説明してきたように本発明による多層プリント配線
板によれば、
■回路の一定の特性インピーダンスＺｏの実現を容易に
行なうことができ、±１０％以内の誤差範囲で多層プリ
ント配線板の特性インピーダンスＺｏを制御することが
可能となる。(Effects) As explained above, according to the multilayer printed wiring board according to the present invention, ■ It is possible to easily realize a constant characteristic impedance Zo of the circuit, and the multilayer printed wiring board can be manufactured within an error range of ±10%. It becomes possible to control the characteristic impedance Zo.
■信号層のライン幅をその上片幅を基準としたため、直
流導体抵抗の上限値を抑えることが可能となる。■Since the line width of the signal layer is based on the width of one side of the line, it is possible to suppress the upper limit of the DC conductor resistance.
■層間厚さのバラツキを小さく抑えることができるため
、結果的に多層プリント配線板の板厚公差を小さくする
ことが可能となる等の種々の効果を有する。(2) Variations in interlayer thickness can be suppressed, resulting in various effects such as making it possible to reduce the board thickness tolerance of a multilayer printed wiring board.
第１図は本発明に係る多層プリント配線板の要部を示す
断面図、第２図はプリント配線板におけるマイクロスト
リップ構造を示す断面図、第３図はプリント配線板にお
けるストリップ構造を示す断面図、第４図はエツチング
後の導体層の一般例を示す断面図である。
１０・・・多層プリント配線板
１１・・・電源層（グラウンド層）
１２・・・信号層
１３・・・基材
１４・・・プリプレグ
フイ、７′・
代理人 弁理士 廣 瀬 章（′、−・°′１・ 。Fig. 1 is a sectional view showing the main parts of a multilayer printed wiring board according to the present invention, Fig. 2 is a sectional view showing a microstrip structure in the printed wiring board, and Fig. 3 is a sectional view showing the strip structure in the printed wiring board. , FIG. 4 is a sectional view showing a general example of a conductor layer after etching. 10...Multilayer printed wiring board 11...Power layer (ground layer) 12...Signal layer 13...Base material 14...Prepreg wire, 7'・Agent Patent attorney Akira Hirose (', −・°′1・ .
Claims (2)
リプレグを介在させた多層プリント配線板において、 前記銅張基材およびプリプレグのトータル厚みの３分の
２以上を銅張基材により占有させたことを特徴とする多
層プリント配線板。1. In a multilayer printed wiring board in which a prepreg is interposed between a power supply layer and a signal layer formed on a copper-clad base material, two-thirds or more of the total thickness of the copper-clad base material and prepreg is occupied by the copper-clad base material. Features multilayer printed wiring board.
、導体の上片幅寸法を基準としたことを特徴とする請求
の範囲第１項記載の多層プリント配線板の製造方法。2. 2. The method of manufacturing a multilayer printed wiring board according to claim 1, wherein the effective line width of the signal layer formed on the copper-clad base material is based on the upper width dimension of the conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4843788A JPH01222497A (en) | 1988-03-01 | 1988-03-01 | Multilayer printed wiring board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4843788A JPH01222497A (en) | 1988-03-01 | 1988-03-01 | Multilayer printed wiring board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01222497A true JPH01222497A (en) | 1989-09-05 |
Family
ID=12803329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4843788A Pending JPH01222497A (en) | 1988-03-01 | 1988-03-01 | Multilayer printed wiring board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01222497A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0519827A2 (en) | 1991-06-18 | 1992-12-23 | New Media Development Association | Metaphor selecting/switching system in information processors |
-
1988
- 1988-03-01 JP JP4843788A patent/JPH01222497A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0519827A2 (en) | 1991-06-18 | 1992-12-23 | New Media Development Association | Metaphor selecting/switching system in information processors |
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