JPH01214197A - Printed-wiring board - Google Patents
Printed-wiring boardInfo
- Publication number
- JPH01214197A JPH01214197A JP3993988A JP3993988A JPH01214197A JP H01214197 A JPH01214197 A JP H01214197A JP 3993988 A JP3993988 A JP 3993988A JP 3993988 A JP3993988 A JP 3993988A JP H01214197 A JPH01214197 A JP H01214197A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- land
- hole
- component
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 56
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 238000005476 soldering Methods 0.000 abstract description 9
- 238000004806 packaging method and process Methods 0.000 abstract 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はプリント配線板のスルーホールの内周面を除
く部品面または半田面のスルーホールのランドに部品面
側ランドレジスト層または半田面側ランドレジスト層を
設けたものである。[Detailed Description of the Invention] [Industrial Application Field] This invention provides a land resist layer on the component surface side or a solder surface side on the land of the through hole on the component surface or solder surface other than the inner peripheral surface of the through hole of a printed wiring board. A land resist layer is provided.
第３図＋７）ｆａ １ｆｂ）および第４図ノ［ａｌｔｂ
ｌｃ ）は従来のプリント配線基板への電気部品の取付
は状態を示し。Figure 3+7) fa 1fb) and Figure 4 [altb
lc) indicates the state of mounting electrical components on a conventional printed wiring board.
これらの図において１１１は基板（イ）に設けた多数の
スルーホールの内周面、（２１は各スルーホールの内周
面を覆う導電層、（３）はこの導電層（２）を除く範囲
に半田が付着しないように部品面側の表面を覆う部品面
側レジスト層、第４図の（４）は部品面の反対面側にな
る半田面の表面を覆うレジスト層、（７１はリード線を
有しない、いわゆる面実装部品、（団はこの面実装部品
（７）の電極を取付けるための半田ランドで隣設導電層
（２）と一連になっている。（９）はｔ配置実装部品（
７）と半田ランド（８）とを電気的に接続するための半
田、第４図のαＧはリード線（＋ Ｏａ）を有する。い
わゆるリード部品、αυはこのリード線（１Ｏａ）
の接続半田、１１３は１記接続半田αυのはみ出しによ
る隣設導電層（２）相互の短絡部を示す。In these figures, 111 is the inner peripheral surface of a large number of through holes provided in the substrate (A), (21 is a conductive layer covering the inner peripheral surface of each through hole, and (3) is the range excluding this conductive layer (2). (4) in Figure 4 is a resist layer that covers the surface of the solder side opposite to the component side, (71 is a lead wire) This is a so-called surface mount component that does not have a surface mount component (7), which is connected to the adjacent conductive layer (2) with a solder land for attaching the electrode of this surface mount component (7). (9) is a t-configuration component. (
7) and the solder land (8), αG in FIG. 4 has a lead wire (+Oa). The so-called lead part, αυ, is this lead wire (1Oa)
The connecting solder 113 indicates a short circuit between adjacent conductive layers (2) due to protrusion of the connecting solder αυ described in 1 above.
を記第３図のものは面実装部品（７）を半田ランド（８
）に電気的に接続するための半田（９）は、予めＥ記半
田ランド（８）に半田ペーストとして塗布されており、
熱溶融により電気的に接続されるものであるが、このと
き隣設スルーホールの導電層（２ンと半田ランド（８）
とが図示のように一連に接続されて、その間に部品面側
レジスト層（３）が存在しない場合は。The one in Figure 3 shows the surface mount component (7) connected to the solder land (8).
) is applied as a solder paste to the solder land (8) marked E in advance.
Electrical connection is made by thermal melting, but at this time the conductive layer (2) of the adjacent through hole and the solder land (8)
and are connected in series as shown in the figure, and there is no component side resist layer (3) between them.
半田（９）が図示のように隣設スルーホール内へ流れこ
み、その結果肝心の接続個所での半田不足を起し面実装
部品（７）は半田付不良を発生する。As shown in the figure, the solder (9) flows into the adjacent through hole, resulting in insufficient solder at the critical connection point, resulting in soldering failure in the surface mount component (7).
一方第４図のものでは半田面におけるリード部品Ｏ１の
半田付は９面実装部品（７）およびリード部品ＣＩＧを
それぞれ実装した後、予め半田を融解させた槽に基板（
イ）の半田面側をひたすことにより行なうのであるが、
このときリード線（１Ｏａ ） の接続半田αυのは
み出しにより図示のように隣設導電層（２）間に短絡部
Ｃ１２を生じさせる場合がある。On the other hand, in the case of Fig. 4, the soldering of the lead component O1 on the solder surface is performed after mounting the 9-sided mounting component (7) and the lead component CIG, respectively, and then placing the board (
This is done by soaking the solder side of (a).
At this time, the protrusion of the connection solder αυ of the lead wire (10a) may cause a short circuit C12 between adjacent conductive layers (2) as shown in the figure.
この発明はと記の問題点を解消するよう部品面側での他
への流れこみ半田による電気部品の半田付不良および半
田面側でのはみ出し半田による隣設導電層間のショート
を防止することを目的とする。In order to solve the above-mentioned problems, this invention aims to prevent poor soldering of electrical components due to solder flowing into other parts on the component side and short circuit between adjacent conductive layers due to solder protruding from the solder side. purpose.
この発明の場合は先ず第１に部品面の各スルーホールの
ランドにスルーホールの内周面を除く範囲に半田が付着
しないように，該部に部品側ランドレジスト層（５）を
それぞれ設ける。In the case of the present invention, first, a component-side land resist layer (5) is provided on each land of each through-hole on the component surface to prevent solder from adhering to the area other than the inner peripheral surface of the through-hole.
第２には半田面の各スルーホールのランドにスルーホー
ルの内周面を除く範囲に半田が付着しないように，該部
に半田面側ランドレジスト層（６）を設ける。Second, a land resist layer (6) on the solder side is provided on the land of each through hole on the solder side so that solder does not adhere to the area other than the inner peripheral surface of the through hole.
この発明の場合は各スルーホールのランドに設けた部品
面側ランドレジスト層および半田面側ランドレジスト層
は、それぞれ隣設されたスル−ホール相互間およびスル
ーホールと電気部品との間の壁となり。In the case of this invention, the component side land resist layer and the solder side land resist layer provided on the land of each through hole serve as walls between adjacent through holes and between the through hole and the electrical component, respectively. .
（１）部品面側の電気部品からスルーホールへの半田の
流れこみが阻止され、半田不足による当該電気部品の半
田付不良を防止する。(1) Solder is prevented from flowing into the through hole from the electrical component on the component side, thereby preventing poor soldering of the electrical component due to insufficient solder.
（２）半田面側の隣設導電層に対するリード線からの沿
面距離を広げ、はみ出し半田による導電層相互のショー
トを防止する。(2) The creepage distance from the lead wire to the adjacent conductive layer on the solder surface side is increased to prevent short-circuits between the conductive layers due to protruding solder.
以下この発明の一実施例について説明する。すなオ）ち
第１図および第２図において第３図および第４図のもの
と同一個所は同一符号を付してその重複説明は省略する
ことにするが、第１図の（５）は実装部品（７）が取付
けられる部品面のスルーホールのランドにスルーホール
の内周面＋１１を除＜範囲に半田が付着しないように，
該部に設けられた部品面側ランドレジスト層、第２図の
（６）はリード部品ａＧが取付けられる半田面のスルー
ホールのランドに、スルーホールの内周面＋１１を除く
範囲に半田が付着しないように，該部に設けられた半田
面側ランドレジスト層で、これらの存在にこの発明の特
徴を有するものである。An embodiment of this invention will be described below. In other words, the same parts in Figures 1 and 2 as those in Figures 3 and 4 will be given the same reference numerals and redundant explanation will be omitted, but (5) in Figure 1 To prevent solder from adhering to the land of the through hole on the component surface where the mounted component (7) is attached, excluding the inner peripheral surface of the through hole +11,
The land resist layer on the component surface side provided in this part, (6) in Fig. 2, shows that solder adheres to the land of the through hole on the solder surface to which the lead component aG is attached, except for the inner peripheral surface +11 of the through hole. The land resist layer on the solder surface side is provided in this portion to prevent the solder from forming, and the feature of the present invention lies in the presence of these layers.
すなわち第１図のものにおいては面実装部品（７）を取
付ける半田ランド（８）と隣設されたスルーホールのラ
ンドに、その内周面＋１１を除く範囲に半田＋９）が付
着しないように部品面側ランドレジスト層（５）が設け
られているため、ｈ記半田（９）が隣設スルーホール内
へ流れこむのを防ぎ、接続個所での半田不足による面実
装部品（７）の半田付は不良を防止する。In other words, in the case of the one in Figure 1, the solder land (8) for attaching the surface mount component (7) and the land of the through hole adjacent to the land of the through-hole are made so that the solder +9) does not adhere to the area other than the inner circumferential surface +11 of the solder land (8). Since the surface side land resist layer (5) is provided, it prevents the solder (9) listed in h from flowing into the adjacent through hole, and prevents soldering of the surface mount component (7) due to insufficient solder at the connection point. prevents defects.
また第２図のものにおいてはリード部品αＧのリード線
（１Ｏａ ） を取付けるスルーホールと隣接されたス
ルーホールのランドに、半田側ランドレジスト層り６）
が設けられているため半田デイツプ時の沿面距離が長（
なり、隣設スルーホール間の半田ブリッジが防止される
ことになる。In addition, in the one shown in Fig. 2, a solder side land resist layer 6) is applied to the land of the through hole adjacent to the through hole for attaching the lead wire (10a) of the lead component αG.
is provided, so the creepage distance during solder dip is long (
Therefore, solder bridging between adjacent through holes is prevented.
この発明のプリント配線板は以とのように構成されてい
るので１部品面での他への流れこみ半田による半田付不
良ならびに半田面でのはみ出し半田による隣設導電層間
の半田ブリッジが防止され。Since the printed wiring board of the present invention is constructed as follows, poor soldering due to solder flowing into other parts from one component side and solder bridging between adjacent conductive layers due to solder protruding from the solder side can be prevented. .
これらにより不良品の発生を大幅に減らし、信頼性の高
い製品が得られるという効果がある。These have the effect of significantly reducing the occurrence of defective products and producing highly reliable products.
第１図の１ａ）ｉｂ）は面実装部品の取付は状態を示す
この発明の一実施例を示すプリント配線板の断面図およ
び平面図、第２図の（ａｌｂｌｃ）はリード部品の取付
は状態を示すこの発明の一実旌例を示すプリント配線板
の断面図、平面図および背面図、第３図の（ａｌｆｂｌ
は第１図に相当する従来のプリント配線板を示す同様の
図、第４図のｆａＸｂ）［ｃ）は第２図に相当する従来
のプリント配線板を示す同様の図である。
なお図中（イ）は基板、１１１は内周面、（５）は部品
面側ランドレジスト層、（６）は半田面側ランドレジス
ト層、（７）は面実装部品、αＧはリード部品である。
その他図中同−符号は同一部分を示すものとする。1a) ib) in FIG. 1 shows the state in which surface-mounted components are mounted. A cross-sectional view and a plan view of a printed wiring board showing an embodiment of the present invention, and (alblc) in FIG. 2 shows the state in which lead components are mounted. A sectional view, a top view, and a back view of a printed wiring board showing one practical example of the present invention, and (alfbl
is a similar diagram showing a conventional printed wiring board corresponding to FIG. 1, and faXb) [c) of FIG. 4 is a similar diagram showing a conventional printed wiring board corresponding to FIG. 2. In the figure, (a) is the board, 111 is the inner peripheral surface, (5) is the land resist layer on the component side, (6) is the land resist layer on the solder side, (7) is the surface mount component, and αG is the lead component. be. In other figures, the same reference numerals indicate the same parts.
Claims (2)
スルーホールのランドに，スルーホールの内周面を除く
範囲に半田が付着しないように，該部に部品面側ランド
レジスト層を設けたプリント配線板。(1) A printed circuit board with a land resist layer on the component surface side to prevent solder from adhering to the land of the through hole on the component surface where the surface mount component is attached, except for the inner peripheral surface of the through hole. wiring board.
スルーホールのランドに，スルーホールの内周面を除く
範囲に半田が付着しないように，該部に半田面側ランド
レジスト層を設けたプリント配線板。(2) Printed wiring with a land resist layer on the solder side of the board to prevent solder from adhering to the land of the through hole on the solder side where the lead component is attached, except for the inner peripheral surface of the through hole. Board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3993988A JPH01214197A (en) | 1988-02-23 | 1988-02-23 | Printed-wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3993988A JPH01214197A (en) | 1988-02-23 | 1988-02-23 | Printed-wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01214197A true JPH01214197A (en) | 1989-08-28 |
Family
ID=12566917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3993988A Pending JPH01214197A (en) | 1988-02-23 | 1988-02-23 | Printed-wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01214197A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0492684U (en) * | 1990-12-28 | 1992-08-12 | ||
| JPH0555580U (en) * | 1991-12-20 | 1993-07-23 | 株式会社三協精機製作所 | Printed board |
-
1988
- 1988-02-23 JP JP3993988A patent/JPH01214197A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0492684U (en) * | 1990-12-28 | 1992-08-12 | ||
| JPH0555580U (en) * | 1991-12-20 | 1993-07-23 | 株式会社三協精機製作所 | Printed board |
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