JPH01214126A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01214126A JPH01214126A JP63041157A JP4115788A JPH01214126A JP H01214126 A JPH01214126 A JP H01214126A JP 63041157 A JP63041157 A JP 63041157A JP 4115788 A JP4115788 A JP 4115788A JP H01214126 A JPH01214126 A JP H01214126A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- wirings
- protective film
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 14
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000010521 absorption reaction Methods 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 abstract description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に集積回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor devices, and particularly to integrated circuits.
従来、この種の半導体装置は、素子を構成する配線の上
に半導体装置を保護するための絶縁膜で覆われた層で形
成されている。Conventionally, this type of semiconductor device has been formed with a layer covered with an insulating film for protecting the semiconductor device over wiring constituting an element.
上述した従来の半導体装置は、集積回路を保護するため
の膜が通常酸化膜あるいは、窒化膜等で覆われているの
で、外部からの汚れが付着した場合、保護膜の中に可動
イオンが浸透し、素子特性に影響を与える。又、水分等
が吸湿した場合、保護膜を通して、金属配線を腐食させ
るという欠点がある。In the conventional semiconductor devices mentioned above, the film to protect the integrated circuit is usually covered with an oxide film or nitride film, so if dirt from the outside adheres, mobile ions can penetrate into the protective film. and affect device characteristics. Another disadvantage is that when moisture or the like absorbs moisture, it passes through the protective film and corrodes the metal wiring.
本発明の半導体装置は、従来構造である保護膜の上に、
金属膜を覆う。またその金属膜を半導体の基板電位と同
電位にする構造を有している。The semiconductor device of the present invention has a conventional structure on which a protective film is provided.
Cover the metal film. It also has a structure in which the metal film is at the same potential as the substrate potential of the semiconductor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。半導体基板
ｌに素子を形成し、その上に配線及び絶縁層２を形成し
、さらにポンディングパッド以外を絶縁層で覆われた保
護膜３が形成されており、その上に能動領域全面（ポン
ディングパッド開口部より内側）を金属膜で覆った半導
体装置である。FIG. 1 is a sectional view of an embodiment of the present invention. A device is formed on a semiconductor substrate 1, wiring and an insulating layer 2 are formed on it, and a protective film 3 is formed which covers the area other than the bonding pad with an insulating layer. This is a semiconductor device in which the pad opening (inner side) is covered with a metal film.
第２図は本発明の実施例２の断面図である。保護金属膜
６と、半導体基板１とを接続することにより、保護金属
膜６の電位が固定され、安定した状態に維持することが
できる。FIG. 2 is a sectional view of Example 2 of the present invention. By connecting the protective metal film 6 and the semiconductor substrate 1, the potential of the protective metal film 6 is fixed and can be maintained in a stable state.
以上説明したように、本発明は、半導体装置の最終保護
膜として金属被膜を用いることにより、外部からの汚れ
などによる可動イオンを阻止し、あるいは、水分の吸湿
による金属腐食が発生しても最終保護膜である金属被膜
が反応し、内部の金属配線に到達するまでの浸入速度を
低下させ、寿命が従来よりも長くできる効果がある。As explained above, the present invention uses a metal film as the final protective film of a semiconductor device to prevent mobile ions caused by external contamination, or to protect the semiconductor device even if metal corrosion occurs due to moisture absorption. The protective metal film reacts, reducing the rate of penetration until it reaches the internal metal wiring, resulting in a longer service life than before.
第１図は本発明の実施例１、第２図は本発明の実施例２
、第３図は従来の断面図である。
１・・・・・・半導体基板、２・・・・・・絶縁層及び
配線層、３・・・・・・保護絶縁膜層、４・・・・・・
ポンディングパッド、５・・・・・・ポンディングワイ
ヤ、６・・・・・・保護金属膜層。
代理人 弁理士 内 原 晋
茅 ２ 図
第 ３ 閉FIG. 1 is a first embodiment of the present invention, and FIG. 2 is a second embodiment of the present invention.
, FIG. 3 is a conventional sectional view. 1... Semiconductor substrate, 2... Insulating layer and wiring layer, 3... Protective insulating film layer, 4...
Bonding pad, 5... Bonding wire, 6... Protective metal film layer. Agent Patent Attorney Shinkyo Uchihara 2 Figure 3 Closed
Claims (1)
を形成し、その上に能動領域全面を金属膜層で覆うこと
を特徴とする半導体装置。A semiconductor device characterized in that wiring for configuring elements and an insulating layer are formed on a semiconductor substrate, and the entire active region is covered with a metal film layer thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63041157A JPH01214126A (en) | 1988-02-23 | 1988-02-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63041157A JPH01214126A (en) | 1988-02-23 | 1988-02-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01214126A true JPH01214126A (en) | 1989-08-28 |
Family
ID=12600582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63041157A Pending JPH01214126A (en) | 1988-02-23 | 1988-02-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01214126A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5227314A (en) * | 1989-03-22 | 1993-07-13 | At&T Bell Laboratories | Method of making metal conductors having a mobile inn getterer therein |
| US6720656B2 (en) | 1998-12-21 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device with analysis prevention feature |
| US7750485B2 (en) | 2005-07-05 | 2010-07-06 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
-
1988
- 1988-02-23 JP JP63041157A patent/JPH01214126A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5227314A (en) * | 1989-03-22 | 1993-07-13 | At&T Bell Laboratories | Method of making metal conductors having a mobile inn getterer therein |
| US6720656B2 (en) | 1998-12-21 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device with analysis prevention feature |
| US7750485B2 (en) | 2005-07-05 | 2010-07-06 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
| US8076212B2 (en) | 2005-07-05 | 2011-12-13 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
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