JPH01214056A - Semiconductor device and usage thereof - Google Patents
Semiconductor device and usage thereofInfo
- Publication number
- JPH01214056A JPH01214056A JP63039153A JP3915388A JPH01214056A JP H01214056 A JPH01214056 A JP H01214056A JP 63039153 A JP63039153 A JP 63039153A JP 3915388 A JP3915388 A JP 3915388A JP H01214056 A JPH01214056 A JP H01214056A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- gate
- active layer
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 11
- 230000005669 field effect Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 description 16
- 230000009977 dual effect Effects 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、ＭＥＳ型又はＭＯＳ型の電界効果トランジス
タと抵抗素子とを１つの半４体基板に集積した半導体装
置とその使用方法に関するもので、更に詳しくはゲート
電極を分割して複数の周波数帯域に対応可能とした半導
体装置とその使用方法に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device in which a MES type or MOS type field effect transistor and a resistance element are integrated on one half-quadruple substrate; The present invention relates to a method of use, and more specifically, to a semiconductor device whose gate electrode is divided to support a plurality of frequency bands, and a method of use thereof.
（従来の技術）
ＶＨＦ帯ないしＵ ＨＦ帯で使用される高周波回路の性
能は不断の進歩を続けている。ＵＨＦの高周波回路で使
用される半導体デバイスの従来例として、Ｔ Ｖチュー
ナ用のＧａ ＡＳデュアルゲートＭＥＳ ＦＥＴを取
りあげ、図面を参照して以下説明する。第５図はこのＭ
ＥＳ ＦＥＴの電極配置を模式的に示す平面図、第６
図は第５図に示すｘ−ｘ′断面図である。 第６図にお
いて、半絶縁性Ｇａ Ａｓ基板１上に動作層２が形成さ
れ、動作層２に連接してＮ４ドレイン領域３及びＮ４ソ
ース領域４か設けられる。 ドレイン電極５はＮ゛ ド
レイン領域３とオーミック接触をすると共にその一部は
基板上に延びドレイン電極パッド５ａ＜第５図）を形成
する。 同様に符号６はソース電極、符号６ａはソース
電極パッドである。(Prior Art) The performance of high frequency circuits used in the VHF band or UHF band continues to improve. As a conventional example of a semiconductor device used in a UHF high frequency circuit, a Ga AS dual gate MES FET for a TV tuner will be described below with reference to the drawings. Figure 5 shows this M
Plan view schematically showing electrode arrangement of ES FET, No. 6
The figure is a sectional view taken along the line xx' shown in FIG. In FIG. 6, an active layer 2 is formed on a semi-insulating GaAs substrate 1, and an N4 drain region 3 and an N4 source region 4 are provided in connection with the active layer 2. The drain electrode 5 makes ohmic contact with the N2 drain region 3, and a portion thereof extends over the substrate to form a drain electrode pad 5a (FIG. 5). Similarly, numeral 6 is a source electrode, and numeral 6a is a source electrode pad.
ドレイン電極に近い側の動作層上に、動作層とショット
キー接合をする第２ゲート電極７が形成される。 第２
ゲート電極７は、例えばゲート長１μｍ、ゲート幅は６
００μｍである。 ソース電極に近い側の動作層上に、
第２ゲート電楕７と等しいゲート幅とゲート長を有する
ショットキー接合の第１ゲート電極８を設ける。 第１
、第２ゲート電極の一部は基板上に延び第１ゲート電朽
パツド８ａ、第２ゲート電極パッド７ａを設ける。A second gate electrode 7 that forms a Schottky junction with the active layer is formed on the active layer closer to the drain electrode. Second
The gate electrode 7 has a gate length of 1 μm and a gate width of 6 μm, for example.
00 μm. On the active layer near the source electrode,
A Schottky junction first gate electrode 8 having the same gate width and gate length as the second gate electrode 7 is provided. 1st
A part of the second gate electrode extends over the substrate to provide a first gate electrode pad 8a and a second gate electrode pad 7a.
デュアルゲートＭＥＳ ＦＥＴは第２ゲート′二極の
な位Ｖ ｇ２により増幅度を制御できるので、チューナ
の高周波増幅用として用いられる場合には、第２ゲート
電極は自動利得側９ｐ（ＡＧＣ）に利用される。 ス第
２ゲート電極はドレイン電極と第１ゲート電極との間に
あるので、シングルゲートＦＥＴに比しドレイン電極と
第１ゲート電極間の静電容量ＣｄＱは小さくなり、ドレ
インから入力端の第１ゲート電極への！ｌｉ’！還作用
は微弱で中和回路は不用となる。 デュアルゲートＦＥ
Ｔは、低い雑音指数を有すると共に前記利点があるので
、゛ｒ゛■チューナ回路の基＃素子として用いられてい
る。Since the amplification degree of the dual gate MES FET can be controlled by the second gate's polarity V g2, when used for high frequency amplification of a tuner, the second gate electrode can be used for automatic gain side 9p (AGC). be done. Since the second gate electrode is located between the drain electrode and the first gate electrode, the capacitance CdQ between the drain electrode and the first gate electrode is smaller than that of a single gate FET, and the capacitance CdQ from the drain to the input terminal To the gate electrode! li'! The reaction is weak and a neutralization circuit is not required. dual gate FE
Since it has a low noise figure and has the above-mentioned advantages, it is used as the basic element of the tuner circuit.
従来はＵＨＦ帯にはＧａ ＡｓデュアルゲートＭＥＳ
ＦＥＴ、ＶＨＦ帯にはシリコンデュアルゲートＭＯ３
ＦＥＴが使用されることが多く、これだと回路が大きく
且つ複雑になる。Conventionally, GaAs dual gate MES was used for UHF band.
Silicon dual gate MO3 for FET and VHF band
FETs are often used, which results in large and complex circuits.
（発明が解決しようとする課題）
最近のＣＡＴＶ、衛星放送等の情報伝達手段の多様化に
伴い、テレビ受像機、ＶＴＲ等を代表とする民生用映像
機器に対するチャン木ル増加と多機能化についてのニー
ズは非常に大きい、 これら機器のＶＨＦないしＵＨＦ
帯の高周波回路は、多数の周波帯の高周波信号を受信し
これを処理することが必要となり、これにより回路の小
型化、性能向上への要求は切実なものとなっている。(Problem to be solved by the invention) With the recent diversification of information transmission means such as CATV and satellite broadcasting, the number of channels and multifunctionality of consumer video equipment, typified by television receivers and VTRs, has increased. There is a huge need for VHF or UHF for these devices.
2. Description of the Related Art High frequency circuits in high frequency bands are required to receive and process high frequency signals in a large number of frequency bands, and as a result, there is an urgent need for circuit miniaturization and improved performance.
本発明の目的は、複数の周波数帯に使用でき、回路設計
の自由度も多く、又従来の個別素子の一部を同一基板に
集積し、もって高周波回路の多チャンネル化、小型化、
多機能化に対応できる半導体装置とその使用方法を提供
するものである。The object of the present invention is to be able to be used in multiple frequency bands, to have a large degree of freedom in circuit design, and to integrate some of the conventional individual elements on the same substrate, thereby increasing the number of channels and miniaturizing high frequency circuits.
The present invention provides a semiconductor device that can be multi-functionalized and a method for using the same.
［発明の構成］
（課題を解決するための手段とその作用）本発明の第１
請求項に係る半導体装置は、デュアルゲートのＭＥＳ型
又はＭＯ３型電界効果トランジスタの第１ゲート電極を
２分割し、ドレイン電極、第２ゲート電極及びソース電
極は共通で、分割された第１ゲート電極Ｇ１ａ及び第１
ゲート＝極Ｇｔｂをそれぞれの第１ゲート電極とする２
つのデュアルゲートＦＥＴを並設すると共にバイアス抵
抗膜を介してソース電極に接続する分岐ソース電極を具
備することを特徴とするものである。[Structure of the invention] (Means for solving the problem and its effects) First aspect of the present invention
In the semiconductor device according to the present invention, a first gate electrode of a dual-gate MES type or MO3 field effect transistor is divided into two, a drain electrode, a second gate electrode, and a source electrode are common, and the divided first gate electrode is divided into two. G1a and 1st
2 with gate=pole Gtb as each first gate electrode
This device is characterized by having two dual-gate FETs arranged in parallel and a branch source electrode connected to the source electrode via a bias resistance film.
なおバイアス抵抗膜の抵抗値は、デバイス作動時に核層
を流れる電流により、ソース電極と分岐ソース電極との
間に発生する電圧が、（イ）第１ゲート電極Ｇ、ａ又は
Ｇ１ｂ直下の動作層を十分ピンチオフできる大きさの電
圧になるようその抵抗値が決められる場合と、（ｏ）安
定な動作特性が得られる適当な負帰還率の抵抗値とする
場合とある。The resistance value of the bias resistance film is such that the voltage generated between the source electrode and the branch source electrode due to the current flowing through the core layer during device operation is determined by (a) the operating layer immediately below the first gate electrode G, a, or G1b; In some cases, the resistance value is determined so as to have a voltage large enough to pinch off the voltage, and (o) in other cases, the resistance value is determined to have an appropriate negative feedback rate that provides stable operating characteristics.
第２請求項の発明は、上記構成の半導体装１１で、バイ
アス抵抗膜は前記（イ）項の場合の使用方法に関するも
のである。 即ち分岐ソース電極を接地点（又は共通電
位点）に結んだ状態で、外部切換回路により、第１ゲー
ト電極Ｇ、ａスはＧ１ｂのいずれかの電極を分岐ソース
電極に直接又は接地部材を介して結ぶ、 この結ばれた
電極直下の動作層はピンチオフされるので、本半導体装
置は第１ゲート電極Ｇ、ａ又はＧｌｂのうち結ばれない
電極を第１ゲート電極とするデュアルゲートＦＥＴとし
て使用できる。 又外部切換回路により第１ゲート電極
Ｇ、ａ及びＧｌｂを互いに結べば、両ゲート電極を１つ
の第１ゲー１−１４１ｉとするデュアルゲートＦＥＴと
して使用できる。 又、第１ゲート電極Ｇ、ａ及びＧｔ
ｂを分離した状態で使用し、それぞれを第１ゲー１〜電
極とする２つのデュアルゲートＦＥＴとして動作させる
こともできる。The invention of claim 2 relates to the method of using the bias resistive film in the case of item (a) in the semiconductor device 11 having the above structure. That is, with the branch source electrodes connected to the ground point (or common potential point), the first gate electrode G, a is connected to the branch source electrode either directly or via a ground member by an external switching circuit. Since the active layer directly under the connected electrodes is pinched off, this semiconductor device can be used as a dual gate FET in which the unconnected electrode of the first gate electrodes G, a, or Glb is used as the first gate electrode. . If the first gate electrodes G, a, and Glb are connected to each other by an external switching circuit, it can be used as a dual gate FET in which both gate electrodes form one first gate 1-141i. Moreover, the first gate electrodes G, a and Gt
It is also possible to use the transistors b in a separated state and operate them as two dual-gate FETs, each of which serves as the first gate electrode.
−ＪＲにデュアルゲートＦＥＴにおいて第１ゲート電極
のゲート幅は、該ＦＥＴのゲート・ソース間の容量（ソ
ース接地増幅回路では入力容量となる）及びｇ、（又は
順方向アドミタンス）に影響する。 前述の本発明の半
導体装置とその使用方法によれば、第１ゲート電極Ｇ、
ａ、Ｇ１ｂ及びこれらを結んだ第１ゲート電極の３種類
のゲート幅を持つＦ Ｅ ”ｌ’が得られる。 即ち３
種類の入力容量と（Ｊ＋＋ ＠を持つＦ Ｅ ′ｌ’を
所望により選択することができる。 第１ゲート電［！
Ｇ ｔａ及びＧｔｂのゲート幅の和と、その分割比は
、高周波回路に要求される周波数帯域、ｇｌｌ Ｍ等を
考慮してあらかじめ決定される。 これにより本発明の
ＦＥＴは幅広い周波数帯に適応できると共に、種々の使
用方法があり、回ＩＩ％設計の自由度は増加する。 又
第１ゲート電極Ｇ１ａ及びＧｔｂを動作させるｖｉ流バ
イアス回路は、同一基板にＭ槓形成しても、あるいは外
部に設けても良く、又１つの共用直流バイアス回路とし
ても良いし、所望により２つのバイアス回路を設け、異
なる動作点で使用しても差支えない。-JR In a dual-gate FET, the gate width of the first gate electrode affects the gate-source capacitance (input capacitance in a source-grounded amplifier circuit) and g (or forward admittance) of the FET. According to the semiconductor device and method of using the same of the present invention described above, the first gate electrode G,
F E "l" having three types of gate widths of a, G1b, and the first gate electrode connecting these can be obtained. That is, 3
The type of input capacitance and F E 'l' with (J++ @ can be selected as desired. The first gate voltage [!
The sum of the gate widths of Gta and Gtb and the division ratio thereof are determined in advance in consideration of the frequency band, gllM, etc. required for the high frequency circuit. As a result, the FET of the present invention can be applied to a wide frequency band and can be used in various ways, increasing the degree of freedom in design. Further, the vi current bias circuit for operating the first gate electrodes G1a and Gtb may be formed in an M-shaped manner on the same substrate, or may be provided externally, or may be formed as one shared DC bias circuit, or may be formed into two if desired. Two bias circuits may be provided and used at different operating points.
第３請求項の半導体装置は従来のシングルゲー）−ＦＥ
Ｔに本発明を適用したものである。 即ちゲート電極を
２分割し、ドレイン電極、ソース電極は共通で、分割さ
れたゲート電極をそれぞれのゲート電極とする２つのＦ
Ｅ Ｔを形成したものである。 前記第２請求項に準
する使用方法により従来のＦ Ｅ Ｔに比し、大幅に機
能が拡大され、主として低周波用回路に使用することが
できる。The semiconductor device of the third claim is a conventional single game)-FE
The present invention is applied to T. In other words, the gate electrode is divided into two, the drain electrode and the source electrode are common, and the divided gate electrodes are used as the respective gate electrodes.
It was formed by ET. By using the method according to the second claim, the functions are greatly expanded compared to the conventional FET, and the device can be used mainly for low frequency circuits.
（実施例）
本発明の半導体装置の実施例の１つを第１図に示す、
本実施例は、主要構成要素のＧａ ＡＳデュアルゲート
Ｍ Ｅ Ｓ Ｆ Ｅ Ｔと、このＦＥＴの直流バイアス
回路とを半絶縁性Ｇａ Ａｓ基板に集積したリニアＩＣ
である。 第１図（ａ）はこのＩＣの模式的な平面図で
、主として電極及び抵抗膜の配置を示す、 同図（ｂ）
はＦＥＴとこれに接続する抵抗膜との断面を模式的に示
す部分拡大断面図であり、同図（ｃ）はこのリニアＩＣ
の電気回路図である。 なお第５及び第６図と同一符号
は同一部分若しくは対応部分を表わす。 Ｇａ Ａｓ半
絶縁性基板１の一方の主面（図の上方）に露出するＮ型
動作層２と、動作層２を挟みこれに連接するＮ４ドレイ
ン領域３及びＮ４ソース領域４とが、Ｓｔイオン注入に
より選択的に形成される。(Embodiment) One embodiment of the semiconductor device of the present invention is shown in FIG.
This example is a linear IC in which a Ga AS dual gate MESFET, which is the main component, and a DC bias circuit for this FET are integrated on a semi-insulating Ga As substrate.
It is. Figure 1 (a) is a schematic plan view of this IC, mainly showing the arrangement of electrodes and resistive films. Figure 1 (b)
is a partially enlarged sectional view schematically showing a cross section of an FET and a resistive film connected to it, and (c) is a partially enlarged sectional view of this linear IC.
FIG. Note that the same reference numerals as in FIGS. 5 and 6 represent the same or corresponding parts. An N-type active layer 2 exposed on one main surface (upper part of the figure) of the GaAs semi-insulating substrate 1, and an N4 drain region 3 and an N4 source region 4 connected to this with the active layer 2 interposed therebetween, are formed by St ions. Formed selectively by injection.
Ｎ′″ドレイン領域３及びＮ４ソース領域４とそれぞれ
オーミック接触をするドレイン電極５及びソース電極６
を設ける。 ドレイン電極５とソース″ｔ１極６との
間のドレイン電極に近い側にあって前記動作層上に、こ
れとショットキー接合を形成する第２ゲートな極７を設
け、又ドレイン電極５とソース電極６との間のソース電
極に近い側にあって前記動作層上に、これとショットキ
ー接合を形成する１つのゲート電極（従来の第１ゲート
電極に対応する電極）を２つに分割して得られる第１ゲ
ート′＠極Ｇ１ａ１８及びＧ１ｂ１９を設ける。 以上
の構成によりドレイン電極５、第２ゲート電極７及びソ
ース電極６を共通とし、分割したゲート電極Ｇ １ａ
１８及びＧ１ｂ１９をそれぞれ第１ゲート！極とする２
つのデュアルゲートＭＥｓ ＦＥＴが形成される。
本実施例では、第１ゲート電極Ｇ、ａ及びＧｔｂと第２
ゲート電極とのゲート長はいずれも１μｍで、ゲート幅
は第１ゲート電極Ｇｉａ及び、Ｇｌｂのいずれも３００
μｍとし、第２ゲート電極のゲート幅は６００μｍとし
た。A drain electrode 5 and a source electrode 6 make ohmic contact with the N′″ drain region 3 and the N4 source region 4, respectively.
will be established. A second gate electrode 7 is provided on the active layer on the side near the drain electrode between the drain electrode 5 and the source electrode 6, and forms a Schottky junction therewith. One gate electrode (an electrode corresponding to a conventional first gate electrode) that forms a Schottky junction with the active layer on the side near the source electrode between the electrode 6 and the active layer is divided into two. The first gate'@poles G1a18 and G1b19 obtained by the above structure are provided. With the above structure, the drain electrode 5, the second gate electrode 7, and the source electrode 6 are made common, and the divided gate electrodes G1a
18 and G1b19 respectively at the first gate! pole 2
Two dual gate MEs FETs are formed.
In this embodiment, the first gate electrodes G, a and Gtb and the second
The gate length with the gate electrode is 1 μm, and the gate width is 300 μm with the first gate electrode Gia and Glb.
μm, and the gate width of the second gate electrode was 600 μm.
又バイアス抵抗Ｍ１６と、この膜を介してソース電極６
に接続する分岐ソース電極２０が基板１に形成される。Also, the bias resistor M16 and the source electrode 6 are connected via this film.
A branch source electrode 20 connected to the substrate 1 is formed on the substrate 1 .
なお抵抗膜はＧａ Ａｓ基板にＳｉイオンをドープし
てつくられる。 本実施例ではバイアス抵抗膜１６の抵
抗値は、デバイス作動時にソース電極と分岐ソース電極
との間に発生する電圧が、第１ゲート電極Ｇ１ａ直下の
動作層を十分ピンチオフできる大きさの電圧になるよう
決められる。 又本実施例では、このバイアス抵抗１１
！１６と共にデバイスの動作点を決めるためのバイアス
抵抗Ｊ１１１１３．１４．１５を設け、その一端を第１
ゲート電極Ｇｉｂ１９に接続する。Note that the resistive film is made by doping a GaAs substrate with Si ions. In this embodiment, the resistance value of the bias resistive film 16 is such that the voltage generated between the source electrode and the branch source electrode during device operation can sufficiently pinch off the active layer immediately below the first gate electrode G1a. It can be decided as follows. In addition, in this embodiment, this bias resistor 11
! 16 and a bias resistor J11113.14.15 for determining the operating point of the device, one end of which is connected to the first
Connected to gate electrode Gib19.
なお符号５ａ、６ａ、７ａ、１８ａ、１９ａ、及び２０
ａは、それぞれドレインｔｉ、ソース電極、第２ゲート
電極、第１ゲート電極Ｇｉａ、第１ゲートな極Ｇｔｂ及
び分岐電極Ｓａに外部接続線をボンディングするための
電極パッドである。 又５ｂ、６ｂ及び１９ｂはそれぞ
れドレイン電極、ソース電極及び第１ゲート重極Ｇ１ｂ
の電極配線である。 又符号１１及び１２は、それぞれ
極性反対に直列接続された１組のＰＮ接合ダイオードで
、第１ゲートな極Ｇ１ｂ及び第２ゲート電極Ｇ２のショ
ットキー接合を保護するために設けられる。Note that the codes 5a, 6a, 7a, 18a, 19a, and 20
Reference characters a are electrode pads for bonding external connection lines to the drain ti, the source electrode, the second gate electrode, the first gate electrode Gia, the first gate electrode Gtb, and the branch electrode Sa, respectively. Further, 5b, 6b and 19b are respectively a drain electrode, a source electrode and a first gate heavy pole G1b.
This is the electrode wiring. Reference numerals 11 and 12 denote a pair of PN junction diodes connected in series with opposite polarities, and are provided to protect the Schottky junction between the first gate electrode G1b and the second gate electrode G2.
以上の構造のリニアＩＣ５０では、第１ゲートｔ ％の
ゲート幅が３００μｍの２つのＦ Ｅ ’ｒ’と、互い
に結んだ時のゲート幅が６００μｒｎのＦ Ｅ ’Ｔ”
とが得られる。 これらのＦ Ｅ Ｔは互いにゲート幅
が異なるが、それ以外のゲート長、動作層の不純物濃度
、厚さ等すべて等しい、 従って第１ゲート電極とソー
ス電極間の入力容量Ｃｔｓ、ドレイン電流Ｉ。及びｈは
、デーｌ−幅にほぼ比例した値となり、又ＮＦについて
は高周波になるに従い良好となる。 これらの電気的特
性は試行によっても確認された。In the linear IC 50 having the above structure, two F E 'r' whose gate width of the first gate t% is 300 μm and F E 'T' whose gate width when connected to each other is 600 μrn.
is obtained. Although these FETs have different gate widths, the other gate lengths, impurity concentration of the active layer, thickness, etc. are all the same. Therefore, the input capacitance Cts between the first gate electrode and the source electrode, and the drain current I. and h have values almost proportional to the data width, and the NF becomes better as the frequency becomes higher. These electrical characteristics were also confirmed through trials.
第２図は、第１図の実施例のリニアＩＣΣ旦の使用方法
の一例を示す電気回路図である。 同図において、分岐
ソース電極Ｓａは接地され、第２ゲート電極Ｇ２は自動
利得制御＜ＡＧＣ）回路に接続される。 符号ＳＷ、及
びＳＷ２は連動する外部切換器であって、通常スイッチ
ングダイオード等の電子デバイスを使用する。FIG. 2 is an electrical circuit diagram showing an example of a method of using the linear IC Σ converter of the embodiment shown in FIG. In the figure, the branch source electrode Sa is grounded, and the second gate electrode G2 is connected to an automatic gain control (AGC) circuit. Symbols SW and SW2 are interlocked external switches, which typically use electronic devices such as switching diodes.
外部切換器ＳＷ２がＵＨＦ帯チューナ側に接続された状
態では、第１ゲート電極Ｇ、ａは接地され、又ソースＮ
［Ｉ Ｓの電位は、バイアス抵抗膜１６により接地電
位より高電位側にレベルシフトされ、第１ゲート′＠［
ｆ Ｇ １ａ面直下動作層はピンチオフされ、この部分
にはドレイン電流が流れずＦＥＴとしての動作をしない
。 従ってＵＨＦ帯チューナに接続する第１ゲート電極
Ｇ１ｂのＦＥＴのみ動作状態となる。 このＦＥＴはゲ
ート幅が３００μｍで短く、入力容量が小さく、ＮＦも
良く、より高周波のＵＨＦ帯の増幅に適している。 次
に、外部切換器ＳＷ２がＶＨＦ帯入力同調泗局回路側に
接続された状態では、第１ゲート電極Ｇ１ａ及びＧ１ｂ
は結ばれ、ゲート幅６００μｍのＦＥＴとして動作をす
る。 この場合はゲート幅が長く、入力容量は増加する
が、ｇ、も大きくなりＶＨＦ帯の高周波増幅に適してい
る。 従来はＶＨＦ帯をシリコントランジスタでＵＨＦ
帯をＧａ ＡＳデュアルゲートトランジスタでチューナ
回路を別々につくっていたが、本発明により簡単な外部
切換回路によりＶＨＦ帯及びＵＨＦ帯のチューナ回路の
一部を一体化でき、小型で高性能な回路をつくることが
できる。When the external switch SW2 is connected to the UHF band tuner side, the first gate electrode G, a is grounded, and the source N
The potential of [IS is level-shifted to a higher potential side than the ground potential by the bias resistance film 16, and the potential of the first gate'@[
The active layer immediately below the f G 1a plane is pinched off, and no drain current flows through this portion, so it does not operate as an FET. Therefore, only the FET of the first gate electrode G1b connected to the UHF band tuner is in the operating state. This FET has a short gate width of 300 μm, a small input capacitance, and a good NF, making it suitable for amplification in the higher frequency UHF band. Next, when the external switch SW2 is connected to the VHF band input tuning/station circuit side, the first gate electrodes G1a and G1b
are connected and operate as a FET with a gate width of 600 μm. In this case, the gate width is long and the input capacitance increases, but g also becomes large, making it suitable for high frequency amplification in the VHF band. Conventionally, the VHF band was converted to UHF using silicon transistors.
Previously, tuner circuits for the VHF band and UHF band were made separately using Ga AS dual-gate transistors, but with the present invention, a part of the VHF band and UHF band tuner circuits can be integrated using a simple external switching circuit, making it possible to create a compact and high-performance circuit. You can make it.
第３図は、電気回路図で表わした第２の実施例である。FIG. 3 shows the second embodiment as an electrical circuit diagram.
このリニアＩＣ５１が第１の実施例と異なる点は、直
流バイアス抵抗膜１４と１５との接続点２１を第１ゲー
！・電極Ｇ１ｂから分離して、別に外部接続端子Ｔ、と
なるポンディングパッドを設けたことである。 これに
より第１ゲート電極Ｇ１２、Ｇｌｂ及びこれらを結んだ
第１ゲー！・電極の３種類のゲート幅を持つデュアルゲ
ートＭＥＳＦＥＴのうち、使用する高周波回路に適した
ＦＥＴを、簡≠な外部切換回路により選択できる。The difference between this linear IC 51 and the first embodiment is that the connection point 21 between the DC bias resistance films 14 and 15 is connected to the first gate. - A bonding pad that serves as an external connection terminal T is provided separately from the electrode G1b. As a result, the first gate electrodes G12, Glb and the first gate electrodes connecting these! - Among dual-gate MESFETs with three types of electrode gate widths, the FET suitable for the high-frequency circuit to be used can be selected using a simple external switching circuit.
第１ゲート電極Ｇｊ＆及びＧ１ｂのうちピンチオフする
電極を分岐ソース電極Ｓａに、動作する電極を外部接続
端子Ｔ、にそれぞれ結んで使用する。Of the first gate electrodes Gj& and G1b, the pinch-off electrode is connected to the branch source electrode Sa, and the operating electrode is connected to the external connection terminal T.
又第１ゲート電極Ｇ、δとＧ１ｂとを結んで使用すると
きには分岐ソースな極Ｓａは使用しない。Further, when the first gate electrodes G, δ and G1b are connected and used, the branch source pole Sa is not used.
第４図は、電気回路図で表わした本発明の半導体装置の
第３の実施例である。 ＦＥＴの動作点を決める直流
バイアス回路は外付けとし、バイアス抵抗Ｍ２２は主と
して安定な動作特性を得るための負帰還抵抗として作用
する。 外部切換回路により、第１ゲート電極のゲート
幅の異なる３種類のＦＥＴを所望により選択使用するこ
とができる。FIG. 4 shows a third embodiment of the semiconductor device of the present invention represented by an electric circuit diagram. A DC bias circuit for determining the operating point of the FET is provided externally, and the bias resistor M22 mainly functions as a negative feedback resistor to obtain stable operating characteristics. An external switching circuit allows three types of FETs having different gate widths of the first gate electrodes to be selectively used as desired.
以上の実施例はＧａ ＡＳデュアルゲートＭＥＳＦ Ｅ
Ｔについて述べたが、シリコンデュアルゲ−１−ＭＯ
３Ｆ゛ＥＴについてもほぼ同様の構成で、類似の作用と
効果か得られる。The above embodiment is a Ga AS dual gate MESF E
As mentioned above, silicon dual game 1-MO
3FET has almost the same configuration and can obtain similar actions and effects.
又シングルゲートのＭＥＳ型又はＭＯ３型ＦＥ′ｒのゲ
ート電極を２分割した半導体装置においては 前記第１
ないし第３実施例とほぼ同様の構成とし、大幅にその機
能を拡大することができる。In addition, in a semiconductor device in which the gate electrode of a single gate MES type or MO3 type FE'r is divided into two, the first
The configuration is substantially the same as that of the third embodiment, and its functions can be greatly expanded.
これら機能の応用については今後の技術開発を必要とす
る。Application of these functions will require future technological development.
［発明の効果］
これまで述べたように、本発明においては、ＭＥＳ型又
はＭＯ８型ＦＥＴのゲート電極を２分割し、その他の電
極を共通とする２つのＦ Ｅ ”ｒ’とバイアス抵抗膜
とを１つの基板に集積し、外部切換回路によりデー１−
幅の異なるＦ Ｅ Ｔを選択できるようにした。 これ
により本発明の半導体装置と使用方法は複数の周波数帯
に使用でき、回Ｆ＃１設計の自由度も多く、高周波回路
の多チャンネル化、多機能化に対応できる。 又従来例
えばＵＨＦ帯とＶＨＦ帯とで別々の半導体装置を使用し
ていたものを、簡単な外部切換回路を付加した１つの半
導体装置とすることが可能となり、又付設の直流バイア
ス回路等も１つでよく、高周波回路の小型化が可能とな
る。[Effects of the Invention] As described above, in the present invention, the gate electrode of an MES type or MO8 type FET is divided into two, and two F E "r" and a bias resistance film having the other electrodes in common are used. are integrated on one board, and the data 1-
It is now possible to select FETs with different widths. As a result, the semiconductor device and method of use of the present invention can be used in a plurality of frequency bands, and there is a large degree of freedom in designing frequency F#1, making it possible to accommodate multi-channel and multi-functional high frequency circuits. In addition, whereas conventionally separate semiconductor devices were used for the UHF band and VHF band, it is now possible to use a single semiconductor device with a simple external switching circuit added, and additional DC bias circuits etc. This makes it possible to miniaturize high-frequency circuits.
第１図は本発明の半導体装置の実施例を示すもので同図
（ａ）はその平面図、同図（ｂ）は部分拡大断面図、同
図（ｃ）は本装置の電気回路図、第２図は本発明の半導
体装置の使用方法を説明するための電気回路図、第３図
及び第４図は本発明の半導体装置の第２及び第３の実施
例を示す電気回路図、第５図は従来のＧａ Ａｓデュア
ルゲートＭＥＳ ＦＥＴの平面図、第６図は第５図の
ＭＥＳ ＦＥＴの部分拡大断面図である。
１・・・半導体基板（Ｇａ Ａｓ半絶縁性基板）、２・
・・動作層、 ３・・・ドレイン領域、 ４・・・ソー
ス領域、 ５・・・ドレイン電極（Ｄ）、 ６・・
・ソース電極（Ｓ）、 ７・・・第２ゲート電極（Ｇ２
）、１６・・・バイアス抵抗膜、 １８・・・第１ゲー
ト電桶Ｇ１ａ、 １９・・・第１ゲート電’Ｆｆ２
Ｇ １ｂ、 ２０ ・・・分岐ソース電極（Ｓａ）
。
特許出願人 株式会社 東 芝
第１図（１）
２０ （Ｓａ ｉ ６ （Ｓ）
第１図（２）
Ｃ
第３図 第４区
８ノ ７FIG. 1 shows an embodiment of the semiconductor device of the present invention; FIG. 1(a) is a plan view thereof, FIG. 1(b) is a partially enlarged sectional view, and FIG. 1(c) is an electric circuit diagram of the device. FIG. 2 is an electric circuit diagram for explaining how to use the semiconductor device of the present invention, and FIGS. 3 and 4 are electric circuit diagrams showing second and third embodiments of the semiconductor device of the present invention. FIG. 5 is a plan view of a conventional GaAs dual-gate MES FET, and FIG. 6 is a partially enlarged sectional view of the MES FET shown in FIG. 1... Semiconductor substrate (GaAs semi-insulating substrate), 2...
...Active layer, 3...Drain region, 4...Source region, 5...Drain electrode (D), 6...
・Source electrode (S), 7... second gate electrode (G2
), 16... Bias resistance film, 18... First gate voltage G1a, 19... First gate voltage 'Ff2
G 1b, 20...Branch source electrode (Sa)
. Patent Applicant Toshiba Corporation Figure 1 (1) 20 (Sa i 6 (S) Figure 1 (2) C Figure 3 Section 4 Section 8-7
Claims (1)
、該動作層に挟接するドレイン領域及びソース領域と、
該ドレイン領域及びソース領域とそれぞれオーミック接
触をするドレイン電極及びソース電極と、ドレイン電極
とソース電極との間のドレイン電極に近い側にあって前
記動作層上に直接又は絶縁膜を介して設けられる第２ゲ
ート電極と、ドレイン電極とソース電極との間のソース
電極に近い側にあって前記動作層上に直接又は絶縁膜を
介して設けられる１つのゲート電極を２つに分割して得
られる第１ゲート電極Ｇ＿１ ＿ａ及び第１ ゲート電極Ｇ＿１＿ｂとを、具備する電界効果トランジ
スタと、（ｂ）バイアス抵抗膜を介して前記ソース電極
に接続する分岐ソース電極とを、前記半導体基板に集積
して成ることを特徴とする半導体装置。 ２ 外部切換回路により、第１ゲート電極Ｇ＿１＿ａを
第１ゲート電極Ｇ＿１＿ｂに結び、第１ゲート電極Ｇ＿
１＿ａ及びＧ＿１＿ｂを１つの第１ゲート電極として使
用し、又は第１ゲート電極Ｇ＿１＿ａを分岐ソース電極
に結び、第１ゲート電極Ｇ＿１＿ａ直下の動作層をピン
チオフし、第１ゲート電極Ｇ＿１＿ｂのみを第１ゲート
電極として使用し、又は第１ゲート電極Ｇ＿１＿ｂを分
岐ソース電極に結び、第１ゲート電極Ｇ＿１＿ｂ直下の
動作層をピンチオフし、第１ゲート電極Ｇ＿１＿ａのみ
を第１ゲート電極として使用する特許請求の範囲第１項
記載の半導体装置の使用方法。 ３ 特許請求の範囲第１項記載の半導体装置において、
第２ゲート電極を設けない半導体装置。[Claims] 1 (a) an active layer exposed on one main surface of a semiconductor substrate, a drain region and a source region sandwiched between the active layer;
A drain electrode and a source electrode that make ohmic contact with the drain region and the source region, respectively; and a drain electrode and a source electrode that are located between the drain electrode and the source electrode on the side closer to the drain electrode and are provided directly or through an insulating film on the active layer. A second gate electrode and one gate electrode located on the side closer to the source electrode between the drain electrode and the source electrode and provided on the active layer directly or through an insulating film are obtained by dividing into two. A field effect transistor including a first gate electrode G_1_a and a first gate electrode G_1_b, and (b) a branch source electrode connected to the source electrode via a bias resistance film are integrated on the semiconductor substrate. A semiconductor device characterized by: 2 The external switching circuit connects the first gate electrode G_1_a to the first gate electrode G_1_b, and connects the first gate electrode G_1_a to the first gate electrode G_1_b.
1_a and G_1_b are used as one first gate electrode, or the first gate electrode G_1_a is connected to a branch source electrode, the active layer directly under the first gate electrode G_1_a is pinched off, and only the first gate electrode G_1_b is used as the first gate electrode. The first gate electrode G_1_b is used as an electrode, or the first gate electrode G_1_b is connected to a branch source electrode, the active layer directly under the first gate electrode G_1_b is pinched off, and only the first gate electrode G_1_a is used as the first gate electrode. A method of using the semiconductor device according to item 1. 3. In the semiconductor device according to claim 1,
A semiconductor device without a second gate electrode.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63039153A JPH0770733B2 (en) | 1988-02-22 | 1988-02-22 | Semiconductor device and method of using the same |
| EP89102993A EP0330142A3 (en) | 1988-02-22 | 1989-02-21 | Multi-gate field-effect transistor |
| KR1019890002088A KR910010060B1 (en) | 1988-02-22 | 1989-02-22 | Semiconductor device and its using method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63039153A JPH0770733B2 (en) | 1988-02-22 | 1988-02-22 | Semiconductor device and method of using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01214056A true JPH01214056A (en) | 1989-08-28 |
| JPH0770733B2 JPH0770733B2 (en) | 1995-07-31 |
Family
ID=12545163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63039153A Expired - Fee Related JPH0770733B2 (en) | 1988-02-22 | 1988-02-22 | Semiconductor device and method of using the same |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0330142A3 (en) |
| JP (1) | JPH0770733B2 (en) |
| KR (1) | KR910010060B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224448A (en) * | 1993-01-26 | 1994-08-12 | Sumitomo Electric Ind Ltd | Semiconductor device |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3732611A1 (en) * | 1987-09-28 | 1989-04-06 | Siemens Ag | Method for producing an implanted source/drain connection for a short-channel MOS transistor |
| EP0373803A3 (en) * | 1988-12-16 | 1991-07-10 | Raytheon Company | R. f. switching circuits |
| US5313083A (en) * | 1988-12-16 | 1994-05-17 | Raytheon Company | R.F. switching circuits |
| US5005059A (en) * | 1989-05-01 | 1991-04-02 | Motorola, Inc. | Digital-to-analog converting field effect device and circuitry |
| DE4134176C2 (en) * | 1991-10-16 | 1994-04-21 | Telefunken Microelectron | Semiconductor arrangement with a tetrode integrated in the semiconductor body and made up of two field effect transistors |
| GB9201004D0 (en) * | 1992-01-17 | 1992-03-11 | Philips Electronic Associated | A semiconductor device comprising an insulated gate field effect device |
| EP0645822A1 (en) * | 1993-08-30 | 1995-03-29 | Motorola, Inc. | High efficiency electrically adjustable width field effect transistor and method therefor |
| US5525819A (en) * | 1994-07-06 | 1996-06-11 | The Aerospace Corporation | Microwave concentric mesfet with inherent electromagnetic shielding |
| US5616945A (en) * | 1995-10-13 | 1997-04-01 | Siliconix Incorporated | Multiple gated MOSFET for use in DC-DC converter |
| DE10047168A1 (en) | 2000-09-22 | 2002-04-18 | Eupec Gmbh & Co Kg | Controllable semiconductor device |
| US8222874B2 (en) | 2007-06-26 | 2012-07-17 | Vishay-Siliconix | Current mode boost converter using slope compensation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5470778A (en) * | 1977-08-19 | 1979-06-06 | Plessey Handel Investment Ag | Fet transistor |
| JPS61110464A (en) * | 1984-11-02 | 1986-05-28 | Nec Corp | Manufacture of semiconductor device |
| JPS61182268A (en) * | 1985-02-08 | 1986-08-14 | Hitachi Ltd | Field-effect transistor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4160259A (en) * | 1976-12-27 | 1979-07-03 | Zaidan Hojin Handotai Kenkyu Shinkokai | Semiconductor device |
| JPS55108775A (en) * | 1979-02-09 | 1980-08-21 | Fujitsu Ltd | Semiconductor device |
| NL8104414A (en) * | 1981-09-25 | 1983-04-18 | Philips Nv | SEMICONDUCTOR DEVICE WITH FIELD-EFFECT TRANSISTOR. |
| JPS6155971A (en) * | 1984-08-27 | 1986-03-20 | Sumitomo Electric Ind Ltd | Schottky gate field-effect transistor |
-
1988
- 1988-02-22 JP JP63039153A patent/JPH0770733B2/en not_active Expired - Fee Related
-
1989
- 1989-02-21 EP EP89102993A patent/EP0330142A3/en not_active Withdrawn
- 1989-02-22 KR KR1019890002088A patent/KR910010060B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5470778A (en) * | 1977-08-19 | 1979-06-06 | Plessey Handel Investment Ag | Fet transistor |
| JPS61110464A (en) * | 1984-11-02 | 1986-05-28 | Nec Corp | Manufacture of semiconductor device |
| JPS61182268A (en) * | 1985-02-08 | 1986-08-14 | Hitachi Ltd | Field-effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224448A (en) * | 1993-01-26 | 1994-08-12 | Sumitomo Electric Ind Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0330142A3 (en) | 1990-05-02 |
| KR910010060B1 (en) | 1991-12-12 |
| KR890013797A (en) | 1989-09-26 |
| EP0330142A2 (en) | 1989-08-30 |
| JPH0770733B2 (en) | 1995-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11606065B2 (en) | Body tie optimization for stacked transistor amplifier | |
| US6355961B1 (en) | Structure and method for improved signal processing | |
| US5734296A (en) | Low voltage operational amplifier input stage and method | |
| US5408198A (en) | Semiconductor power amplifier integrated circuit | |
| US8058694B2 (en) | Semiconductor device | |
| JPH01214056A (en) | Semiconductor device and usage thereof | |
| US6639446B2 (en) | High linearity, high gain mixer circuit | |
| JPH0738337A (en) | Low distortion cascade circuit | |
| JP3188346B2 (en) | Field effect transistor | |
| US3749985A (en) | High frequency insulated gate field effect transistor for wide frequency band operation | |
| US4709251A (en) | Double Schottky-gate field effect transistor | |
| KR100644980B1 (en) | Compound semiconductor switch circuit device | |
| JPH11168099A (en) | Semiconductor device | |
| JP2005340550A (en) | Semiconductor device | |
| US6577170B1 (en) | CMOS transconductor with increased dynamic range | |
| US4245231A (en) | Combination capacitor and transistor structure for use in monolithic circuits | |
| US7012285B2 (en) | Semiconductor device | |
| JPH11283994A (en) | Multi-finger type field effect transistor | |
| US6448616B1 (en) | Adaptive biasing of RF power transistors | |
| JP2007194412A (en) | Active element and switching circuit device | |
| JP3071985B2 (en) | Switch device | |
| EP0610564A2 (en) | Dual gate fet and circuits using dual gate fet | |
| JP3027883B2 (en) | Microwave semiconductor amplifier | |
| JPS60137071A (en) | Schottky gate field effect transistor | |
| JP3443367B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |