JPH01209925A - Power supply parallel operation system - Google Patents
Power supply parallel operation systemInfo
- Publication number
- JPH01209925A JPH01209925A JP63035867A JP3586788A JPH01209925A JP H01209925 A JPH01209925 A JP H01209925A JP 63035867 A JP63035867 A JP 63035867A JP 3586788 A JP3586788 A JP 3586788A JP H01209925 A JPH01209925 A JP H01209925A
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- Japan
- Prior art keywords
- power supply
- circuit
- voltage
- power source
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000005669 field effect Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 230000000977 initiatory effect Effects 0.000 abstract 1
- 230000000630 rising effect Effects 0.000 abstract 1
- 230000008878 coupling Effects 0.000 description 24
- 238000010168 coupling process Methods 0.000 description 24
- 238000005859 coupling reaction Methods 0.000 description 24
- 238000001514 detection method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔概 要〕
同一極性の複数の直流電源を接続し運転をする電源並列
運転方式に関し、
並列動作を開始する時に自覚源への電流の流れ込みを阻
止し、且つ、通常の動作時に消費電力の少ない結合回路
とすることを目的とし、同一極性の複数の直流電源回路
を並列運転する電源供給回路において、前記複数の一つ
の直流電源回路の出力に接続される電界効果トランジス
タと、該電界効果トランジスタの駆動電圧を当該直流電
源回路の立ち上がりより遅れて入力する遅延回路を備え
、当該直流電源回路の出力電流に比例した電圧を当該直
流電源回路の制御回路に帰還し一定の出力電圧を得られ
るよう構成する。[Detailed Description of the Invention] [Summary] Regarding a power supply parallel operation method in which multiple DC power supplies of the same polarity are connected and operated, the present invention is to prevent current from flowing into the conscious source when starting parallel operation, and to A field effect transistor connected to the output of one of the plurality of DC power supply circuits in a power supply circuit that operates a plurality of DC power supply circuits of the same polarity in parallel, with the aim of creating a coupled circuit with low power consumption during operation. and a delay circuit that inputs the drive voltage of the field effect transistor with a delay from the rise of the DC power supply circuit, and feeds back a voltage proportional to the output current of the DC power supply circuit to the control circuit of the DC power supply circuit to maintain a constant voltage. Configure so that output voltage can be obtained.
本発明は、同一極性の複数の直流電源を接続し動作をす
る電源並列運転方式に関する。The present invention relates to a power supply parallel operation system in which a plurality of DC power supplies of the same polarity are connected and operated.
従来、同一機能を持つ電源を並列に接続し、並列運転す
ることは、負荷に対してパワー向上を図り実質的に１電
源装置当りの供給量を半分にできること、叉、二重化に
より一方の電源装置による供給が障害等で停止した場合
に他方の電源装置の余力により継続運転可能であること
等のために用いられている。Conventionally, connecting power supplies with the same function in parallel and running them in parallel has been used to improve the power for the load and virtually halve the amount supplied per power supply, and by duplicating one power supply This is used so that even if the power supply from one power source stops due to a failure, etc., the remaining power of the other power source allows for continued operation.
なお、これら並列に動作する電源において、動作中の他
の電源からの影響を阻止するため結合素子にダイオード
を用いる方法があった。しかし、ダイオード結合を用い
ると、このダイオードの電圧降下は０．５〜１．２ｖ程
度であり、出力電圧が＋５ｖや一２ｖの低電圧の場合、
この結合素子での電力消費は全体の１０％強にも達して
電源効率を低下させる問題があった。Note that in these power supplies that operate in parallel, there is a method of using a diode as a coupling element in order to block the influence from other power supplies that are operating. However, when diode coupling is used, the voltage drop across this diode is about 0.5 to 1.2V, and when the output voltage is as low as +5V or -2V,
The power consumption in this coupling element reaches over 10% of the total power consumption, which poses a problem of lowering the power supply efficiency.
このため、オン抵抗が小さく、電圧降下の少ない電界効
果トランジスタ（以下ＦＥＴと称す）を結合回路として
用いて消費電力を小さくし、複数の電源を並列に接続す
る電源並列運転方式が考えられる。Therefore, a power supply parallel operation system can be considered in which a field effect transistor (hereinafter referred to as FET) with low on-resistance and low voltage drop is used as a coupling circuit to reduce power consumption and a plurality of power supplies are connected in parallel.
ところが、この結合回路のＦＥＴは、両方向の導通特性
を有しているため、並列動作の開始のときに相手側の電
源との電圧差から、自重源に内臓する濾波用コンデンサ
へ充電電流が流れ込み相手側にとって一瞬短絡状態にな
り、系全体では電源変動となって現れる。この現象は、
電源の並列動作開始時の安定度を損なうために、この逆
電流を遮断する機能をも備えることが必要となる。However, since the FET in this coupling circuit has bidirectional conduction characteristics, when parallel operation starts, charging current flows into the filtering capacitor built into the self-weight source due to the voltage difference with the other side's power supply. This creates a momentary short circuit for the other party, and the entire system experiences power fluctuations. This phenomenon is
In order to reduce the stability of the power supplies at the start of parallel operation, it is necessary to have a function to cut off this reverse current.
従って、上記したことを避けるためには、低消費電力で
あり、更に、逆電流を遮断する二つの機能を持つ結合回
路が、電源の並列運転の安定稼働と高能率化にとって重
要な要素となり、本発明は上記条件を備えた並列運転方
式を提供する。Therefore, in order to avoid the above-mentioned problems, a coupling circuit with low power consumption and the dual function of blocking reverse current is an important element for stable operation and high efficiency of parallel operation of power supplies. The present invention provides a parallel operation system that meets the above conditions.
第５図は、従来の一実施例を示すブロック図である。図
中、ＩＡ、ＩＢは並列に接続された直流電源であって、
ＩＡは、直流電源回路１ａと結合回路路２ａより構成さ
れている動作中の直流電源、一方、直流電源ＩＢは、直
流電源回路１ｂと結合回路路２ｂより構成され、直流電
源ＩＡ、 ＩＢは同一構成である。FIG. 5 is a block diagram showing a conventional example. In the figure, IA and IB are DC power supplies connected in parallel,
IA is an operating DC power supply consisting of a DC power supply circuit 1a and a coupling circuit 2a, while DC power supply IB is composed of a DC power supply circuit 1b and a coupling circuit 2b, and the DC power supplies IA and IB are the same. It is the composition.
直流電源ＩＡ、 １Ｂは同時に並列運転されるとしても
、運転開始時には差が生じる。従って以下の説明では直
流電源ＩＡは動作中、直流電源ＩＢは直流電源ＩＡに並
列に接続し起動を開始する電源として説明を行う。Even if the DC power supplies IA and 1B are operated in parallel at the same time, a difference occurs at the start of operation. Therefore, in the following explanation, the DC power supply IA is in operation, and the DC power supply IB is connected in parallel to the DC power supply IA to start the power supply.
直流電源回路１ａにおいて、１２ａは電圧変換回路、１
３ａは整流回路、１４ａは電圧検出回路、１５ａはパル
ス幅変調回路（以下ＰＷＭ回路と称す）である。In the DC power supply circuit 1a, 12a is a voltage conversion circuit;
3a is a rectifier circuit, 14a is a voltage detection circuit, and 15a is a pulse width modulation circuit (hereinafter referred to as PWM circuit).
直流電源回路１ａに入力される直流入力は、電圧変換回
路１２ａで直流入力は交流電圧に変換され、整流回路１
３ａで直流電圧となり、結合回路２ａを経て負荷に電力
を供給する。一方、直流電源回路１ａの出力電圧の変化
は、電圧検出回路１４ａで検出してＰＷＭ回路１５ａに
加えられパルス幅変調される。このパルス幅の変化は、
直流電源回路１ａの出力が増加するときには減少し、逆
に出力電圧が減少するときはパルス幅は増加する。即ち
、この電圧変換回路１２ａに加わるパルス幅の変化と直
流電源回路１ａの出力電圧の変化を逆変化の関係にある
。この結果、直流電源回路の出力電圧を一定に維持され
る。The DC input input to the DC power supply circuit 1a is converted into an AC voltage by the voltage conversion circuit 12a, and the DC input is converted into an AC voltage by the voltage conversion circuit 12a.
3a becomes a DC voltage and supplies power to the load via the coupling circuit 2a. On the other hand, a change in the output voltage of the DC power supply circuit 1a is detected by a voltage detection circuit 14a and applied to a PWM circuit 15a, where it is pulse width modulated. This change in pulse width is
When the output of the DC power supply circuit 1a increases, the pulse width decreases, and conversely, when the output voltage decreases, the pulse width increases. That is, the change in the pulse width applied to the voltage conversion circuit 12a and the change in the output voltage of the DC power supply circuit 1a are in an inverse relationship. As a result, the output voltage of the DC power supply circuit is maintained constant.
また、結合回路２ａ、２ｂは同一構成を持つ回路である
。直流電源１ａ、１ｂのいずれか一方の電源が動作中の
時、他の電源を接続するときに、逆電流が流れ込む現象
を阻止することを目的として設けたダイオードからなる
回路で、通常の動作時には、約０．５〜１．２ｖの電圧
降下をもつ。Further, the coupling circuits 2a and 2b are circuits having the same configuration. This is a circuit consisting of a diode installed for the purpose of preventing reverse current from flowing when one of the DC power supplies 1a and 1b is in operation and the other power supply is connected.During normal operation, , with a voltage drop of about 0.5-1.2v.
上記した動作において、直流電源ＩＡが動作中である場
合、他の直流電源ＩＢを並列に接続し起動を行ったとし
ても、結合回路２ｂが接続されているので、逆電流を阻
止するため直流電源回路１ａから直流電源回路１ｂへ電
流が流れ込むことは阻止される。In the operation described above, when the DC power supply IA is in operation, even if another DC power supply IB is connected in parallel and started, since the coupling circuit 2b is connected, the DC power supply IA is used to prevent reverse current. Current is prevented from flowing from circuit 1a to DC power supply circuit 1b.
上記したような従来の結合回路２ａ、２ｂは、動作中の
直流電源に、他の直流電源を並列接続して起動する場合
、並列運転を開始する側へに逆電流が流れることを阻止
しており初期の目的は達成している。The conventional coupling circuits 2a and 2b as described above prevent reverse current from flowing to the side where parallel operation is started when an operating DC power supply is connected in parallel with another DC power supply and started. The initial objectives have been achieved.
然し、ＩＣを負荷とする回路では、その電源供給電圧は
約＋５ｖ程度、結合回路２ａ、２ｂのグイオ−ドの直列
ドロップ電圧は通常は約０．５ｖ程度で約１０％にも相
当し、通常の動作中の電源能率を低下さている。However, in a circuit that uses an IC as a load, the power supply voltage is about +5V, and the series drop voltage of the guides in the coupling circuits 2a and 2b is usually about 0.5V, which is equivalent to about 10%. The power supply efficiency during operation is reduced.
本発明は、この結合回路２ａ、２ｂの直列ドロップの減
少を図り、且つ、並列に接続して起動する直流電源回路
２ａ、２ｂへ流れ込む逆電流を阻止して、高能率で安定
した電源供給回路を得ることを目的とするものである。The present invention aims to reduce the series drop in the coupling circuits 2a and 2b, and prevents reverse current from flowing into the DC power supply circuits 2a and 2b connected in parallel and activated, thereby creating a highly efficient and stable power supply circuit. The purpose is to obtain.
本発明は、第１図の原理構成を示すブロック図に示すよ
うに、動作中の直流電源１＾と、該直流電源ＩＡに並列
に接続し起動を行う直流電源ＩＢとの二つの直流電源を
並列運転する電源供給回路において、
前記複数の一つの直流電源回路１ｂの出力に接続される
ＦＥ７２１ｂと、該Ｆ Ｅ ７２１ｂの駆動電圧を当該
直流電源回路１ｂの立ち上がりより遅れて入力する遅延
回路２２ｂを備え、当該直流電源回路１ｂの出力電流に
比例した電圧を当該直流電源回路１ｂの制御回路に帰還
し一定の出力電圧を得るよう構成する。As shown in the block diagram of the principle configuration in FIG. 1, the present invention uses two DC power supplies: an operating DC power supply 1^ and a DC power supply IB connected in parallel to the DC power supply IA to start up. In the power supply circuit that operates in parallel, an FE 721b connected to the output of one of the plurality of DC power supply circuits 1b, and a delay circuit 22b that inputs the drive voltage of the FE 721b with a delay from the rise of the DC power supply circuit 1b. A voltage proportional to the output current of the DC power supply circuit 1b is fed back to the control circuit of the DC power supply circuit 1b to obtain a constant output voltage.
本発明において、直列の電圧低下を小さくするため、第
３図（Ａ）に示すような内部に寄生ダイオ−１’Ｄｆを
もつＦＥＴのゲートに順バイアスし、第３図（Ｂ）に示
す抵抗Ｒｆをつくる。この抵抗Ｒｆの電圧低下は、第３
図（Ｃ）に示すように一定電流までは寄生ダイオードＤ
ｆの電圧低下より小さい。In the present invention, in order to reduce the voltage drop in series, the gate of the FET having an internal parasitic diode -1'Df as shown in FIG. 3(A) is forward biased, and the resistor shown in FIG. 3(B) is Create Rf. The voltage drop across this resistor Rf is caused by the third
As shown in Figure (C), the parasitic diode D
It is smaller than the voltage drop of f.
この特性を利用することにより電圧低下を小さくする。By utilizing this characteristic, the voltage drop can be reduced.
なお、Ｆ Ｅ Ｔ２１ａ 、２１ｂに流れる電流が変化
して電圧低下が変化しての出力電圧の変化は、第１図に
示すように、そのＦ Ｅ ７２１ｂの出力電圧を直流電
源回路１ｂに帰還することにより補償を行うようにする
。In addition, as shown in FIG. 1, the output voltage changes due to a change in the current flowing through F E T21a, 21b and a change in voltage drop, the output voltage of F E T21b is fed back to the DC power supply circuit 1b. Compensation will be provided accordingly.
また、逆電流の防止については、第４図（Ｃ）に示す如
く、Ｆ Ｅ ７２１ｂの導通の開始時間をｔｄだけ遅延
させるゲート電圧を遅延回路２２ｂにて発生し、該ＦＥ
Ｔ２１ｂのゲートに加えて直流電源ＩＢの出力電圧ν０
２が直流電源ＩＡの出力電圧ＶＯＩと同一の値に上昇す
る時間の間をＦＥ７２１ｂをオフとする。この結果、第
４図（Ａ）に示した動作中の直流電源ｌ＾の出力電圧の
ＶＯＩと起動の直流電源ＩＢの出力電圧ＶＯ２との電圧
差（ＶＯＩ−ＶＯ２）による逆電流を阻止し、第３図（
Ｂ）に示すよう゛に逆電流は流れなくなる。In addition, to prevent reverse current, as shown in FIG. 4(C), a gate voltage is generated in the delay circuit 22b to delay the start time of conduction of the FE 721b by td.
In addition to the gate of T21b, the output voltage ν0 of the DC power supply IB
The FE 721b is turned off during the time when the output voltage VOI of the DC power source IA rises to the same value as the output voltage VOI of the DC power supply IA. As a result, a reverse current due to the voltage difference (VOI-VO2) between the output voltage VOI of the DC power supply l^ during operation and the output voltage VO2 of the DC power supply IB during startup shown in FIG. 4(A) is prevented, Figure 3 (
As shown in B), the reverse current no longer flows.
第２図は本発明の一実施例を示す回路ブロック図であり
、図中、ＩＡ、ＩＢは並列に接続された電源であって、
ｌ＾は直流電源回路１ａと、都結合回路２ａより構成さ
れている動作中の直流電源、一方、ＩＢは、直流電源回
路１ｂと結合回路路２ｂより構成され、直流電源ＩＡ、
ＩＢは並列接続し動作する。なお、直流電源ＩＡ、
１Ｂは同一構成であり、その動作は全く同一である。FIG. 2 is a circuit block diagram showing an embodiment of the present invention, in which IA and IB are power supplies connected in parallel,
I^ is an operating DC power supply consisting of a DC power supply circuit 1a and a coupling circuit 2a, while IB is composed of a DC power supply circuit 1b and a coupling circuit 2b, and a DC power supply IA,
IBs are connected in parallel and operate. In addition, the DC power supply IA,
1B has the same configuration and its operation is completely the same.
直流電源ＩＡの直流入力は電流検出回路１１ａを経由し
て電圧変換回路１２ａに加えられる。電圧変換回路１２
ａではを交流電圧を電圧変換をし、整流回路１３ａと遅
延回路２２ａに直流電圧を出力し、結合回路２１ａから
負荷に電力を供給する。その動作は、はぼ従来回路と同
一の動作をしているが、電圧検出回路１４ａのみが従来
回路と動作を異にする。A DC input from the DC power supply IA is applied to the voltage conversion circuit 12a via the current detection circuit 11a. Voltage conversion circuit 12
In a, the AC voltage is converted into a voltage, a DC voltage is output to the rectifier circuit 13a and the delay circuit 22a, and power is supplied to the load from the coupling circuit 21a. Its operation is essentially the same as that of the conventional circuit, but only the voltage detection circuit 14a differs from the conventional circuit in its operation.
電圧検出回ＦＩｉ１１４ａは、Ｆ Ｅ Ｔ２１ ａの出
力電圧の変化分と入力電流の変化を検出する電流検出回
路１１ａで検出された電流変化を電圧変化に変換した電
圧を合成し、その合成電圧が出力するように回路構成さ
れており、この電圧検出回路１４ａの出力は、パルス幅
変調を行うＰＷＭ回路１５ａに加えられる。以後、第５
図の従来例の直流電源回路と同様、パルス幅変調された
ゲート信号を、電圧変換回路１２ａに加え、該直流電源
回路１ａの入力電流や出力電圧が一定となるように動作
する。この結果、出力電流の変化によりＦＥＴ２１ａの
電圧低下が変化して出力電圧が変化するＦＥＴ特有の問
題点も解決される。The voltage detection circuit FIi114a synthesizes the change in the output voltage of the FET21a and the voltage obtained by converting the current change detected by the current detection circuit 11a that detects the change in the input current into a voltage change, and outputs the combined voltage. The output of this voltage detection circuit 14a is applied to a PWM circuit 15a that performs pulse width modulation. From now on, the fifth
Similar to the conventional DC power supply circuit shown in the figure, a pulse width modulated gate signal is applied to the voltage conversion circuit 12a, and the DC power supply circuit 1a operates so that the input current and output voltage thereof are constant. As a result, the problem peculiar to the FET in which the voltage drop of the FET 21a changes due to a change in the output current and the output voltage changes is also solved.
また、結合回路２ａは、ＦＥＴ２１ａと遅延回路２２ａ
とから構成されている。結合回路２ａの遅延回路２２ａ
に、電圧変換回路１２ａからの制御電圧を加えることに
より、遅延回路２２ａから一定の時間ｔｄＯ間だけＦＥ
Ｔ２１ａのオンの開始時間を遅延させるゲート電圧を発
生させる。そのゲート電圧をＦＥＴ２１ａのゲートに加
えて、直流電源回路１ａの出力電圧が規定の電圧に達す
るまでの間、並列動作を遅らせるような働きをする。Further, the coupling circuit 2a includes an FET 21a and a delay circuit 22a.
It is composed of. Delay circuit 22a of coupling circuit 2a
By applying a control voltage from the voltage conversion circuit 12a to
A gate voltage is generated that delays the turn-on start time of T21a. The gate voltage is applied to the gate of the FET 21a, and the parallel operation is delayed until the output voltage of the DC power supply circuit 1a reaches a specified voltage.
上記した動作において、直流電源ＩＡの動作中である場
合、他の直流電源ＩＢを並列に接続し起動を行ったとし
ても、結合回路２ｂを有しているので、逆電流を阻止す
るため直流電源回路１ａから直流電源回路１ｂへ電流が
流れ込むことは阻止されると共に、Ｆ Ｅ ７２１ａか
ら電圧検出回路１４ａへ、またはＦＥＴ２１ｂから電圧
検出回路１４ｂへの電圧帰還により出力電圧の二定とな
る。また、結合回路２ａ、 ２ｂの直列回路がＦＥＴで
構成されておるので電圧低下の少ない電源となる。In the above operation, when the DC power supply IA is in operation, even if another DC power supply IB is connected in parallel and started, the DC power supply has the coupling circuit 2b to prevent reverse current. Current is prevented from flowing from the circuit 1a to the DC power supply circuit 1b, and the output voltage becomes constant due to voltage feedback from the F E 721a to the voltage detection circuit 14a or from the FET 21b to the voltage detection circuit 14b. Furthermore, since the series circuit of the coupling circuits 2a and 2b is composed of FETs, it becomes a power supply with little voltage drop.
以上説明した直流電源ＩＡ、 ＩＢの並列運転開始時、
逆の順番で開始しても同様に説明される。When starting the parallel operation of the DC power supplies IA and IB explained above,
The same explanation applies if you start in the reverse order.
上記のように、本発明の結合回路を使用すれば、負荷電
流による直列のドロップによる電力消費の小さい、しか
も、並列動作の開始の時に生ずる逆電流も無い直流電源
が実現が可能となり、電源の能率と安定性の向上に大き
な貢献が期待できる。As described above, by using the coupling circuit of the present invention, it is possible to realize a DC power supply that consumes less power due to series drop due to load current, and also has no reverse current that occurs when starting parallel operation. It can be expected to make a significant contribution to improving efficiency and stability.
第１図は本発明の原理構成を示すブロック図、第２図は
本発明の一実施例を示す回路ブロック図、第３図はＦＥ
Ｔの特性と等価回路の説明図、第４図は本発明の結合回
路の動作説明図、第５図は従来の一実施例を示す回路ブ
ロック図、を示す。
第１図において
ＩＡは直流電源（動作中）、
１Ｂは直流電源（動作開始）、
１ｂは直流電源回路、
２ｂは結合回路、
２１ｂは電界効果トランジスタ、
２２ｂは遅延回路、である。Fig. 1 is a block diagram showing the principle configuration of the present invention, Fig. 2 is a circuit block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram showing the basic configuration of the present invention.
FIG. 4 is an explanatory diagram of the characteristics of T and an equivalent circuit, FIG. 4 is an explanatory diagram of the operation of the coupling circuit of the present invention, and FIG. 5 is a circuit block diagram showing a conventional embodiment. In FIG. 1, IA is a DC power supply (in operation), 1B is a DC power supply (in operation), 1b is a DC power supply circuit, 2b is a coupling circuit, 21b is a field effect transistor, and 22b is a delay circuit.
Claims (1)
回路において、 前記複数の一つの直流電源回路（１ｂ）の出力に接続さ
れる電界効果トランジスタ（２１ｂ）と、該電界効果ト
ランジスタ（２１ｂ）の駆動電圧を当該直流電源回路（
１ｂ）の立ち上がりより遅れて入力する遅延回路（２２
ｂ）を備え、 当該直流電源回路（１ｂ）の出力電流に比例した電圧を
当該直流電源回路（１ｂ）の制御回路に帰還し一定の出
力電圧を得ることを特徴とする電源並列運転方式。[Claims] A power supply circuit that operates a plurality of DC power supply circuits of the same polarity in parallel, comprising: a field effect transistor (21b) connected to the output of one of the plurality of DC power supply circuits (1b); The drive voltage of the effect transistor (21b) is controlled by the DC power supply circuit (
The delay circuit (22
b), wherein a voltage proportional to the output current of the DC power supply circuit (1b) is fed back to the control circuit of the DC power supply circuit (1b) to obtain a constant output voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63035867A JPH01209925A (en) | 1988-02-17 | 1988-02-17 | Power supply parallel operation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63035867A JPH01209925A (en) | 1988-02-17 | 1988-02-17 | Power supply parallel operation system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01209925A true JPH01209925A (en) | 1989-08-23 |
Family
ID=12453939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63035867A Pending JPH01209925A (en) | 1988-02-17 | 1988-02-17 | Power supply parallel operation system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01209925A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36513E (en) * | 1994-04-11 | 2000-01-18 | Corning Inc. | Gallium sulfide glasses |
-
1988
- 1988-02-17 JP JP63035867A patent/JPH01209925A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36513E (en) * | 1994-04-11 | 2000-01-18 | Corning Inc. | Gallium sulfide glasses |
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