JPH01205569A - Manufacture of mos-type semiconductor device - Google Patents
Manufacture of mos-type semiconductor deviceInfo
- Publication number
- JPH01205569A JPH01205569A JP3027988A JP3027988A JPH01205569A JP H01205569 A JPH01205569 A JP H01205569A JP 3027988 A JP3027988 A JP 3027988A JP 3027988 A JP3027988 A JP 3027988A JP H01205569 A JPH01205569 A JP H01205569A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate electrode
- drain
- source
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000007772 electroless plating Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 238000001312 dry etching Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 5
- 125000006850 spacer group Chemical group 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯＳ型半導体装置の製造方法に関し、高融点
メタル・ゲートの如き自己整合プロセスに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing MOS type semiconductor devices, and relates to a self-aligned process such as a high melting point metal gate.
従来の自己整合プロセスに於いては特開昭６２−５１５
０６に示されている如く、半導体基板上にゲート絶縁膜
を介してゲートを設けた後、上記基板全面に絶縁膜を堆
積せしめ、上記基板にほぼ垂直にエツチングガスを入射
せしめて上記絶縁膜のドライエツチングを行って上記ゲ
ートの側面をｆｆｌ’）如く絶縁膜パターンを形成する
方法が用いられていた。In the conventional self-alignment process, Japanese Patent Application Laid-Open No. 62-515
As shown in Fig. 06, after a gate is provided on a semiconductor substrate via a gate insulating film, an insulating film is deposited on the entire surface of the substrate, and an etching gas is applied almost perpendicularly to the substrate to remove the insulating film. A method has been used in which dry etching is performed to form an insulating film pattern such as ffl') on the side surface of the gate.
しかし、上記従来技術によると、絶縁膜を堆積せしめる
工程と該絶縁膜をドライエツチングする工程を要し、い
ずれも装置に高額を要すると共にドライエツチング工程
が余分に心安であると云う問題点があった。However, the above-mentioned conventional technology requires a step of depositing an insulating film and a step of dry etching the insulating film, which both require expensive equipment and have the problem that the dry etching step is unnecessary. Ta.
本発明は、かかる従来技術の問題点をなくし、無電解メ
ッキ処理と云う安価な装置で且つドライエツチング工程
も土留な自己整合型ゲートの側面スペーサーの形成方法
を提供する事及びゲート電極表面を安定化する方法を提
供する事を目的とする。The present invention eliminates the problems of the prior art and provides a method for forming side spacers of a self-aligned gate using an inexpensive device called electroless plating and a dry etching process, and also stabilizes the surface of the gate electrode. The purpose is to provide a method for converting
上記問題点を解決するために本発明はＭＯ３型半導体装
置のゲート電極の少くとも側面を含′ｒＪ表面に無電解
メッキ層を形成する手段をとる事を基本とする。In order to solve the above problems, the present invention is based on forming an electroless plating layer on the rJ surface including at least the side surfaces of the gate electrode of the MO3 type semiconductor device.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明によるＩＡＯ８型Ｏ８効果トランジスタ
の作成を工程順に示したものである。例としてＮチャネ
ルについて説明する。FIG. 1 shows the manufacturing process of an IAO8 type O8 effect transistor according to the present invention in the order of steps. As an example, N channels will be explained.
（σ） Ｐ型の（１００）面を有する８１基板１の所望
の位置に、周知の選択酸化法により素子間分離用のフィ
ールド５ｉｎ２膜２を形成する。(σ) A field 5in2 film 2 for isolation between elements is formed at a desired position on an 81 substrate 1 having a P-type (100) plane by a well-known selective oxidation method.
その後８１基板１を再び酸化してゲーｈ Ｓ ｉ Ｏ。After that, the 81 substrate 1 is oxidized again and the game is completed.
膜６を成長せしめる。A film 6 is grown.
（ｈ） この上からタングステン等の金Ｉ＋４膜等から
成るゲー［１を極膜４をスパッタ法や化学蒸着法で形成
し、ゲートパターンを形成するための７オトレジスト５
をパターン状に写真蝕刻法により形成する。(h) On top of this, an electrode film 4 of tungsten or other gold I+4 film is formed by sputtering or chemical vapor deposition.
is formed into a pattern by photolithography.
（Ｃ） フォトンシスト５をマスクとしてゲート電極膜
４をエッチしてゲート電極６を形成する。この時、フレ
オン系のガスによるドライエツチングを用いる。(C) Gate electrode film 4 is etched using photon cyst 5 as a mask to form gate electrode 6. At this time, dry etching using Freon gas is used.
この後、次の工程に移っても良いが、ここでは、ゲート
電極６をマスクとして浅い拡散層を形成する為の低濃度
のリン又は砒素の不純物のイオン打込み層７を形成する
。After this, the process may proceed to the next step, but here, an ion-implanted layer 7 of impurities of phosphorus or arsenic at a low concentration is formed to form a shallow diffusion layer using the gate electrode 6 as a mask.
（ｄ） 次で、ニッケル等の金属膜等から成るメッキ
層８をゲート電極膜の側面を含む表面に無電解メッキ法
にて形成し、高濃度のリン又は砒素の不純物イオン打込
みを行ないソース９、及びドレイン１０を形成する。（
Ｃ）で浅いイオン打込み層７を形成しない場合は、本工
程での高濃度イオン打込みのみでも良く、更に、低濃度
拡散領域は、熱拡散にて形成する場合もある。(d) Next, a plating layer 8 made of a metal film such as nickel is formed on the surface including the side surfaces of the gate electrode film by electroless plating, and impurity ions of high concentration phosphorus or arsenic are implanted into the source 9. , and drain 10 are formed. (
If the shallow ion implantation layer 7 is not formed in step C), only the high concentration ion implantation in this step may be sufficient, and the low concentration diffusion region may also be formed by thermal diffusion.
第２図は本発明の他の実施例を示す。FIG. 2 shows another embodiment of the invention.
（ａ） 第１図＜ｈ＞でホトレジスト５をパターン状
に形成して、該ホトレジストを残存させたままリン又は
砒素を浅く、低濃度でイオン打込みしてイオン打込み層
７を形成する。(a) A photoresist 5 is formed into a pattern as shown in FIG. 1<h>, and ions of phosphorus or arsenic are implanted shallowly and at a low concentration while the photoresist remains to form an ion implantation layer 7.
本イオン打込みは必ずしも心安でなく、その場合は後工
程にてソース・ドレインを形成したままに留めるか、あ
るいはソース・ドレインからの熱拡散処理によりこれを
おぎな５事もできる。This ion implantation is not necessarily safe, and in that case, it is possible to leave the source/drain formed in a subsequent process, or to improve this by thermal diffusion treatment from the source/drain.
（ｂ） 次でメッキ層８をゲート電極膜の側面にのみ
ホトレジスト５をマスクとして無電解で形成する。(b) Next, plating layer 8 is electrolessly formed only on the side surfaces of the gate electrode film using photoresist 5 as a mask.
（Ｃ） ホトレジスト５を除去してリン又は砒素の高濃
度イオン打込みによりソース９及びトンイン１０を形成
する。(C) The photoresist 5 is removed and a source 9 and a tunnel 10 are formed by high-concentration ion implantation of phosphorus or arsenic.
尚本発明では、いわゆるＬ Ｄ Ｄ （Ｌｉｇｈｔ］、
ｙ Ｄｏｐｅｄ Ｄｒａｉｎ 構造に関して説明した
がＤ Ｄ Ｄ （ＤＯｕｆｌｅ Ｄｉｆｆａｓｉｏｎ
Ｄｒａｉｎ構造等に適用できる事は云うまでもなく、又
、ゲート′電極はタングステンのみならずモリブデンや
多結晶８１等高融点金属であっても良く、メッキ層は、
ニッケルのみならず、ゲート電極と同一材料であっても
良く、銅、白金あるいはパラジウム等の高融点金属を一
層あるいは多層に形成しても良い事は云うまでもない。In the present invention, so-called LDD (Light),
y I explained about the Doped Drain structure, but D D D (DOufle Diffusion
Needless to say, it can be applied to a drain structure, etc., and the gate' electrode may be made of not only tungsten but also a high melting point metal such as molybdenum or polycrystalline 81, and the plating layer is
Needless to say, it may be made of not only nickel but also the same material as the gate electrode, or may be made of a single layer or multiple layers of high melting point metal such as copper, platinum, or palladium.
更に、本発明は、ゲート電極の５ｉａｅ Ｗａ］、Ｉ
５ｐａｃｅｒ の形成に限らず電極配線、例えばＡｔ
電極配線の耐マイグレーシヨン処理として無電解メッキ
処理を施したり、コンタクト抵抗低減のための無電解メ
ッキ処理を施す場合にも適用できることは想像に難くな
い。Furthermore, the present invention provides a gate electrode with 5iae Wa], I
Not limited to the formation of 5pacer, but also electrode wiring, such as At
It is not difficult to imagine that the present invention can be applied to electroless plating for anti-migration treatment of electrode wiring, or electroless plating for reducing contact resistance.
本発明によるとＬ Ｄ Ｄ Ｊ！Ｉｔ造あるいはＤＤＤ
構造やゲート表ｍｊ安定化処理したＭＯ８型半導体装置
が低コストで工程数少なく形成できる効果があるAccording to the present invention, L D D J! It-made or DDD
MO8 type semiconductor devices with structure and gate surface mj stabilization treatment can be formed at low cost and with fewer steps.
第１図（ａ）〜（ｄ）は、本発明の一実施例にかかるＭ
ＯＳトランジスタの製造工程図、第２図（ａ）〜（Ｃ）
は、５ｉｄｅ Ｗａｌｌ ５ｐａｃｅｒ のみを形成
した他の実施例の要部工程図である。
１・・・・・・・・Ｓ１基板
２ ・・・・ ・フィールド５１０２膜５・・・・−・
・・ゲート５ｉ０２１換４・・ ・・・・ゲート電極膜
５・・・・・・・・ホトンジスト
６・・・・・・・・ゲート＠極
７・・・・・・・イオン打込み層
８・・・・・・・・メッキ層
９・・・・・・・・ソース
１０・・・・・ドレイン
以上
出願人 セイコーエプソン株式会社
代理人 弁理士最上筋（他１名）
ｑ口FIGS. 1(a) to 1(d) show M according to an embodiment of the present invention.
Manufacturing process diagram of OS transistor, Figure 2 (a) to (C)
These are main part process diagrams of another example in which only 5ide wall 5pacer was formed. 1... S1 substrate 2... ・Field 5102 film 5...
...Gate 5i021 conversion 4...Gate electrode film 5...Photonist 6...Gate @ pole 7...Ion implantation layer 8.・・・・・・Plating layer 9・・・・・・・・・Source 10・・・・・・Drain and above Applicant Seiko Epson Co., Ltd. agent Patent attorney Mogamisuji (1 other person) q mouth
Claims (2)
テンあるいはモリブデンあるいはシリコンによるゲート
を設けた後、該ゲートの少くとも側面を含む表面にタン
グステン、モリブデン、ニッケル、銅、白金あるいはパ
ラジウム等の無電解メッキ層を形成し、上記ゲート及び
無電解メッキ層をマスクとして上記基板表面に不純物を
導入してソース・ドレインを形成して成ることを特徴と
するＭＯＳ型半導体装置。(1) After providing a gate made of tungsten, molybdenum, or silicon on a semiconductor substrate via a gate insulating film, the surface including at least the side surfaces of the gate is coated with tungsten, molybdenum, nickel, copper, platinum, palladium, etc. 1. A MOS type semiconductor device comprising: forming an electrolytic plating layer, and introducing impurities into the surface of the substrate using the gate and the electroless plating layer as a mask to form a source/drain.
クとしてソース・ドレインと同一導電型の不純物を上記
基板表面に導入して浅い又は上記ソース・ドレインより
低濃度の不純物層が形成され、さらに上記ゲート直下の
領域に上記ソース・ドレインが達しないように形成され
ることを特徴とするＭＯＳ型半導体装置の製造方法。(2) Before forming the electroless plating layer, an impurity of the same conductivity type as the source/drain is introduced into the surface of the substrate using the gate as a mask to form a shallow impurity layer or an impurity layer with a lower concentration than the source/drain; A method of manufacturing a MOS type semiconductor device, characterized in that the source and drain are formed so as not to reach a region immediately below the gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3027988A JPH01205569A (en) | 1988-02-12 | 1988-02-12 | Manufacture of mos-type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3027988A JPH01205569A (en) | 1988-02-12 | 1988-02-12 | Manufacture of mos-type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205569A true JPH01205569A (en) | 1989-08-17 |
Family
ID=12299276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3027988A Pending JPH01205569A (en) | 1988-02-12 | 1988-02-12 | Manufacture of mos-type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205569A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216156A (en) * | 1993-01-18 | 1994-08-05 | Semiconductor Energy Lab Co Ltd | Mis-type semiconductor device and manufacture thereof |
| JPH11354797A (en) * | 1999-06-02 | 1999-12-24 | Semiconductor Energy Lab Co Ltd | Mis type semiconductor device and its manufacture |
| JP2000004025A (en) * | 1999-06-02 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | Mis-type semiconductor device and manufacture thereof |
| JP2001210833A (en) * | 1999-11-18 | 2001-08-03 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing it |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| US6737306B2 (en) | 2000-11-28 | 2004-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a tapered gate and method of manufacturing the same |
-
1988
- 1988-02-12 JP JP3027988A patent/JPH01205569A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216156A (en) * | 1993-01-18 | 1994-08-05 | Semiconductor Energy Lab Co Ltd | Mis-type semiconductor device and manufacture thereof |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| US6984551B2 (en) | 1993-01-18 | 2006-01-10 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| US7351624B2 (en) | 1993-01-18 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| JPH11354797A (en) * | 1999-06-02 | 1999-12-24 | Semiconductor Energy Lab Co Ltd | Mis type semiconductor device and its manufacture |
| JP2000004025A (en) * | 1999-06-02 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | Mis-type semiconductor device and manufacture thereof |
| JP2001210833A (en) * | 1999-11-18 | 2001-08-03 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing it |
| JP4683710B2 (en) * | 1999-11-18 | 2011-05-18 | 株式会社半導体エネルギー研究所 | Liquid crystal display device, EL display device and electronic apparatus |
| US6737306B2 (en) | 2000-11-28 | 2004-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a tapered gate and method of manufacturing the same |
| US7161179B2 (en) | 2000-11-28 | 2007-01-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US7745824B2 (en) | 2000-11-28 | 2010-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
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