JPH01204453A - Structure of pin grid array using resin substrate - Google Patents
Structure of pin grid array using resin substrateInfo
- Publication number
- JPH01204453A JPH01204453A JP63028456A JP2845688A JPH01204453A JP H01204453 A JPH01204453 A JP H01204453A JP 63028456 A JP63028456 A JP 63028456A JP 2845688 A JP2845688 A JP 2845688A JP H01204453 A JPH01204453 A JP H01204453A
- Authority
- JP
- Japan
- Prior art keywords
- resin substrate
- pattern
- chip
- resin
- pga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 68
- 229920005989 resin Polymers 0.000 title claims abstract description 68
- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000007789 sealing Methods 0.000 abstract description 10
- 229920000954 Polyglycolide Polymers 0.000 description 31
- 235000010409 propane-1,2-diol alginate Nutrition 0.000 description 31
- 230000017525 heat dissipation Effects 0.000 description 22
- 239000000919 ceramic Substances 0.000 description 17
- 239000002184 metal Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂基板を用いたピングリッドアレイ（以下Ｐ
ＧＡという）の放熱構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a pin grid array (hereinafter referred to as P pin grid array) using a resin substrate.
(referred to as GA).
ＩＣチップを搭載したＰＧＡは近年それを交換し他の機
能に変換させることにより装置の応用範囲を広げること
が行なわれてきており、この用途のためのＰＧＡの回路
基板としてセラミックが用いられてきた。In recent years, the range of applications of PGAs equipped with IC chips has been expanded by replacing them and converting them to other functions, and ceramics have been used as circuit boards for PGAs for this purpose. .
第４図は、セラミック基板を用いたＰＧＡの断面図であ
り、配線パターンを有するセラミック基板１００上にセ
ラミック枠１０１を取付け、ＩＣチップ１を実装した後
セラミック蓋１０２を接着して封止したパッケージ構造
となっている。FIG. 4 is a cross-sectional view of a PGA using a ceramic substrate, in which a ceramic frame 101 is mounted on a ceramic substrate 100 having a wiring pattern, an IC chip 1 is mounted, and a ceramic lid 102 is bonded and sealed. It has a structure.
このセラミック製の基板は、絶縁性に優れ、従って製品
としての信頼性が大きい半面、配線パターンを印刷、焼
付により行なうため収縮を伴ない、配線パターンを多く
したり、細密パターン化することが困難であり、パター
ンの本数を多くすると可及的に大型化するとともに、そ
の単体での価格が高いという欠点があった。This ceramic substrate has excellent insulation properties and is therefore highly reliable as a product, but since the wiring pattern is printed and baked, it shrinks, making it difficult to increase the number of wiring patterns or create finer patterns. However, when the number of patterns is increased, the size becomes as large as possible, and the price of each pattern is high.
このセラミック製の基板に代わるものとして近年、細密
パターン加工が可能で、かつ廉価な基板として樹脂基板
を用いたＰＧＡの開発が提案されている。前記樹脂基板
を用いたＰＧＡは、現在まだ開発段階にあり、量産市販
されているものはほとんど存在しないが従来の提案は、
その封止構造の違いにより第５図〜第７図に示すものが
ある。In recent years, as an alternative to this ceramic substrate, it has been proposed to develop a PGA using a resin substrate as a substrate that can be processed into fine patterns and is inexpensive. PGA using the resin substrate is currently still in the development stage, and there are almost no mass-produced commercially available PGAs, but conventional proposals include:
There are some types shown in FIGS. 5 to 7 depending on the difference in the sealing structure.
第５図に示すものは、樹脂基板２上に枠６を取付けて封
止樹脂４を滴下し、ＩＣチップ１を封止するものであり
、構造的には最も単純だが樹脂封止する際、ボッティン
グにより行なうため、該封止部がポーラスとなり湿気が
浸透し、さらに樹脂基板２と封止樹脂４との界面及び樹
脂基板２の周囲の破断面からの浸透も著しく、製品の信
頼性の点では必ずしも満足のいくものではなかった。The one shown in FIG. 5 is one in which a frame 6 is mounted on a resin substrate 2 and a sealing resin 4 is dropped to seal an IC chip 1. Although it is structurally the simplest, when sealing with resin, Since this is done by botting, the sealing part becomes porous and moisture penetrates.Furthermore, moisture penetrates through the interface between the resin substrate 2 and the sealing resin 4 and from the fractured surface around the resin substrate 2, which reduces the reliability of the product. The results were not necessarily satisfactory.
第６図に示すものは第５図に示すＰＧＡの欠点を考慮し
たものであり、樹脂基板２上にＩＣテップ１を載置し、
樹脂封止した後、上面全体に金属キャップ５を接着剤に
より被覆したものである。The one shown in FIG. 6 takes into account the drawbacks of the PGA shown in FIG.
After resin sealing, the entire upper surface is covered with a metal cap 5 with an adhesive.
上記第６図に示すＰＧＡは、信頼性の点では改良されて
いるが、金属キャップ５の加工及び被覆のための特別の
工程を必要としている。Although the PGA shown in FIG. 6 is improved in terms of reliability, it requires special steps for processing and coating the metal cap 5.
第７図に示すものは前記第５図及び第６図に示したＰＧ
Ａの欠点を改良するものとして本出願人が特願昭６１−
８７０８１にて提案したＰＧＡであり、下面に複数のコ
ンタクトピン２０を備えた樹脂基板２のＩＣチップ１を
載置した上面と樹脂基板周囲の破断面とを射出成形樹脂
６によって完全に被覆したパンケージング構造を有スる
。What is shown in Figure 7 is the PG shown in Figures 5 and 6 above.
In order to improve the drawbacks of A, the present applicant filed a patent application in 1986-
87081, in which the upper surface of a resin substrate 2 with a plurality of contact pins 20 on the lower surface on which the IC chip 1 is mounted and the fractured surface around the resin substrate are completely covered with injection molded resin 6. Has a caging structure.
前記樹脂基板２を用いたＰＧＡがセラミック基板１０゛
０を用いたＰＧＡに対し、細密パターン加工による小型
化と廉価とが可能であるにもかかわらず、未だに普及し
得ない理由として放熱特性の問題がある。Although the PGA using the resin substrate 2 can be made smaller and cheaper due to fine pattern processing than the PGA using the ceramic substrate 10゛0, the reason why it has not yet become widespread is due to the problem of heat dissipation characteristics. There is.
すなわちＰＧＡに実装されるＩＣはチップサイズの大き
いＬＳＩであるため動作電流による発熱が多（、この発
熱を素早くパッケージ外へ放熱してやらないと前記ＬＳ
Ｉの温度が上昇することにより、その読出し速度が低下
したり、極端な場合はＬＳＩが熱破壊されてしまう問題
が発生する。In other words, since the IC mounted on the PGA is an LSI with a large chip size, it generates a lot of heat due to the operating current.
As the temperature of I increases, the read speed decreases, and in extreme cases, the LSI may be thermally destroyed.
この放熱特性について第４図に示すセラミック基板ＰＧ
Ａと、第５図〜第７図に示す樹脂基板ＰＧＡとを比較す
ると、まずパッケージ材料の熱伝導率に於いてセラミッ
クが
４Ｘ１０ ｃａｌ ／ｃｙＬ＊’ｃｓｓｅｃ で
あるのに対して、樹脂基板ＰＧＡを達成する材料は樹脂
基板が４．５Ｘ １０ ｃａｌ／ ＣｒｒＬｓ’Ｃ
＊ｓｅｃ 、モールド樹Ｑ旨が２Ｘ１０ ｃａｌｌ
／ｃｒｎａ０Ｃｍｓｅｃ であり、パッケージ材料の
熱伝導率については、セラミック基板ＰＧＡに対して樹
脂基板ＰＧＡの方が１桁〜２桁低い値となっている。こ
のことからＩＣチップ１に発生した熱は、セラミック基
板ＰＧＡの場合にはセラミック基板１００、セラミック
枠１０１、セラミック蓋１０２を通して素早（放熱され
るが、樹脂基板ＰＧＡの場合には樹脂材料のため放熱が
少く、この分だけＩＣチップの温度が上昇することにな
る。Regarding this heat dissipation characteristic, the ceramic substrate PG shown in Fig. 4
A and the resin substrate PGA shown in Figs. The material to achieve this is a resin substrate of 4.5X 10 cal/ CrrLs'C.
*sec, mold tree Q is 2X10 call
/crna0Cmsec, and the thermal conductivity of the package material is one to two orders of magnitude lower for the resin substrate PGA than for the ceramic substrate PGA. Therefore, in the case of the ceramic substrate PGA, the heat generated in the IC chip 1 is quickly (radiated) through the ceramic substrate 100, ceramic frame 101, and ceramic lid 102, but in the case of the resin substrate PGA, the heat is radiated due to the resin material. is small, and the temperature of the IC chip increases by this amount.
上記のごとく樹脂基板ＰＧＡを普及させるには、その放
熱特性をセラミック基板ＰＧＡに近いレベル迄改良する
ことが急務であり、この放熱特性の改良の面から従来技
術を吟味する。In order to popularize the resin substrate PGA as described above, it is urgently necessary to improve its heat dissipation characteristics to a level close to that of the ceramic substrate PGA, and conventional techniques will be examined from the perspective of improving this heat dissipation characteristic.
まず第７図に示すＰＧＡの放熱経路を考えると、ＩＣチ
ップ１からの発熱は樹脂基板２を通して下面側へ放熱す
る経路と、封止樹脂６を通って上面側へ放熱する経路と
がある。First, considering the heat dissipation paths of the PGA shown in FIG. 7, the heat generated from the IC chip 1 has two paths: one through the resin substrate 2 to the lower surface side, and the other through the sealing resin 6 to the upper surface side.
そして上面側の経路については第６図に示すごとく封止
樹脂の上面に金属キャンプ５を接着する構成とすること
により、前記金属キャップ５が放熱板の役目を果し、放
熱特性が太き（改良されることが確認されている。これ
はＰＧＡに限られるものではなく一般の樹脂封止構造を
有する電力用トランジスタ等の発熱を伴う半導体が、そ
の封止樹脂の上面に金属製の放熱用フィンを装着してい
るのと同様な効果である。As for the path on the upper surface side, as shown in FIG. 6, by adhering the metal cap 5 to the upper surface of the sealing resin, the metal cap 5 serves as a heat dissipation plate, and the heat dissipation characteristics are thick ( It has been confirmed that this is an improvement.This is not limited to PGAs, but semiconductors that generate heat such as power transistors that have a general resin-sealed structure are It has the same effect as wearing fins.
次に下面側への経路については前述のごとくＰＧＡとし
て対策したものは、まだ存在しないが、一般の半導体を
実装した樹脂基板に於ける放熱構造としては第８図及び
第９図に示すものが知られている。Next, regarding the route to the bottom side, as mentioned above, there is no PGA that has taken measures yet, but the heat dissipation structure shown in Figures 8 and 9 for a resin substrate with a general semiconductor mounted thereon is Are known.
すなわち第８−図の構造シま樹脂基板２のＩＣチップ１
を載置する部分に貫通穴を設げ該貫通穴内に絞り加工し
た金属製の容器５０を埋設し、この容器５０の内部にＩ
Ｃチップ１を載置して実装することにより前記ＩＣチッ
プ１の発熱を容器５０を通して下面側に放熱するもので
ある。That is, the structure shown in FIG. 8 is the IC chip 1 on the resin substrate 2.
A through hole is provided in the part where the I/O is placed, a drawn metal container 50 is buried in the through hole, and an I
By placing and mounting the C chip 1, the heat generated by the IC chip 1 is radiated to the lower surface side through the container 50.
又第９図の構造は、樹脂基板２の貫通穴の下面に金属板
６０を接着し、この金属板６０の上にＩＣチップ１を載
置して実装することにより前記ＩＣチップ１０発熱を金
属板６０を通して下面側に放熱するものである。Further, in the structure shown in FIG. 9, a metal plate 60 is bonded to the lower surface of the through hole of the resin substrate 2, and the IC chip 1 is placed and mounted on this metal plate 60, so that the heat generated by the IC chip 10 is transferred to the metal plate. Heat is radiated to the lower surface side through the plate 60.
以上が樹脂基板ＰＧＡの放熱構造に適用可能な従来技術
であるが、このうち第８図及び第９図に示す樹脂基板２
より下面側への放熱構造を考えてみると次のような欠点
がある。The above is the conventional technology applicable to the heat dissipation structure of resin substrate PGA. Among these, the resin substrate 2 shown in FIGS.
When considering a structure for dissipating heat toward the lower surface, there are the following drawbacks.
すなわち第８図及び第９図に示す構造は、いずれも樹脂
基板２に貫通穴を設け、こ゛の貫通穴に容器５０や金属
板６０等の放熱部材を接着してＩＣチップ１を実装する
構造であるが、これは樹脂基板２に貫通穴を形成する工
程及びその貫通穴に放熱部材を接着する工程を必要とし
、又特殊な放熱部材を用意する必要がある等、コストア
ップになる欠点がある。In other words, the structures shown in FIGS. 8 and 9 are structures in which a through hole is provided in the resin substrate 2, and a heat dissipating member such as a container 50 or a metal plate 60 is bonded to the through hole to mount the IC chip 1. However, this requires a process of forming a through hole in the resin substrate 2 and a process of gluing a heat dissipating member to the through hole, and also requires the preparation of a special heat dissipating member, which has the disadvantage of increasing costs. be.
さらに前述の樹脂基板２０貫通穴に放熱部材を接着する
構造に於いては、その接着状態が悪い場合には、その部
分よりの湿気の浸透によるトラブルが発生する結果とな
り、製品の信頼性上の欠点となりうる。Furthermore, in the structure in which the heat dissipation member is bonded to the through hole of the resin substrate 20, if the bonding condition is poor, problems may occur due to moisture penetration from that part, which may affect the reliability of the product. This can be a drawback.
本発明は樹脂基板Ｐ Ｇ Ａに於げる樹脂基板側の放熱
特性を改良しようとするものであり、その目的は、コス
トアップが少なく、放熱特性に勝れ、かつ信頼性を損う
ことのないＰＧＡを提供することにある。The present invention aims to improve the heat dissipation characteristics of the resin substrate side in a resin substrate PGA, and its purpose is to minimize cost increase, improve heat dissipation characteristics, and avoid deterioration of reliability. The goal is to provide a PGA that is not available.
上記目的を達成するための本発明の要旨は下記の通りで
ある。The gist of the present invention for achieving the above object is as follows.
下面側に複数のコンタクトピンを有する樹脂基板にＩＣ
チップを実装し、該ＩＣチップを樹脂封止してなるピン
グリッドアレイにおいて、前記ＩＣチップをダイボンデ
ングするため前記樹脂基板の上面に形成されたダイボン
ドパターンと前記樹脂基板の裏面に、前記ダイボンドパ
ターンに対応して形成された裏面パターンとを設け、か
つ前記ダイボンドパターンと裏面パターンとを熱伝導部
材にて接続したことを特徴とする。IC is mounted on a resin substrate with multiple contact pins on the bottom side.
In a pin grid array in which a chip is mounted and the IC chip is sealed with resin, a die bond pattern is formed on the upper surface of the resin substrate in order to die bond the IC chip, and a die bond pattern is formed on the back surface of the resin substrate. A correspondingly formed back pattern is provided, and the die bond pattern and the back pattern are connected by a heat conductive member.
〔実施例〕 以下本発明の実施例を図面に基づいて詳述する。〔Example〕 Embodiments of the present invention will be described in detail below based on the drawings.
第１図は、本発明の樹脂基板ＰＧＡの断面図である。そ
の構造を説明する。樹脂基板２のダイボンドパターン２
ａ上にＩＣテップ１が載置してあり、公知の如くＩＣチ
ップ１は樹脂基板２上のパターン２ｄにワイヤー８で接
続されている。FIG. 1 is a sectional view of a resin substrate PGA of the present invention. Its structure will be explained. Die bond pattern 2 on resin substrate 2
An IC chip 1 is mounted on a, and as is well known, the IC chip 1 is connected to a pattern 2d on a resin substrate 2 by a wire 8.
さらにＩＣチップ１は射出成形樹脂６で封止されており
、射出成形樹脂６の上面には、放熱板７が１体モールド
で固定されている。又前記樹脂基板２の裏面のダイボン
ドパターン２ａに対応した位置には裏面パターン２ｂが
形成されている。Further, the IC chip 1 is sealed with an injection molded resin 6, and a heat dissipation plate 7 is fixed to the upper surface of the injection molded resin 6 by a single mold. Further, a back surface pattern 2b is formed on the back surface of the resin substrate 2 at a position corresponding to the die bond pattern 2a.
第２図は、ダイボンドパターン２ａの近辺のパターンの
平面図であり、ダイボンドパターン２ａの一部は前記コ
ンタクトピン２０が植設されている部分に伸張しており
、その伸張部２Ｃの先端に形成されたスルーホール２ｅ
にコンタクトピン２０ａが半田付されており、又コンタ
クトピン２０ａはスルーホール２ｅを貫通して裏面パタ
ーン２ｂにも半田付されている。FIG. 2 is a plan view of a pattern in the vicinity of the die bond pattern 2a, in which a part of the die bond pattern 2a extends to the part where the contact pin 20 is implanted, and a part of the die bond pattern 2a is formed at the tip of the extension part 2C. through hole 2e
A contact pin 20a is soldered to the back surface pattern 2b through the through hole 2e.
すなわち、前記コンタクトピン２０ａは、ＩＣチップ１
からの発熱をダイボンドパターン２ａ。That is, the contact pin 20a is connected to the IC chip 1.
The heat generated from the die bond pattern 2a.
伸張部２Ｃ，コンタクトピン２０ａ、裏面パターン２ｂ
の経路を介して外部へ放出する機能をになっている。第
３図は、本発明の他の実施例を示す樹脂基板２の断面図
である。ダイボンドパターン２ａの平面内に配設された
複数のスルーホール１０は、樹脂基板２の裏面パターン
２ｂと直接コンタクトしている。Extension part 2C, contact pin 20a, back pattern 2b
It has the ability to be released to the outside through this route. FIG. 3 is a sectional view of a resin substrate 2 showing another embodiment of the present invention. The plurality of through holes 10 arranged within the plane of the die bond pattern 2 a are in direct contact with the back pattern 2 b of the resin substrate 2 .
従ってＩＣチップ１からの発熱は該スルーホール１０を
伝って裏面パターン２ｂの広い面積で外部に放熱される
。Therefore, heat generated from the IC chip 1 is transmitted through the through hole 10 and radiated to the outside over a wide area of the back pattern 2b.
上記これらの２実施例を組み合わせると更に樹脂基板Ｐ
ＧＡに於いて、樹脂基板２側への放熱効果は一層強力に
なる事はいうまでもない。When these two embodiments are combined, the resin substrate P
Needless to say, in the GA, the heat dissipation effect toward the resin substrate 2 side becomes even stronger.
父上記樹脂基板側への放熱対策と、第１図に示す射出成
形樹脂乙に一体成形された放熱板７による上面側への放
熱対策とを併用することによって樹脂封止型ＰＧＡの放
熱特性を従来のセラミック基板ＰＧＡに匹敵するレベル
に改善することが出来た。The heat dissipation characteristics of the resin-sealed PGA can be improved by combining the heat dissipation measures to the resin substrate side described above and the heat dissipation measures to the upper surface side using the heat dissipation plate 7 integrally molded with the injection molded resin B shown in FIG. We were able to improve this to a level comparable to conventional ceramic substrate PGA.
上記のごとく本発明によれば、樹脂基板ＰＧＡのダイボ
ンドパターンと裏面パターンとを熱伝導部材にて接続す
ることにより、ＩＣチップよりの発熱を裏面パターンを
介して放出しているため、樹脂基板の密封性を損うこと
な（放熱特性を改善することが出来、しかも加工工程は
スルーホール工程やコンタクトピン植工程のどと（、す
べて樹脂基板の加工工程と同一の工程を兼用して行うこ
とが出来るとともに、従来のごとく特別の放熱部材を必
要としないため、この放熱特性改善のためのコストアッ
プは極めて少な（、従って本発明は放熱特性及び耐湿性
に優れ、かつ外形々状の安定した樹脂封止ＰＧ’Ａを低
コストにて提供する上で犬なる効果を有する。As described above, according to the present invention, by connecting the die bond pattern and the back pattern of the resin substrate PGA with a heat conductive member, heat generated from the IC chip is released through the back pattern. It is possible to improve the heat dissipation characteristics without impairing the sealing performance, and the processing process is the same as the through-hole process and contact pin implantation process (all of which can be performed in the same process as the resin substrate processing process). In addition, the cost increase for improving heat dissipation properties is extremely small because a special heat dissipation member is not required as in the past. This has a significant effect in providing sealed PG'A at low cost.
第１図は本発明の一実施例を示す樹脂基板ＰＧＡの断面
図、第２図は第１図に示す樹脂基板上パターンの部分平
面図、第３図は本発明の他の実施例を示す樹脂封止前の
ＰＧＡ断面図、第４図はセラミック基板を用いた従来の
ＰＧＡの断面図、第５図〜第７図は樹脂基板を用いた従
来のＰＧＡの断面図、第８図及び第９図は従来の樹脂基
板に於ける放熱構造を示す断面図である。
１・・・・・・ＩＣチップ、
２・・パ・・・樹脂基板、
２ａ・・・・・・ダイボンデングパターン、２ｂ・・・
・・・裏面パターン、
６・・・・・・射出成形樹脂。
第１図
第２図
第４図
第５図
第６図FIG. 1 is a cross-sectional view of a resin substrate PGA showing one embodiment of the present invention, FIG. 2 is a partial plan view of the pattern on the resin substrate shown in FIG. 1, and FIG. 3 is a diagram showing another embodiment of the present invention. 4 is a sectional view of a conventional PGA using a ceramic substrate, FIGS. 5 to 7 are sectional views of a conventional PGA using a resin substrate, and FIGS. FIG. 9 is a sectional view showing a heat dissipation structure in a conventional resin substrate. 1...IC chip, 2...Paper...resin substrate, 2a...die bonding pattern, 2b...
... Back pattern, 6... Injection molded resin. Figure 1 Figure 2 Figure 4 Figure 5 Figure 6
Claims (2)
にＩＣチップを実装し、該ＩＣチップを樹脂封止してな
るピングリッドアレイにおいて、前記ＩＣチップをダイ
ボンデングするため前記樹脂基板の上面に形成されたダ
イボンドパターンと前記樹脂基板の裏面に、前記ダイボ
ンドパターンに対応して形成された裏面パターンとを設
け、かつ前記ダイボンドパターンと裏面パターンとを熱
伝導部材にて接続したことを特徴とする樹脂基板を用い
たピングリッドアレイ構造。(1) In a pin grid array in which an IC chip is mounted on a resin substrate having a plurality of contact pins on the lower surface side and the IC chip is sealed with resin, the IC chip is formed on the upper surface of the resin substrate in order to die bond the IC chip. A resin substrate characterized in that a die bond pattern and a back surface pattern formed corresponding to the die bond pattern are provided on the back surface of the resin substrate, and the die bond pattern and the back surface pattern are connected by a heat conductive member. Pin grid array structure using a substrate.
であることを特徴とする樹脂基板を用いたピングリッド
アレイ構造。(2) A pin grid array structure using a resin substrate, wherein the heat conductive member according to claim 1 is the contact pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63028456A JPH01204453A (en) | 1988-02-09 | 1988-02-09 | Structure of pin grid array using resin substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63028456A JPH01204453A (en) | 1988-02-09 | 1988-02-09 | Structure of pin grid array using resin substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01204453A true JPH01204453A (en) | 1989-08-17 |
Family
ID=12249168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63028456A Pending JPH01204453A (en) | 1988-02-09 | 1988-02-09 | Structure of pin grid array using resin substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01204453A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337512B1 (en) | 1999-03-31 | 2002-01-08 | Abb Research Ltd. | Semiconductor module |
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274755A (en) * | 1986-05-23 | 1987-11-28 | Hitachi Vlsi Eng Corp | Semiconductor device |
| JPS6320859A (en) * | 1986-07-14 | 1988-01-28 | Matsushita Electric Works Ltd | Pin grid array |
-
1988
- 1988-02-09 JP JP63028456A patent/JPH01204453A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274755A (en) * | 1986-05-23 | 1987-11-28 | Hitachi Vlsi Eng Corp | Semiconductor device |
| JPS6320859A (en) * | 1986-07-14 | 1988-01-28 | Matsushita Electric Works Ltd | Pin grid array |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337512B1 (en) | 1999-03-31 | 2002-01-08 | Abb Research Ltd. | Semiconductor module |
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
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