JPH01200654A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01200654A JPH01200654A JP2399788A JP2399788A JPH01200654A JP H01200654 A JPH01200654 A JP H01200654A JP 2399788 A JP2399788 A JP 2399788A JP 2399788 A JP2399788 A JP 2399788A JP H01200654 A JPH01200654 A JP H01200654A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- implanted
- layer
- boron
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 8
- 239000011574 phosphorus Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- WQGWDDDVZFFDIG-UHFFFAOYSA-N pyrogallol Chemical compound OC1=CC=CC(O)=C1O WQGWDDDVZFFDIG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 238000009413 insulation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a method of manufacturing a semiconductor device.
（従来の技術）
近年素子の微細化、配線の多層化に伴なって、層間絶縁
膜の平坦化が必要になっている。現状のプロセスにおい
ては、層間絶縁膜としてＰＳＧ。(Prior Art) In recent years, with the miniaturization of elements and the increase in the number of layers of wiring, it has become necessary to planarize interlayer insulating films. In the current process, PSG is used as an interlayer insulating film.
ＢＰＳＧ等が多く用いられており、これらの膜を用いて
平坦化を行った場合の断面図を第２図に示す。同図にお
いて、１１はＰ型車結晶シリコン裁板、１２、１３．１
４は絶縁膜であり、 １５．１６は配線金属である。BPSG and the like are often used, and FIG. 2 shows a cross-sectional view of planarization using these films. In the same figure, 11 is a P-type car crystal silicon cutting board, 12, 13.1
4 is an insulating film, and 15 and 16 are wiring metals.
（発明が解決しようとする課題）
上記、従来の構造においては、ＰＳＧ、ＢＰＳＧをフロ
ーするときに、ウェハー内高さの高い領域でＰＳＧ、Ｂ
ＰＳＧがフローしやすいため、その領域でのＰＳＧ、Ｂ
ＦＳＧの膜厚が薄くなり、−層目と二層目の配線金属が
十分に絶縁されない欠点があった。(Problems to be Solved by the Invention) In the conventional structure described above, when PSG and BPSG are flowed, PSG and B
Since PSG tends to flow, PSG and B in that area
There was a drawback that the thickness of the FSG became thinner and the wiring metals in the -th layer and the second layer were not sufficiently insulated.
本発明の目的は、従来の欠点を解消し、ウェハー内高さ
の低い領域でのフロー形状をそこなうことなく、−層目
と二層目の配線金属の絶縁を十分に保つことのできる半
導体装置の製造方法を提供することである。It is an object of the present invention to provide a semiconductor device which eliminates the conventional drawbacks and can maintain sufficient insulation between the wiring metals of the first and second layers without impairing the flow shape in the low-height region of the wafer. An object of the present invention is to provide a manufacturing method.
（課題を解決するための手段）
本発明の半導体装置の製造方法は、配線金属の上に絶縁
膜を推積する工程と、注入マスクを形成する工程と、注
入マスク領域以外の部分に燐またはボロンを選択的に注
入する工程と１．熱処理によって絶縁１換をフローする
工程とを具備するものである。(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of depositing an insulating film on a wiring metal, a step of forming an implantation mask, and a step of depositing phosphorus or A step of selectively injecting boron; 1. The method includes a step of flowing the insulation through heat treatment.
（作 用）
上記製造方法によれば、ウェハー内高さの低い領域での
フロー形状を損うことなく二層目と二層１−１の配線金
属の絶縁性が保てるので、高性能、高信頼性の半導体装
置が形成される。(Function) According to the above manufacturing method, the insulation of the wiring metal of the second layer and the second layer 1-1 can be maintained without impairing the flow shape in the low-height region of the wafer, resulting in high performance and high performance. A reliable semiconductor device is formed.
（実施例） 本発明の一実施例を第１図に基づいて説明する。(Example) An embodiment of the present invention will be described based on FIG.
第１図（ａ）ないしくｃ）は本発明の半導体装置の製造
方法の工程を示す断面図である。FIGS. 1(a) to 1(c) are cross-sectional views showing the steps of the method for manufacturing a semiconductor device of the present invention.
第１図（ａ）において、Ｐ型車結晶シリコン基板１上に
、熱酸化膜、またはＰＳＧ、ＢＰＳＧ等の絶縁膜（■）
２を１０００〜３０００人推積し、配線を２０００〜６
０００人のドープドポリシリコン等によって行う。その
のち、熱酸化膜、シリコン窒化膜等の絶縁膜’（ＩＩ）
３を１０００〜３０００人推積し、 ４０００〜６０
００人のドープドポリシリコンまたはシリサイドの配線
金属（１）４によって二層目の配線を行う。In FIG. 1(a), a thermal oxide film or an insulating film (■) such as PSG or BPSG is formed on a P-type wheel crystal silicon substrate 1.
2 is estimated to be 1,000 to 3,000 people, and the wiring is estimated to be 2,000 to 6
000 doped polysilicon or the like. After that, an insulating film such as a thermal oxide film or a silicon nitride film (II) is applied.
3 is estimated at 1000-3000 people, 4000-60
A second layer of wiring is formed using a wiring metal (1) 4 of doped polysilicon or silicide.
そののち、）’ＳＧ、Ｂ）’ＳＧ等の絶縁膜（■）５を
４０００〜１００００人推積する。このときの燐濃度は
１〜ｌｏｗｔ ％ 、ボロン濃度は１〜５ｗｔ％とする
。After that, it is estimated that 4,000 to 10,000 people will use insulating films (■) 5 such as )'SG, B)'SG, etc. At this time, the phosphorus concentration is 1-lowt%, and the boron concentration is 1-5wt%.
第１図（ｂ）において、フォトリソ法により、ウェハー
内高の高い領域だけレジスト６が残るようにする。その
のち、燐またはボロンをイオン注入法によりｌ Ｘ １
０” −Ｉ Ｘ １０１Ｇｉｏｎｓ／ ｃｉ程度注入す
る。アッシングまたは発煙硝酸によってレジスト６を除
去する。In FIG. 1(b), photolithography is performed so that the resist 6 remains only in areas with high internal heights of the wafer. After that, phosphorus or boron is ion-implanted into l x 1
Inject about 0''-I x 101 Gions/ci.Remove the resist 6 by ashing or fuming nitric acid.
第１図（ｃ）において、レジストを除去したのち、ＰＳ
Ｇ、Ｂ）’ＳＧ等の絶縁膜（１１１）５を８００〜１０
００℃のドライまたはパイロ条件でフローする。このと
き、イオン注入を行った領域は、燐濃度、ボロン濃度が
濃いため、イオン注入を行っていない領域に比１咬して
フローしやすくなる。そのため、ウェハー内高さの低い
領域でのフロー形状を損うことなく高さが高い領域での
絶縁性も保てることになる。そののち、アルミニウム６
０００〜１００００人の配線金属（■）７で配線を行う
。In FIG. 1(c), after removing the resist, the PS
G, B)' Insulating film (111) 5 such as SG 800-10
Flow under dry or pyro conditions at 00°C. At this time, since the ion-implanted region has a high phosphorus concentration and boron concentration, it is more likely to flow than the ion-implanted region. Therefore, the insulation properties can be maintained in the high-height regions without impairing the flow shape in the low-height regions within the wafer. After that, aluminum 6
000 to 10,000 people wiring metal (■) 7.
以上説明した本発明の半導体装置の製造方法では、高性
能、高信頼性の半導体装置の製造が可能となる。The method for manufacturing a semiconductor device of the present invention described above enables manufacturing of a high-performance, highly reliable semiconductor device.
（発明の効果）
本発明によれば、ウェハー内高さが低い領域のフロー形
状を損うことなく二層目と二層目の配線金属の絶縁性が
保てるので高性能、高信頼性の半導体装置が形成され、
その実用上の効果は大である。(Effects of the Invention) According to the present invention, the insulation properties of the second layer and the second layer wiring metal can be maintained without impairing the flow shape in the low-height region of the wafer, resulting in high-performance and highly reliable semiconductors. A device is formed;
Its practical effects are great.
第１図（ａ）〜（Ｃ）は本発明の一実施例における半導
体装置の製造方法の工程を示す断面図、第２図は従来の
半導体装置の断面図である。
１ ・・・Ｐ型車結晶シリコン基板、２・・・絶縁膜（
Ｉ）、３ ・・・絶縁膜（ＩＩ）、４ ・・・配線金属
（１）、 ５ ・・ 絶縁膜（Ｉｌｌ）、６ ・・・
レジスト、７ ・・・配線金属（■）。
特許出願人 松下電子工業株式会社
第１図FIGS. 1A to 1C are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor device. 1...P-type wheel crystal silicon substrate, 2...Insulating film (
I), 3... Insulating film (II), 4... Wiring metal (1), 5... Insulating film (Ill), 6...
Resist, 7... Wiring metal (■). Patent applicant: Matsushita Electronics Co., Ltd. Figure 1
Claims (1)
を形成する工程と、前記注入マスク以外の部分に燐また
はボロンを選択的に注入する工程と、熱処理によって、
前記絶縁膜をフローする工程とを具備することを特徴と
する半導体装置の製造方法。By depositing an insulating film on the wiring metal, forming an implantation mask, selectively implanting phosphorus or boron into parts other than the implantation mask, and heat treatment,
A method for manufacturing a semiconductor device, comprising the step of flowing the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2399788A JPH01200654A (en) | 1988-02-05 | 1988-02-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2399788A JPH01200654A (en) | 1988-02-05 | 1988-02-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01200654A true JPH01200654A (en) | 1989-08-11 |
Family
ID=12126218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2399788A Pending JPH01200654A (en) | 1988-02-05 | 1988-02-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01200654A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165774A (en) * | 2005-12-16 | 2007-06-28 | Mitsubishi Electric Corp | Thin-film laminated substrate, manufacturing method therefor and display device |
-
1988
- 1988-02-05 JP JP2399788A patent/JPH01200654A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165774A (en) * | 2005-12-16 | 2007-06-28 | Mitsubishi Electric Corp | Thin-film laminated substrate, manufacturing method therefor and display device |
| JP4684877B2 (en) * | 2005-12-16 | 2011-05-18 | 三菱電機株式会社 | Thin film laminated substrate, manufacturing method thereof, and display device |
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