JPH01194613A - Automating equalizer initializing system - Google Patents

Automating equalizer initializing system

Info

Publication number
JPH01194613A
JPH01194613A JP1702388A JP1702388A JPH01194613A JP H01194613 A JPH01194613 A JP H01194613A JP 1702388 A JP1702388 A JP 1702388A JP 1702388 A JP1702388 A JP 1702388A JP H01194613 A JPH01194613 A JP H01194613A
Authority
JP
Japan
Prior art keywords
signal
equalizer
data
tap
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1702388A
Other languages
Japanese (ja)
Inventor
Kazuhiko Takaoka
高岡 和彦
Takashi Suzuki
隆 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1702388A priority Critical patent/JPH01194613A/en
Publication of JPH01194613A publication Critical patent/JPH01194613A/en
Pending legal-status Critical Current

Links

Landscapes

  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To shorten a convergent time of a equalizer by calculating a receiving quality by means of the square sum of an error signal to be a binary signal at the time of tap coefficient updating due to a data signal, weighting an updated gain when as equivalent residual exists because of the bad receiving quality for a set section from the receipt of the data signal, and controlling the updated gain of an equalizer. CONSTITUTION:When the CD signal of a training signal arrives at the prescribed tap position of an equalizer 2, the same pattern as the sent data in a CD period is outputted from a reference signal generator 5. Here, when line distortion is left at the information data, that is, when the equivalent residual is large, the square sum of the error signal of a received quality calculating circuit 8 becomes larger than a fixed threshold TH. Thus, for the constant section of the information data receipt, the AND of a timer 8 output is obtained by a tap updating/weighting circuit 9, the selector of an equalizer coefficient control circuit 7 selects beta, and the tap updated gain is largely weighted. For this reason, the convergent speed of the equalizer is enhanced, an error does not continue, and the data can be correctly and promptly obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、トレーニング信号とデータ信号をキャリア信
号で変調した信号を受信し、復調後に信号波形を等化す
る等化器を備える復調器に係り、特に、トレーニング信
号中の等化器調整信号を検出して参照信号を発生させ該
参照信号と前記等化器が本来出力すべき信号点を出力す
る判定器の出力との誤差信号にて初期設定を行なう自動
等化器初期化方式に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a demodulator including an equalizer that receives a training signal and a data signal modulated with a carrier signal, and equalizes the signal waveform after demodulation. In particular, an error signal between the reference signal and the output of a determiner that outputs a signal point that the equalizer should originally output by detecting an equalizer adjustment signal in a training signal and generating a reference signal. This invention relates to an automatic equalizer initialization method that performs initial settings.

〔従来の技術〕[Conventional technology]

従来の自動等化器初期化方式を第2図及び第5図により
説明する。
A conventional automatic equalizer initialization method will be explained with reference to FIGS. 2 and 5.

トレーニング信号は、第2図(b)に示す様に、AB期
間と、これに続(CD期間と、これに続き情報データの
直前に配置されるSCR期間から成る。
As shown in FIG. 2(b), the training signal consists of an AB period, followed by a CD period, and an SCR period placed immediately before the information data.

AB期間では、第2図(a)に示す信号点配置上のA。During the AB period, A on the signal point arrangement shown in FIG. 2(a).

B点が又互に発生し、CD期間では、自動等化器の調整
のため信号配置上のC,D点がある規則をもってランダ
ムに発生し、SCR期間では、信号点配置上の全ての点
A、B、C,Dが発生する。
Points B occur again and again, and in the CD period, points C and D on the signal constellation occur randomly according to a certain rule due to the adjustment of the automatic equalizer, and in the SCR period, all points on the signal constellation occur randomly. A, B, C, and D occur.

上述したトレーニング信号を第5図のoIA調回路が受
信した場合、トレーニング信号のAB期間を信号検出器
6で検出した後、復調された信号が、等仕儀の所定タッ
グ位置にきた時点で、送信されたCD期間のデータと同
一パターンデータか、参照信号発生器5よシ出力され、
その値と等仕儀2の出力が順次比較される0これは、判
定回路3と、等仕儀2の出力との差分を誤差計算回路4
により演算することで行い、演算結果を等仕儀2の誤差
信号として等仕儀2に帰還させる。かかる動作を繰シ返
し行うことで、等仕儀2の各係数タップの内、絶対参照
信号と相関をもつタップが定められ、等仕儀2は収束し
て引込み動作を完了する。その後は、判定回路3の判定
結果により微細な調整が行なわれる。
When the above-mentioned training signal is received by the oIA modulation circuit shown in FIG. The reference signal generator 5 outputs the same pattern data as the data of the CD period,
The value is sequentially compared with the output of the equalizer 2. This is done by the judgment circuit 3 and the error calculation circuit 4, which calculates the difference between the output of the equalizer 2.
The calculation result is fed back to the isolator 2 as an error signal of the isolator 2. By repeating this operation, taps that have a correlation with the absolute reference signal are determined among the coefficient taps of the isomotor 2, and the isomotor 2 converges to complete the pull-in operation. Thereafter, fine adjustments are made based on the determination result of the determination circuit 3.

尚、従来技術に関連するものとして、特開昭57−t2
ssts号がある。
In addition, as related to the prior art, Japanese Patent Application Laid-Open No. 57-t2
There is a ssts issue.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の初期化方式を採用した自動等仕儀を例え
は海外通信や長距離通信に使用し1′c場合、搬送リン
ク等の歪である大きな伝送路歪があるとき、参照信号に
て等化を実現するためのタップデータは一定区間のため
、完全に等化するにいたらず、その後の判定結果にもと
づく調整が必要となる。しかし、係数更新ゲインは、−
船釣に小さく、最終的に等化が完了するためには時間を
要するという問題がある0このため、信号を受信した直
後にエラーが発生することがらシ、これによりファクシ
ミリ等の通信レートが低下する等の原因ともなっている
@ 本発明の目的は、伝送路歪みが大きな場合でも正しくト
レーニング信号と情報データ信号により等仕儀を調整で
き、等仕残によるデータエラー発生を少なくすることが
できる自動等仕儀初期化方式を提供することにある。
For example, when automatic control using the conventional initialization method described above is used for overseas communication or long-distance communication, when there is large transmission line distortion due to distortion in the carrier link, etc., the reference signal is Since the tap data for achieving equalization is a fixed interval, it is not possible to achieve complete equalization, and adjustments based on subsequent determination results are required. However, the coefficient update gain is −
There is a problem in that it takes a long time for the equalization to be completed.As a result, an error may occur immediately after the signal is received, which reduces the communication rate of facsimile etc. It is an object of the present invention to provide automatic processing that can correctly adjust the processing using training signals and information data signals even when transmission line distortion is large, and that can reduce the occurrence of data errors due to processing errors. The objective is to provide a formal initialization method.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、データ信号によるタップ係数更新時に、2
元信号である誤差信号の2乗和により受信品質を算出し
、信号検出回路からの情報によりデータ信号を受信して
からの一定区間は、受信品質が悪くて等仕残があるとき
は更新ゲインに重みを付けて等仕儀の更新ゲインを制御
することで、達成される。
The above purpose is to update 2 tap coefficients using data signals.
The reception quality is calculated by the sum of squares of the error signal, which is the original signal, and the update gain is calculated during a certain period after receiving the data signal based on information from the signal detection circuit. This is achieved by controlling the update gain of the constant motion by weighting the .

〔作用〕[Effect]

等化器出力と判定出力との誤差の二乗和を監視すること
により、受信信号の等仕残つまシ受信品質を検出し、等
仕残の大きな時は、更新ゲインを大きく重みうけして制
御する0これにより、等仕儀の収束時間は短縮される。
By monitoring the sum of squares of errors between the equalizer output and the judgment output, the reception quality of the received signal is detected, and when the equalization residual is large, the update gain is heavily weighted and controlled. 0 This shortens the convergence time for uniformity.

等仕残改善後および、データ信号受信後の一定区間後は
、更新ゲインを最適値に設定して歪を補正し、正しい復
調を行なうO 〔実施例〕 以下、本発明の一実施例を第1図〜第4図を参照して説
明する。
After improving the balance and after a certain period after receiving the data signal, the update gain is set to the optimum value to correct distortion and perform correct demodulation. This will be explained with reference to FIGS. 1 to 4.

第1図は、本発明の一実施例に係る自動等化器初期化方
式を適用した@l調回路の構成図である0この復調回路
は、第2図で説明したトレーニング信号とこれに続く情
報データを受信する復調器1と、復調した情報データの
波形等化を行なう自動等化器2と、自動等化器2の出力
により信号領域を判定し本来出力すべき信号点を出力す
る判定器3と、復調器1の出力信号中のトレーニング信
号を検出する信号検出器6と、該信号検出器6が検出し
たトレーニング信号に同期したパターンを発生する参照
信号発生器5と、(等仕儀2出カー判定器3出力、)あ
るいは、(吟仕儀2出カー参照信号発生器5出力)を演
算し出力する誤差計算回路4と、該論差計算回路4の出
力ekの値によ)受信品質を判定する受信品質算出回路
8と、該受信品質算出回路8の判定結果によ〕等仕儀更
新ゲイン重み付けを行なう更新ゲイン重み付は回路9と
、情報データの受信後のある一定区間更新ケインを制御
する等仕儀係数制御回路7からなる。
FIG. 1 is a block diagram of an @l modulation circuit to which an automatic equalizer initialization method according to an embodiment of the present invention is applied. This demodulation circuit uses the training signal explained in FIG. A demodulator 1 that receives information data, an automatic equalizer 2 that performs waveform equalization of the demodulated information data, and a determination that determines a signal region based on the output of the automatic equalizer 2 and outputs a signal point that should originally be output. 3, a signal detector 6 that detects a training signal in the output signal of the demodulator 1, and a reference signal generator 5 that generates a pattern synchronized with the training signal detected by the signal detector 6. An error calculation circuit 4 that calculates and outputs the output of the 2-output car determination device 3, ) or (the output of the 2-output car reference signal generator 5) and the value of the output ek of the difference calculation circuit 4) is received. A reception quality calculation circuit 8 that determines the quality, an update gain weighting circuit 9 that performs regular update gain weighting according to the judgment result of the reception quality calculation circuit 8, and a certain interval update key after receiving information data. It consists of a uniformity coefficient control circuit 7 that controls.

第4図は、信号検出器6の詳細構成図であ夛、本信号検
出器は、信号のデータサンプリング毎に人力信号を遅延
させる遅延累子で構成されたフィルタ10と、加算器1
22乗算器13.比較器14等で構成されている。この
信号検出器6には、2次元データX、 Yが入力される
。該信号X、 Yが入力されるフィルタ10は、DCと
ナイキスト周波数に零点をもつ特性を有し、トレーニン
グ信号のAB交互の信号スペクトラムは該フィルタ10
により遮断される。次に続(CD信号は、一定規側のラ
ンダム信号のため、フィルタ10に出力が生ずる。つま
シ、信号検出器6は、2乗和の積分により、トレーニン
グ信号のAB期間からCD期間への変化点を検出し、比
較器14の固定閾値THにより次段の参照信号発生器5
へ起動をかける。また、CD期間よシ情報データまでの
間は、ある固定の期間となシ、更新ゲインlみ付回路9
へ情報データのはじまシ情報を与える。
FIG. 4 is a detailed configuration diagram of the signal detector 6. This signal detector includes a filter 10 composed of a delay multiplier that delays a human input signal every time data sampling of the signal is performed, and an adder 1.
22 multiplier 13. It is composed of a comparator 14 and the like. Two-dimensional data X and Y are input to this signal detector 6. The filter 10 to which the signals X and Y are input has a characteristic of having zero points at the DC and Nyquist frequencies, and the signal spectrum of alternating AB of the training signal is
is blocked by Next, since the CD signal is a random signal on the constant side, an output is generated in the filter 10. Finally, the signal detector 6 detects the signal from the AB period to the CD period of the training signal by integrating the sum of squares. The change point is detected, and the next stage reference signal generator 5 uses the fixed threshold value TH of the comparator 14.
Start up. In addition, the period from the CD period to the information data is a fixed period, and the update gain matching circuit 9
The beginning information of the information data is given to.

第3図は、自動等仕儀2、等仕儀制御回路7、受信品質
算出回路8、史筆[ゲイン重み付は回路9の要部詳細図
である。等化量係数制御回路7はセレクタを備え、受信
品質算出回路8からの信号による等化残信号と、更ル[
ゲイン重み付は回路9の時間制御条件をくわえられた信
号により、α又はβのタップ更新ゲインを選択し、これ
を等仕儀2に出力するようになっている0受信品質算出
回路8は、2次元侶号である誤差毎号13にのΔxt”
7を夫々2乗する乗算器15と、2乗したムx2.Δy
2 を加算する加算器16と、得られた2乗和と固定閾
値THとを比較する比較器17とからなる。更新ゲイン
重み付は回路は、CD期−量変化点情報より、情報デー
タの先頭よりある一定区間の時間を検出するタイマ18
と、受信品質制御回路8からの信号とのアンド金とるア
ンドゲート19をもつ。
FIG. 3 is a detailed diagram of the main parts of the automatic control circuit 2, control circuit 7, reception quality calculation circuit 8, and circuit 9 with gain weighting. The equalization amount coefficient control circuit 7 includes a selector, and outputs the equalized residual signal from the signal from the reception quality calculation circuit 8 and the
The gain weighting circuit 8 selects a tap update gain of α or β based on the signal added to the time control condition of the circuit 9, and outputs this to the input signal 2. Δxt for each dimension error number 13”
a multiplier 15 which squares 7, and a multiplier 15 which squares 7, respectively; Δy
2, and a comparator 17 that compares the obtained square sum with a fixed threshold TH. The update gain weighting circuit uses a timer 18 that detects a certain period of time from the beginning of the information data from the CD period-amount change point information.
and a signal from the reception quality control circuit 8.

自動等化器2は公知の複索形MSE法自#等化器であシ
、Tは遅延器、CMは係数タップである。
The automatic equalizer 2 is a known multi-chord MSE automatic equalizer, T is a delay device, and CM is a coefficient tap.

この自動等化器2は、誤走出力ekと次式(すCj+1
=Cj−α・θに・Xj・曲・・e・(1)のアルゴリ
ズムによりタツブ更新を行なう0尚、XjはデータX、
の複素共役を示す。
This automatic equalizer 2 has an error output ek and the following formula (Cj+1
=Cj-α・θ・Xj・song・・e・Tab update is performed using the algorithm of (1) 0 In addition, Xj is data X,
shows the complex conjugate of.

斯かる構成の復調回路の動作を次に説明する。The operation of the demodulation circuit having such a configuration will be explained next.

トレーニング信号のCD信号が等仕儀2の所定のタップ
位置に来た時点で、送信されてさたCD期間のデータと
同一パターンが参照信号発生器5から出力される。誤差
算出回路4は、等仕儀2の出力と参照信号との誤差θk
を求め、等仕儀2は前記第(0式のアルゴリズムに従っ
た調整を完了する〇その後に情報データが入力してくる
が、それ以後のタップ更新に使用される誤差信号141
には、判定器3の出力との誤差信号となる。
When the CD signal of the training signal reaches a predetermined tap position of the controller 2, the reference signal generator 5 outputs the same pattern as the transmitted CD period data. The error calculation circuit 4 calculates the error θk between the output of the isomotor 2 and the reference signal.
, and the adjustment 2 completes the adjustment according to the algorithm of formula 0. After that, information data is input, and the error signal 141 used for subsequent tap updates is input.
becomes an error signal with respect to the output of the determiner 3.

ここで、従来の場合は、海外通信等で回係歪が大きな場
合、等仕儀の収束時間が長く、情報データを受信しても
誤シが生じてしまう。しかるに、本笑施例では、情報デ
ータに回係歪がのこシ、すなわち等仕残が大きいと、受
信品質算出回路8の誤差信号の2乗和が大きくなって固
定閾値THよシ大きくなってしまう。これにより、タッ
グ更新重み付は回路9にて、情報データ受信の一定区間
はタイマ18出力のアンドがとられ、等化量係数制御回
路7のセレクタはβを選択し、タップ更新ゲインを大き
く重み付けする。このため、等仕儀の収束速度が向上し
て、誤シが継続せず、データが正しく且つ速く得られる
ことになる〇 〔発明の効果〕 不発明によれば、回係の歪成分が大きな場合でも、正し
くトレーニング(3号と情報データ信号により等仕儀を
調整でき、等仕残によるデータエラーの発生を少なくす
る効果がある。このため、海外通信等の通信確率が悪い
伝送路でも、高速のデータ伝送が可能となる。
Here, in the conventional case, when the rotation distortion is large due to overseas communication, etc., the convergence time for uniformity is long, and errors occur even when information data is received. However, in this embodiment, if the information data has a large rotational distortion, that is, if the residual is large, the sum of squares of the error signal of the reception quality calculation circuit 8 becomes large and becomes larger than the fixed threshold value TH. It ends up. As a result, the tag update weighting is performed by the circuit 9, and the output of the timer 18 is ANDed during a certain period of information data reception, and the selector of the equalization amount coefficient control circuit 7 selects β, and the tap update gain is weighted greatly. do. Therefore, the convergence speed of the equation is improved, errors do not continue, and data can be obtained correctly and quickly.〇 [Effect of the invention] According to the invention, when the distortion component of the equation is large. However, correct training (No. 3) and information data signals can be used to adjust the transmission rate, which has the effect of reducing the occurrence of data errors due to transmission errors.For this reason, even on transmission lines with poor communication probability such as overseas communications, high-speed transmission is possible. Data transmission becomes possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係る復調回路の構成図、第
2図(a)は信号点配置図、第2図(b)はトレーニン
グ信号構成図、第3図は第1図に示す復調回路の要部詳
細図、第4図は第1図に示す信号検出器の詳細図、第5
図は従来の復調回路の構成図である。
Figure 1 is a block diagram of a demodulation circuit according to an embodiment of the present invention, Figure 2 (a) is a signal point arrangement diagram, Figure 2 (b) is a training signal configuration diagram, and Figure 3 is similar to Figure 1. 4 is a detailed diagram of the main part of the demodulation circuit shown in FIG. 4, and FIG. 5 is a detailed diagram of the signal detector shown in FIG.
The figure is a configuration diagram of a conventional demodulation circuit.

Claims (1)

【特許請求の範囲】[Claims] 1、トレーニング信号とデータ信号をキャリア信号で変
調した信号を受信し、復調後に信号波形を等化すると共
に、トレーニング信号中の等化器調整信号を検出して参
照信号を発生させ、該参照信号と、前記等化器が本来出
力すべき信号点を出力する判定器の出力との誤差信号に
て初期化を行なう自動等化器初期化方式において、デー
タ信号によるタップ係数更新時に、2元信号である前記
誤差信号の2乗和により受信品質を算出し、信号検出回
路からの情報によりデータ信号を受信してからの一定区
間は、受信品質が悪くて等化残があるときは更新ゲイン
に重みを付けて等化器の更新ゲインを制御することを特
徴とする自動等化器初期化方式。
1. Receive a signal obtained by modulating a training signal and a data signal with a carrier signal, equalize the signal waveform after demodulation, detect an equalizer adjustment signal in the training signal to generate a reference signal, and generate a reference signal. In an automatic equalizer initialization method in which initialization is performed using an error signal between the signal point and the output of a determiner that outputs the signal point that the equalizer should originally output, when the tap coefficient is updated by the data signal, the binary signal The reception quality is calculated by the sum of squares of the error signal, and if the reception quality is poor and there is an equalization residual, the update gain is used for a certain period after receiving the data signal based on information from the signal detection circuit. An automatic equalizer initialization method characterized by controlling the update gain of the equalizer by adding weights.
JP1702388A 1988-01-29 1988-01-29 Automating equalizer initializing system Pending JPH01194613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1702388A JPH01194613A (en) 1988-01-29 1988-01-29 Automating equalizer initializing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1702388A JPH01194613A (en) 1988-01-29 1988-01-29 Automating equalizer initializing system

Publications (1)

Publication Number Publication Date
JPH01194613A true JPH01194613A (en) 1989-08-04

Family

ID=11932398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1702388A Pending JPH01194613A (en) 1988-01-29 1988-01-29 Automating equalizer initializing system

Country Status (1)

Country Link
JP (1) JPH01194613A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09200079A (en) * 1996-01-16 1997-07-31 Nec Corp Data transmission method and data transmitter
US7298774B2 (en) 2000-08-25 2007-11-20 Sanyo Electric Co., Ltd. Adaptive array device, adaptive array method and program
WO2013084367A1 (en) * 2011-12-07 2013-06-13 日本電気株式会社 Equalization signal processing device, and optical receiver device and equalization signal processing method employing same
CN113315968A (en) * 2021-07-29 2021-08-27 杭州博雅鸿图视频技术有限公司 Circuit design method, device, equipment and medium for improving code rate calculation efficiency

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09200079A (en) * 1996-01-16 1997-07-31 Nec Corp Data transmission method and data transmitter
US7298774B2 (en) 2000-08-25 2007-11-20 Sanyo Electric Co., Ltd. Adaptive array device, adaptive array method and program
WO2013084367A1 (en) * 2011-12-07 2013-06-13 日本電気株式会社 Equalization signal processing device, and optical receiver device and equalization signal processing method employing same
JPWO2013084367A1 (en) * 2011-12-07 2015-04-27 日本電気株式会社 Equalized signal processing apparatus, optical receiver using the same, and equalized signal processing method
US9160459B2 (en) 2011-12-07 2015-10-13 Nec Corporation Equalization signal processor, optical receiver including the same, and method for equalization signal processing
CN113315968A (en) * 2021-07-29 2021-08-27 杭州博雅鸿图视频技术有限公司 Circuit design method, device, equipment and medium for improving code rate calculation efficiency
CN113315968B (en) * 2021-07-29 2021-12-03 杭州博雅鸿图视频技术有限公司 Circuit design method, device, equipment and medium for improving code rate calculation efficiency

Similar Documents

Publication Publication Date Title
US6563868B1 (en) Method and apparatus for adaptive equalization in the presence of large multipath echoes
AU593071B2 (en) Adaptive blind equalization method and device
US20030219085A1 (en) Self-initializing decision feedback equalizer with automatic gain control
US6904087B2 (en) Adaptive multi-modulus algorithm method for blind equalization
US5684827A (en) System for controlling the operating mode of an adaptive equalizer
JP2004518317A (en) Signal strength correction for highly time-varying mobile radio channels
US5537439A (en) Decision directed algorithm control method
JPH09186634A (en) Data receiving device
JPH03255729A (en) Demodulation system
JPS5938780B2 (en) How to synchronize digital modems
JP2542470B2 (en) Data mode convergence apparatus and method
JPH01194613A (en) Automating equalizer initializing system
JPH06188788A (en) Adaptive automatic equalizer
US10505705B1 (en) Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin
JPS63228826A (en) Determined instruction controller and method of regulating the same
AU8982098A (en) Method for parameter estimation and receiver
US7312833B2 (en) Channel equalizing apparatus and method for digital television receiver
JP3224496B2 (en) Data receiving device
JP5245685B2 (en) Method, logic and system for adaptive equalizer control with online data pattern compensation
US5422606A (en) Automatic equalizer
JPH01194614A (en) Automatic equalizer
JPS63313908A (en) Automatic equalizer initialization system
JPH0865210A (en) Equalization of equalizer positioning and its circuit
JPH0136284B2 (en)
JPS631781B2 (en)