JPH01186673A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01186673A JPH01186673A JP63006481A JP648188A JPH01186673A JP H01186673 A JPH01186673 A JP H01186673A JP 63006481 A JP63006481 A JP 63006481A JP 648188 A JP648188 A JP 648188A JP H01186673 A JPH01186673 A JP H01186673A
- Authority
- JP
- Japan
- Prior art keywords
- bipolar transistor
- collector
- region
- operates
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000009826 distribution Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- -1 Phosphorus ions Chemical class 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
第６図は、本発明の一実施例のＢ ｔ ＣＭＯ５ＬＳＩ
の製造方法を説明するための断面図であり、５゛１は小
信号領域で動作するバイポーラトランジスタが形成され
る領域、５２は大信号領域で動作するバイポーラトラン
ジスタが形成される領域、５３はＰＭＯ３が形成される
領域を表している。DETAILED DESCRIPTION OF THE INVENTION FIG. 6 shows a B t CMO5LSI according to an embodiment of the present invention.
5 is a cross-sectional view for explaining the manufacturing method of the PMO3. represents the area where is formed.
同図において、Ｐ型の半導体基板６の表面には、Ｎ＋埋
込層７が形成され、その上には、シリコン単結晶がエピ
タキシャル成長され、膜厚１．７μｍのエピタキシャル
層５４が形成されている。In the figure, an N+ buried layer 7 is formed on the surface of a P-type semiconductor substrate 6, and a silicon single crystal is epitaxially grown thereon to form an epitaxial layer 54 with a thickness of 1.7 μm. .
つぎに、バイポーラトランジスタのコレクタ領域および
ＰＭＯ８のチャネル層となるＮウェルを形成するために
、エピタキシャル層５４に１２５Ｋ ｅ Ｖ、 ２
Ｘ １０１２／ｃｍ２のリンイオン打込みをし、バイポ
ーラトランジスタのコレクタ領域となるＮウェル８−３
、およびＰＭＯ８のチャネル層となるＮウェル８−４を
形成する［同図（ａ）］。Next, the epitaxial layer 54 was heated at 125 K e V, 2 to form an N-well that would become the collector region of the bipolar transistor and the channel layer of the PMO 8.
Phosphorus ions are implanted at a density of
, and an N well 8-4 which becomes a channel layer of PMO 8 [FIG. 2(a)].
その後、小信号領域で動作するバイポーラトランジスタ
５１のコレクタ濃度のみを高くするために、大信号領域
で動作するバイポーラトランジスタ５２およびＰＭＯ３
５３をホトレジスト５５でカバーした後、１２５ＫｅＶ
、１．８ｘ１０１３／ｃｍ２のリンイオン打込みをし、
高不純物濃度のＮウェル８−５を形成する［同図（ｂ）
］。Thereafter, in order to increase only the collector concentration of the bipolar transistor 51 that operates in the small signal region, the bipolar transistor 52 and PMO3 that operate in the large signal region
After covering 53 with photoresist 55, 125KeV
, 1.8x1013/cm2 phosphorus ion implantation,
An N well 8-5 with a high impurity concentration is formed [FIG. (b)
].
以上が、コレクタ濃度を決定するＮウェルのイオン打ち
込み条件である。The above are the ion implantation conditions for the N well that determine the collector concentration.
その後、１０００℃、９０分の水蒸気酸化でフィールド
酸化膜３１を５０００人の厚さに形成して素子分離を行
ない、ベース領域６３は、３０Ｋｅ Ｖ、 １ 、
５ Ｘ １０１４／ｃｄ（Ｄ；ｈつ素イ；ｌｒ’打込ミ
で形成した。Thereafter, a field oxide film 31 is formed to a thickness of 5,000 wafers by steam oxidation at 1,000° C. for 90 minutes to perform element isolation.
5 x 1014/cd (D; h element a; lr' implantation).
エミッタ領域６２は、エミッタ開口部形成後、８０Ｋｅ
Ｖ、５Ｘ１０１５／ｃ−のヒ素イオン打込みで形成した
。ベース６３を形成するイオン打込み工程の後の不純物
分布を調整する熱処理は、９５０℃、４０分の条件で行
なった［同図（Ｃ）］。The emitter region 62 is made of 80Ke after forming the emitter opening.
It was formed by arsenic ion implantation of V, 5X1015/c-. The heat treatment for adjusting the impurity distribution after the ion implantation step for forming the base 63 was performed at 950° C. for 40 minutes [FIG. 6(C)].
このように、従来同一の条件で形成されていた、バイポ
ーラトランジスタ５１のコレクタ領域と、ＭＯＳトラン
ジスタ５３のうち、チャネル層の導電型が、前記バイポ
ーラトランジスタのコレクタ領域の導電型と同一である
ＭＯＳトランジスタ５３のチャネル層とを別々に形成し
、前記コレク夕領域の不純物濃度を、チ♀ネル層の不純
物濃度よりも高くすれば、ＢｉＣＭＯ３ＬＳＩの動作速
度を向上させることができる。In this way, among the collector region of the bipolar transistor 51 and the MOS transistor 53, which were conventionally formed under the same conditions, the conductivity type of the channel layer is the same as the conductivity type of the collector region of the bipolar transistor. The operation speed of the BiCMO3LSI can be improved by forming the channel layer 53 separately and making the impurity concentration of the collector region higher than the impurity concentration of the channel layer.
さらに、バイポーラトランジスタ同士であっても、小信
号領域で動作するバイポーラトランジスタ５１のコレク
タ濃度と、大信号領域で動作するバイポーラトランジス
タ５２のコレクタ濃度とを別々に設定し、前記小信号領
域で動作するバイポーラトランジスタ５１のコレクタ濃
度を、大信号領域で動作するバイポーラトランジスタ５
２のコレクタ濃度よりも高くすれば、コレクタ・エミッ
タ間の耐圧を低下させること無＜ＢｉＣＭＯ３ＬＳＩの
動作速度を向上させることができる。Furthermore, even if bipolar transistors are used, the collector concentration of the bipolar transistor 51 that operates in a small signal region and the collector concentration of the bipolar transistor 52 that operates in a large signal region are set separately, and the collector concentration of the bipolar transistor 52 that operates in the small signal region is set separately. The collector concentration of the bipolar transistor 51 is set to
If the collector concentration is higher than No. 2, the operating speed of the BiCMO3LSI can be improved without lowering the breakdown voltage between the collector and emitter.
第１図は、上記した製造条件で製造したバイポーラトラ
ンジスタの不純物分布を表した図である。FIG. 1 is a diagram showing the impurity distribution of a bipolar transistor manufactured under the above manufacturing conditions.
同図において、点線はコレクタ濃度を高くしたバイポー
ラトランジスタの不純物分布、実線は通常のコレクタ濃
度を有するバイポーラトランジスタの不純物分布をそれ
ぞれ表し、とくに、４１はエミッタ領域、４２はベース
領域、４３はコレクタ濃度を高くしたバイポーラトラン
ジスタのコレクタ領域、４４はＭＯＳトランジスタのチ
ャネル層および通常のコレクタ濃度を有するバイポーラ
トランジスタのコレクタ領域の不純物分布を表している
。In the figure, the dotted line represents the impurity distribution of a bipolar transistor with a high collector concentration, and the solid line represents the impurity distribution of a bipolar transistor with a normal collector concentration. In particular, 41 is the emitter region, 42 is the base region, and 43 is the collector concentration. 44 represents the impurity distribution in the channel layer of a MOS transistor and the collector region of a bipolar transistor having a normal collector concentration.
同図より分るように、小信号領域で動作するバイポーラ
トランジスタのコレクタ濃度は約１×１０１７／ｃＩｆ
３であり、大信号領域で動作するバイポーラトランジス
タのコレクタおよびＭＯＳトランジスタのチャンネル層
濃度は約Ｉ Ｘ １０１６／ｃｍ−３であった。As can be seen from the figure, the collector concentration of a bipolar transistor operating in the small signal region is approximately 1×1017/cIf.
3, and the concentration of the collector of the bipolar transistor operating in the large signal region and the channel layer of the MOS transistor was about I x 1016/cm-3.
さらに、このような製造条件によって形成されたバイポ
ーラトランジスタの遮断周波数Ｆｔは、大信号領域で動
作するバイポーラトランジスタが５ＧＨｚであったのに
対して、コレクタ濃度を高くした小信号領域で動作する
バイポーラトランジスタでは８ＧＨｚとなり、約６０％
向上した。Furthermore, the cutoff frequency Ft of a bipolar transistor formed under such manufacturing conditions is 5 GHz for a bipolar transistor that operates in a large signal region, whereas it is 5 GHz for a bipolar transistor that operates in a small signal region with a high collector concentration. Then it becomes 8GHz, which is about 60%
Improved.
さらに、このトランジスタをＤＲＡＭ ＬＳＩに適用
した場合、ＤＲＡＭの遅延時間を３５ｎｓから′２８ｎ
ｓへと短縮することができた。Furthermore, when this transistor is applied to a DRAM LSI, the delay time of the DRAM increases from 35ns to '28nS.
It was possible to shorten it to s.
（発明の効果）
上記したように、ＢｉＣＭＯ５ＬＳＩにおいて、バイポ
ーラトランジスタのコレクタ領域の不純物濃度を、ＭＯ
Ｓトランジスタのチャネル層の不純物濃度より高くすれ
ば、その動作速度を速くすることができる。(Effects of the Invention) As described above, in BiCMO5LSI, the impurity concentration of the collector region of the bipolar transistor is
If the impurity concentration is higher than that of the channel layer of the S transistor, its operating speed can be increased.
さらに、小信号領域で動作するバイポーラトランジスタ
と、大信号領域で動作するバイポーラトランジスタとが
同一基板上に形成されたＩＣにおいて、小信号領域で動
作するバイポーラトランジスタのコレクタ濃度のみを高
くすれば、コレクタ・エミッタ間の耐圧を低下させるこ
と無く、その動作速度を向上させることができる。Furthermore, in an IC in which a bipolar transistor that operates in a small signal region and a bipolar transistor that operates in a large signal region are formed on the same substrate, if only the collector concentration of the bipolar transistor that operates in the small signal region is increased, the collector - The operating speed can be improved without reducing the withstand voltage between emitters.
第１図は本発明を適用したＢｉＣＭＯ３ＬＳＩの不純物
分布を示した図である。
第２図は本発明が適用されるＢｉＣＭＯ８ＬＳＩの断面
図である。
第３図は、バイポーラトランジスタの、遮断周波数とコ
レコタ濃度との関係を示した図である。
第４図は本発明が適用されるＤＲＡＭの構造を示した模
式図である。
第５図はコレコタ濃度の増大によって中性ベース幅が減
少する様子を示した模式図である。
第６図は本発明を適用したＢｉＣＭＯ３ＬＳＩの製造方
法を示した断面図である。
１・・・エミッタ、２・・・ベース、３・・・コレクタ
、１５・・・入力回路、１６・・・デコーダ、１７・・
・ワード線ドライバ、１８・・・メモリセル、１９・・
・センスアンプ、２０・・・出力回路、４１・・・エミ
ッタ領域の不純物分布、４２・・・ベース領域の不純物
分布、４３゜４４・・・コレクタ領域の不純物分布FIG. 1 is a diagram showing the impurity distribution of BiCMO3LSI to which the present invention is applied. FIG. 2 is a cross-sectional view of a BiCMO8LSI to which the present invention is applied. FIG. 3 is a diagram showing the relationship between cutoff frequency and collector concentration of a bipolar transistor. FIG. 4 is a schematic diagram showing the structure of a DRAM to which the present invention is applied. FIG. 5 is a schematic diagram showing how the neutral base width decreases as the concentration of Correcota increases. FIG. 6 is a sectional view showing a method of manufacturing BiCMO3LSI to which the present invention is applied. 1... Emitter, 2... Base, 3... Collector, 15... Input circuit, 16... Decoder, 17...
・Word line driver, 18...Memory cell, 19...
・Sense amplifier, 20... Output circuit, 41... Impurity distribution in emitter region, 42... Impurity distribution in base region, 43° 44... Impurity distribution in collector region
Claims (4)
有する半導体装置において、 前記バイポーラトランジスタのコレクタ領域の不純物濃
度は、小信号領域で動作するバイポーラトランジスタの
コレクタ領域の方が、大信号領域で動作するバイポーラ
トランジスタのコレクタ領域よりも高いことを特徴とす
る半導体装置。(1) In a semiconductor device having a plurality of bipolar transistors on the same substrate, the impurity concentration of the collector region of the bipolar transistor is such that the collector region of the bipolar transistor that operates in a small signal region operates in a large signal region. A semiconductor device characterized by having a collector region higher than that of a bipolar transistor.
トランジスタとを有する半導体装置において、 前記バイポーラトランジスタのコレクタ領域の不純物濃
度と前記ＭＯＳトランジスタのチャネル層の不純物濃度
とが、相異なることを特徴とする半導体装置。(2) Bipolar transistor and MOS on the same substrate
A semiconductor device comprising a transistor, wherein an impurity concentration in a collector region of the bipolar transistor and an impurity concentration in a channel layer of the MOS transistor are different from each other.
純物濃度が、前記ＭＯＳトランジスタのチャネル層の不
純物濃度より高いことを特徴とする特許請求の範囲第２
項記載の半導体装置。(3) The impurity concentration of the collector region of the bipolar transistor is higher than the impurity concentration of the channel layer of the MOS transistor.
1. Semiconductor device described in Section 1.
電型が、前記バイポーラトランジスタのコレクタ領域の
導電型と同一であることを特徴とする特許請求の範囲第
２項または第３項記載の半導体装置。(4) The semiconductor device according to claim 2 or 3, wherein the conductivity type of the channel layer of the MOS transistor is the same as the conductivity type of the collector region of the bipolar transistor.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63006481A JPH01186673A (en) | 1988-01-14 | 1988-01-14 | Semiconductor device |
| US07/253,666 US5121185A (en) | 1987-10-09 | 1988-10-05 | Monolithic semiconductor IC device including blocks having different functions with different breakdown voltages |
| KR1019880013159A KR970006220B1 (en) | 1987-10-09 | 1988-10-08 | Monolithic semiconductor ic device including blocks having different functions wiht different breakdown voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63006481A JPH01186673A (en) | 1988-01-14 | 1988-01-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01186673A true JPH01186673A (en) | 1989-07-26 |
Family
ID=11639666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63006481A Pending JPH01186673A (en) | 1987-10-09 | 1988-01-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01186673A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566217B1 (en) | 1996-01-16 | 2003-05-20 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing process for semiconductor device |
| JP2006196914A (en) * | 1993-09-27 | 2006-07-27 | Sgs Thomson Microelettronica Spa | Manufacturing method for integrated circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4852382A (en) * | 1971-11-01 | 1973-07-23 | ||
| JPS4979479A (en) * | 1972-12-06 | 1974-07-31 | ||
| JPS58212159A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS59177960A (en) * | 1983-03-28 | 1984-10-08 | Hitachi Ltd | Semiconductor device and manufacture thereof |
-
1988
- 1988-01-14 JP JP63006481A patent/JPH01186673A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4852382A (en) * | 1971-11-01 | 1973-07-23 | ||
| JPS4979479A (en) * | 1972-12-06 | 1974-07-31 | ||
| JPS58212159A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS59177960A (en) * | 1983-03-28 | 1984-10-08 | Hitachi Ltd | Semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196914A (en) * | 1993-09-27 | 2006-07-27 | Sgs Thomson Microelettronica Spa | Manufacturing method for integrated circuit |
| US6566217B1 (en) | 1996-01-16 | 2003-05-20 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing process for semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59177960A (en) | Semiconductor device and manufacture thereof | |
| JPH0348458A (en) | Bi-cmos integrated circuit and manufacture thereof | |
| JPS60163452A (en) | Integrated circuit with bipolar device and field effect device and method of producing same | |
| JP3186043B2 (en) | Method for manufacturing semiconductor device | |
| JPH01186673A (en) | Semiconductor device | |
| JPS6081864A (en) | Lateral type transistor | |
| JPS5830742B2 (en) | Junction field effect semiconductor device | |
| JPS63175463A (en) | Manufacture of bipolar mos integrated circuit | |
| JP2864863B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| JPS59124157A (en) | Complementary type semiconductor integrated circuit | |
| JPH03222357A (en) | Semiconductor device and manufacture thereof | |
| JP3231284B2 (en) | Method for manufacturing semiconductor device | |
| JPH045851A (en) | Manufacture of semiconductor device | |
| JPH0387059A (en) | Semiconductor integrated circuit | |
| JPS60105265A (en) | Manufacture of complementary type semiconductor device | |
| JPS6014512B2 (en) | Insulated gate field effect transistor | |
| JPH03270271A (en) | Semiconductor device and its manufacture | |
| JPH027462A (en) | Complementary bi-cmos process having isolated vertical p-n-p transistor | |
| JPS60154656A (en) | Semiconductor device and manufacture thereof | |
| JPH0411767A (en) | Semiconductor device and manufacture thereof | |
| JPS63144567A (en) | Manufacture of semiconductor device | |
| JPH0575033A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| JPH02226759A (en) | Manufacture of bicmos type semiconductor integrated circuit | |
| JPH04159721A (en) | Semiconductor device | |
| JPH0252423B2 (en) |