JPH01186627A - Preparation of passivation film of semiconductor device - Google Patents
Preparation of passivation film of semiconductor deviceInfo
- Publication number
- JPH01186627A JPH01186627A JP624488A JP624488A JPH01186627A JP H01186627 A JPH01186627 A JP H01186627A JP 624488 A JP624488 A JP 624488A JP 624488 A JP624488 A JP 624488A JP H01186627 A JPH01186627 A JP H01186627A
- Authority
- JP
- Japan
- Prior art keywords
- passivation film
- plasma cvd
- film
- plasma
- mosic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002161 passivation Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＭＯＳＩＣ等の半導体素子の表面にパシベー
ション膜（絶縁保護膜）を作成する半導体素子のパシベ
ーション膜作成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a passivation film for a semiconductor element, which forms a passivation film (insulating protective film) on the surface of a semiconductor element such as a MOSIC.
（従来の技術）
半導体素子、例えばＭＯＳＩＣの表面にパシベーション
膜を作成する従来技術には、１．２０Ｔｏｒｒの真空度
のデポジション圧力で、かつ、流量比２０程度のＮ、Ｏ
／ＳｉＨ，の使用ガス条件下で半導体素子表面にプラズ
マＣＶＤ処理を施して該表面にプラズマ５ｉｎｓ膜のパ
シベーション膜を作成するものがある。(Prior art) The conventional technology for forming a passivation film on the surface of a semiconductor device, for example, a MOSIC, involves using N, O, and O at a deposition pressure of 1.20 Torr vacuum and a flow rate ratio of about 20.
There is a method in which a plasma CVD process is performed on the surface of a semiconductor element under the gas conditions of /SiH, to form a passivation film of plasma 5ins on the surface.
（発明が解決しようとする問題点）
上記の従来技術では、プラズマＣＶＤ処理後のＭＯＳＩ
Ｃのしきい電圧（スレッショルド電圧：Ｖｔｈ）が激し
く変動する問題と、そのパシベーション膜の膜質が良く
ないためにエッチレイトが遅く後工程での時間が長くか
かる問題と、ウェハに対するストレスが大きくかかって
そのウェハが大きく反る問題とがある。(Problems to be Solved by the Invention) In the above conventional technology, MOSI after plasma CVD treatment
The problem is that the threshold voltage of C (threshold voltage: Vth) fluctuates rapidly, the quality of the passivation film is poor, resulting in a slow etch rate, which takes a long time in post-processing, and the stress on the wafer. There is a problem that the wafer is greatly warped.
（問題点を解決するための手段）
本発明は、このような問題点を解決するためにデポジシ
ョン圧力が１，３０Ｔｏｒｒ以上の真空度、使用ガスが
流量比１０以下のＮ、Ｏ／Ｓ、ｉ Ｈ４の条件下で半導
体素子表面にプラズマＣＶＤ処理を施して該表面にプラ
ズマＳｔ Ｏｘ膜のパシベーション膜を作成するもので
ある。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a vacuum with a deposition pressure of 1.30 Torr or more, and gases used such as N, O/S, and O/S with a flow rate ratio of 10 or less. A plasma CVD process is performed on the surface of a semiconductor element under iH4 conditions to form a passivation film of plasma St Ox film on the surface.
（実施例）
以下、本発明の実施例に係るパシベーション膜作成方法
を図面を参照して詳細に説明する。本実施例では１．３
５Ｔｏｒｒの真空度のデポジション圧力、流量比的７，
８のＳ ｉ Ｈ４／ Ｎ ２Ｏ（Ｎ ２Ｏ： ３５００
ｃｃ、５ｉＨａ： ４５０ｃｃ）（７）ガス条件下で半
導体素子表面にプラズマＣＶＤ処理を施して該表面にプ
ラズマ５ｉＯｙ膜のパシベーション膜を作成している。(Example) Hereinafter, a passivation film manufacturing method according to an example of the present invention will be described in detail with reference to the drawings. In this example, 1.3
Deposition pressure of 5 Torr vacuum, flow rate ratio 7,
8 S i H4/N2O (N2O: 3500
cc, 5iHa: 450cc) (7) Plasma CVD treatment is performed on the surface of the semiconductor element under gas conditions to form a passivation film of plasma 5iOy film on the surface.
第１図は縦軸に屈折率、横軸にＮ、ｏ／Ｓｉ Ｈ４のガ
ス流量比をとってプラズマ電力８０Ｗ１周波数４００ｋ
Ｈｚ、炉温３８０℃、デポジション圧力が実施例で１．
３５Ｔｏｒｒ、従来例で１．２ｏ’ｒｏｒｒの条件下で
、実施例と従来例との実験結果を対比して示す図である
。第１図から明らかなように、従来例によりパシベーシ
ョン膜を形成した場合の屈折率は流量比を変化させても
ほぼ１゜５付近と余り変化しないのに対して、本実施例
の場合の屈折率は流量比が２０〜４０では従来例と大き
な差がないが、流量比が２０以下からはその屈折率に差
が出てきて流量比が１０以下ではその屈折率に大きな差
（従来例で約１．５０、実施例で約１．７０）が生じて
いる。Figure 1 shows the refractive index on the vertical axis and the gas flow rate ratio of N and o/Si H4 on the horizontal axis.
Hz, furnace temperature of 380°C, and deposition pressure of 1.
FIG. 3 is a diagram showing a comparison of experimental results between the embodiment and the conventional example under conditions of 35 Torr and 1.2 o'rorr in the conventional example. As is clear from FIG. 1, the refractive index when a passivation film is formed according to the conventional example does not change much, staying around 1°5 even when the flow rate ratio is changed, whereas the refractive index in the case of this embodiment does not change much. There is no big difference in refractive index from the conventional example when the flow rate ratio is 20 to 40, but when the flow rate ratio is less than 20, there is a difference in the refractive index. approximately 1.50, approximately 1.70 in the example).
なお、実施例での１．７０という屈折率は、本実施例に
よるパシベーション膜がＳｔ ＯＮ膜が作成されている
と予想され、これはＳｉ ＯＮ膜を作るのに通常は５ｉ
Ｈａ、ＮＨ３、Ｎ２Ｏの３成分系が必要であるために、
各成分をコントロールして膜質管理することがむつかし
かったのが、本実施例では２成分系でのコントロールで
あるから膜質管理が容易となる。Note that the refractive index of 1.70 in this example is expected to be due to the fact that the passivation film in this example is a St ON film, which is different from the 5i
Since a three-component system of Ha, NH3, and N2O is required,
It was difficult to manage film quality by controlling each component, but in this embodiment, control is performed using a two-component system, making film quality management easy.
第２図は縦軸に等方性のドライエッチレイト（単位：オ
ングストローム７分）、横軸にＮ、Ｏ／ＳｉＨ，のガス
流量比にとって、プラズマ電力８０Ｗ１周波数４００ｋ
Ｈｚ、炉温３８０℃で、本実施例では真空度１．３５Ｔ
ｏｒｒのデポジション圧力、従来例では真空度１．２０
のデポジション圧力の成長条件下で実施例と従来例との
実験結果を対比して示す図である。第２図から明らかな
ように、流量比がＩＯでは、従来例のドライエッチレイ
トは４３０オングストロ一ム／分であるのに対して、本
実施例のそれは８２０オンダストロ一ム／分となり、本
実施例の方はパシベーション膜のエッチレイトで従来例
のほぼ２倍となる。Figure 2 shows the isotropic dry etch rate (unit: 7 angstroms) on the vertical axis and the gas flow rate ratio of N, O/SiH on the horizontal axis, plasma power of 80W, frequency of 400k.
Hz, furnace temperature 380°C, vacuum degree 1.35T in this example.
orr deposition pressure, conventional example vacuum degree 1.20
FIG. 3 is a diagram showing a comparison of experimental results between the example and the conventional example under growth conditions of deposition pressures of . As is clear from FIG. 2, when the flow rate ratio is IO, the dry etch rate of the conventional example is 430 angstroms/min, while that of the present example is 820 angstroms/min, and the dry etch rate of the present example is 820 angstroms/min. In the example, the etch rate of the passivation film is approximately twice that of the conventional example.
第３図は縦軸の上側にＮｃ ｈ （チャンネル）のＭＯ
ＳＩＣ，下側にＰｃｈのＭＯＳＩＣのしきい電圧（ｖｔ
ｈ ＞ 、横軸にＭＯＳＩＣへの配線後、プラズマＣ
ＶＤ処理後、熱処理後にとって実施例と従来例との実験
結果を対比して示す図である。In Figure 3, the MO of Nch (channel) is shown above the vertical axis.
SIC, Pch MOSIC threshold voltage (vt
h >, the horizontal axis shows plasma C after wiring to MOSIC
FIG. 4 is a diagram showing a comparison of experimental results between an example and a conventional example after VD treatment and heat treatment.
第３図から明らかなように、ＮｃｈのＭＯＳＩＣの配線
後では従来例と実施例とではしきい電圧がほぼ同一であ
るが、プラズマＣＶＤ処理後では大きな差が生じ、熱処
理後でも大きな差がある。また、ＰｃｈのＭＯＳＩＣの
配線後では従来例と実施例とはしきい電圧がほぼ同一で
あるが、プラズマＣＶＤ処理後では大きな差が生じ、熱
処理後ではその差は縮まるがやはり大きな差力（生じて
いる。As is clear from FIG. 3, the threshold voltages are almost the same between the conventional example and the example after Nch MOSIC wiring, but there is a large difference after plasma CVD treatment, and there is also a large difference after heat treatment. . In addition, after wiring the Pch MOSIC, the threshold voltages of the conventional example and the example are almost the same, but after plasma CVD treatment, a large difference occurs, and after heat treatment, the difference decreases, but there is still a large difference in voltage. ing.
また、従来例と本実施例とをウェハの反りで対比すると
、干渉顕微鏡で調べた結果、従来例では１００μｍとい
う大きな反りがあったのが、本実施例では６０μｍの小
さな反りに止どまった。Also, when comparing the conventional example and this example in terms of wafer warpage, as a result of examining it with an interference microscope, the conventional example had a large warp of 100 μm, but the present example had a small warp of 60 μm. .
（効果）
以上説明したことから明らかなように本発明によれば、
デポジション圧力が１．３０Ｔｏｒｒ以上の真空度、使
用ガスが流量比１０以下のＮ、０／ＳｉＨ，の条件下で
半導体素子表面にプラズマＣＶＤ処理を施して該表面に
プラズマＳｔｏｗ膜のパシベーション膜を作成するよう
にしたから、ＭＯＳＩＧのような半導体素子のプラズマ
ＣＶＤ処理後でのしきい電圧の変動が抑えられるととも
に、作成したパシベーション膜のエッチレイトは従来例
のそれのほぼ２倍となり、またウェハの反りも従来例よ
り小さくな−った。(Effects) As is clear from the above explanation, according to the present invention,
Plasma CVD treatment is performed on the surface of the semiconductor element under the conditions of a vacuum with a deposition pressure of 1.30 Torr or more and a gas used of N, 0/SiH with a flow rate ratio of 10 or less to form a passivation film such as a plasma Stow film on the surface. This method suppresses fluctuations in threshold voltage after plasma CVD processing of semiconductor devices such as MOSIG, and the etch rate of the created passivation film is almost twice that of the conventional method. The warpage was also smaller than that of the conventional example.
図は本発明の実施例に係り、第１図は従来例と実施例と
のパシベーション膜に関する屈折率を対比して示す図、
第２図は従来例と実施例とのパシベーション膜に対する
エッチレイトを対比して示す図（第３図は従来例と実施
例とのＭＯ８Ｉ’Ｃのしきい電圧を対比して示す図であ
る。The figure relates to an embodiment of the present invention, and FIG. 1 is a diagram showing a comparison of refractive index regarding the passivation film of the conventional example and the embodiment,
FIG. 2 is a diagram showing a comparison of etch rates for passivation films in a conventional example and an example (FIG. 3 is a diagram showing a comparison of threshold voltages of MO8I'C in a conventional example and an example).
Claims (1)
度、使用ガスが流量比１０以下のＮ＿２Ｏ／ＳｉＨ＿４
の条件下で半導体素子表面にプラズマＣＶＤ処理を施し
、該表面にプラズマＳｉＯ＿２膜のパシベーション膜を
作成することを特徴とする半導体素子のパシベーション
膜作成方法。(1) Vacuum degree with deposition pressure of 1.30 Torr or more, and N_2O/SiH_4 gas used with a flow rate ratio of 10 or less
1. A method for forming a passivation film for a semiconductor device, comprising performing plasma CVD treatment on the surface of the semiconductor device under the following conditions to form a passivation film of a plasma SiO_2 film on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP624488A JPH01186627A (en) | 1988-01-14 | 1988-01-14 | Preparation of passivation film of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP624488A JPH01186627A (en) | 1988-01-14 | 1988-01-14 | Preparation of passivation film of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01186627A true JPH01186627A (en) | 1989-07-26 |
Family
ID=11633087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP624488A Pending JPH01186627A (en) | 1988-01-14 | 1988-01-14 | Preparation of passivation film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01186627A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03219630A (en) * | 1990-01-25 | 1991-09-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JP2018508980A (en) * | 2015-01-09 | 2018-03-29 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Gate stack materials for semiconductor applications to improve lithography overlay |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59143362A (en) * | 1983-02-03 | 1984-08-16 | Fuji Xerox Co Ltd | Passivation film |
| JPS6236280A (en) * | 1985-08-08 | 1987-02-17 | Ueno Kikai Kogyo Kk | Cheese bobbin |
| JPS62291913A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | Formation of thin film |
| JPS6441244A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-01-14 JP JP624488A patent/JPH01186627A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59143362A (en) * | 1983-02-03 | 1984-08-16 | Fuji Xerox Co Ltd | Passivation film |
| JPS6236280A (en) * | 1985-08-08 | 1987-02-17 | Ueno Kikai Kogyo Kk | Cheese bobbin |
| JPS62291913A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | Formation of thin film |
| JPS6441244A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03219630A (en) * | 1990-01-25 | 1991-09-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JP2018508980A (en) * | 2015-01-09 | 2018-03-29 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Gate stack materials for semiconductor applications to improve lithography overlay |
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