JPH01185521A - Substrate for display device - Google Patents
Substrate for display deviceInfo
- Publication number
- JPH01185521A JPH01185521A JP63007400A JP740088A JPH01185521A JP H01185521 A JPH01185521 A JP H01185521A JP 63007400 A JP63007400 A JP 63007400A JP 740088 A JP740088 A JP 740088A JP H01185521 A JPH01185521 A JP H01185521A
- Authority
- JP
- Japan
- Prior art keywords
- address
- pattern
- semiconductor thin
- display device
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims description 24
- 239000010408 film Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 239000011159 matrix material Substances 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 2
- 239000011521 glass Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910003070 TaOx Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、アクティブマトリックス型表示装置用基板に
関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a substrate for an active matrix display device.
（従来の技術）
近年、非晶質シリコン（ａ−３ｉ）膜を用いた薄膜トラ
ンジスタ（以下ＴＰＴと略称）をスイッチング素子とし
て構成されるアクティブマトリックス型液晶表示装置が
注目されている。これは、安価なガラス基板が利用でき
ることにより、大面積、高精則、高画質且つ安価なパネ
ルデイスプレィが実現できる可能性があるからである。(Prior Art) In recent years, active matrix liquid crystal display devices configured with thin film transistors (hereinafter abbreviated as TPT) using an amorphous silicon (a-3i) film as switching elements have attracted attention. This is because the availability of inexpensive glass substrates makes it possible to realize large-area, high-definition, high-image-quality, and inexpensive panel displays.
従来、このような表示装置駆動用のＴＰＴとじては、第
３図に示すような逆スタツガ型のものが用いられている
。すなわち、ガラス基板１１の上にアドレス線及びゲー
トとなるパターン１２を形成し、ゲート絶縁膜１３．
ａ−３ｉ層１４． ｎ”ａ−３ｉ層１５を堆積し、ａ−
３ｉ層の島を形成する０次に、画素電極１６を形成した
後にソース・ドレイン電極及びデータ線１７を形成する
。このようなスタッガ型のＴＦＴを用いた表示装置用基
板では、Ｂ−８’ 、 Ｃ−Ｃ’部の段差部におけるア
ドレス線１２とデータ線１７とのショートを防ぐために
アドレス線金属層１２の層厚を厚くできない。ゲート絶
縁膜１３のカバレッジを良くするためには、アドレス線
１２の膜厚の約２倍以上の厚みが必要なためである。Conventionally, as a TPT for driving such a display device, an inverted stagger type TPT as shown in FIG. 3 has been used. That is, a pattern 12 serving as an address line and a gate is formed on a glass substrate 11, and a gate insulating film 13.
a-3i layer 14. Deposit n''a-3i layer 15, a-
After forming the 3i-layer island, the pixel electrode 16 is formed, and then the source/drain electrodes and the data line 17 are formed. In a display device substrate using such a staggered TFT, a layer of the address line metal layer 12 is used to prevent a short circuit between the address line 12 and the data line 17 at the stepped portions of B-8' and C-C'. It cannot be made thicker. This is because, in order to improve the coverage of the gate insulating film 13, the film thickness needs to be approximately twice or more than the film thickness of the address line 12.
アドレスラインの抵抗を下げるためには、第４図に示す
ようにアドレスライン上の絶縁膜１３にコンタクトホー
ル１８□、１８３を開口してその上に金属層１９を積層
することが知られている。しかし、コンタクトホール１
８を１０〜２０μｍ程度の細いアドレスライン上に開口
するには高いパターン精度と合わせ精度が必要であり、
パターニングプロセスが１回必要となる。特に、大画面
、高精細になった場合には、ガラス基板の変形のために
、このような精度を確保することは困難である。このた
め、製造コストの増加が避けられない。In order to lower the resistance of the address line, it is known to open contact holes 18□, 183 in the insulating film 13 on the address line and stack a metal layer 19 thereon, as shown in FIG. . However, contact hole 1
8 on a thin address line of about 10 to 20 μm requires high pattern precision and alignment precision.
One patterning process is required. Particularly in the case of large screens and high definition, it is difficult to ensure such precision due to the deformation of the glass substrate. For this reason, an increase in manufacturing costs is unavoidable.
（発明が解決しようとする課題）
以上のように、従来のアクティブマトリックス型デイス
プレィで、大画面、高精細デイスプレィを実現しようと
した場合、ガラス基板の変形によるマスク合わせが困難
になり、又、アドレスライン上のコンタクトホール開口
のためのマスクのコストの増大が避けられない。本発明
はこのようなで提供することを目的としている。(Problems to be Solved by the Invention) As described above, when attempting to realize a large screen, high-definition display using a conventional active matrix display, mask alignment becomes difficult due to deformation of the glass substrate, and address An increase in the cost of a mask for opening contact holes on the line is unavoidable. The present invention aims to provide such a solution.
（作 用）
第３図より明らかなように、アドレス、データ線間のシ
ョートを防ぐための絶縁膜１３は、Ｂ−８’のＴＦＴ部
、ｃ−ｃ’の交差部にあれば良く、他の部分にはなくて
も問題は生じない。このため、ゲート絶縁膜１３をａ−
５ｉ １４の下のみに残し他の部分を除去しても良い。(Function) As is clear from FIG. 3, the insulating film 13 for preventing short circuits between the address and data lines may be provided at the TFT portion of B-8' and the intersection of c-c'; There is no problem even if the part is not included. Therefore, the gate insulating film 13 is
It is also possible to leave only the portion under 5i 14 and remove the other portions.
このためには、ａ−５ｉの島１４と同一のパターンで絶
縁膜１３をエツチングすれば良い。For this purpose, the insulating film 13 may be etched in the same pattern as the island 14 of a-5i.
上に述べたように、Ｂ−８’、 Ｃ−Ｃ’のようなａ−
３ｉの島の部分だけ絶縁膜を残すことにより、アドレス
、データ間のショートは発生しない、その他の部分の絶
縁膜を除去することにより、高い合わせ精度。As mentioned above, a- like B-8', C-C'
By leaving the insulating film only on the 3i islands, short circuits between addresses and data do not occur. By removing the insulating film on other parts, high alignment accuracy is achieved.
パターニング精度を全く必要とせずに、アドレスライン
と他の積層金属をコンタクトできる。又、コンタクトホ
ール用のマスクは必要としないために、パターニングプ
ロセスを１回少なくすることができる。このように、本
発明によれば、コストを下げて提供することを目的とす
る。Address lines can be contacted with other laminated metals without requiring any patterning precision. Furthermore, since a mask for contact holes is not required, the number of patterning processes can be reduced by one. Thus, according to the present invention, it is an object of the present invention to provide a device at a reduced cost.
（課題を解決するための手段）
この発明にかかる表示装置用基板は、絶縁性基板上に形
成された複数のアドレス配線と、このアドレス配線、ま
たはその延長上に第１の絶縁膜を介して形成され前記ア
ドレス線をゲート配線として動作するトランジスタ領域
となる複数の半導体薄膜島状パターンと、前記アドレス
線に第２の島状絶縁膜を介して交差する複数のデータ配
線と、前記半導体薄膜島状パターン近傍の絶縁性基板上
に形成される複数の画素電極パターンと、前記半導体薄
膜島状パターンの一方側の端部上に形成され前記データ
配線に接続されるソース（ドレイン）電極と、前記半導
体薄膜島状パターンの他方側の端部上に形成され前記画
素電極パターンに接続されたドレイン（ソース）電極と
電極パターンで構成されたアクティブマトリックス型の
表示装置用基板において前記第１の絶縁膜が半導体薄膜
島状パターンと同一パターンにより形成され、かつ、前
記第１と第２の絶縁膜を除く前記アドレス配線および前
記データ線の少なくとも一方の露出部分に積層して形成
された導電膜を具備したことを特徴とするものである。(Means for Solving the Problems) A display device substrate according to the present invention includes a plurality of address wirings formed on an insulating substrate, and a first insulating film formed on the address wirings or an extension thereof. a plurality of semiconductor thin film island patterns that are formed and serve as transistor regions that operate with the address line as a gate wiring; a plurality of data wirings that intersect the address line via a second island insulating film; and the semiconductor thin film island. a plurality of pixel electrode patterns formed on an insulating substrate near the shaped pattern; a source (drain) electrode formed on one end of the semiconductor thin film island pattern and connected to the data wiring; The first insulating film in an active matrix display device substrate comprising a drain (source) electrode and an electrode pattern formed on the other end of the semiconductor thin film island pattern and connected to the pixel electrode pattern. is formed in the same pattern as a semiconductor thin film island pattern, and includes a conductive film laminated on exposed portions of at least one of the address wiring and the data line excluding the first and second insulating films. It is characterized by the fact that
また、導電膜がデータ配線導電膜で形成されていること
、さらに、半導体薄膜がアモルファスシリコンであるこ
とを特徴とする。本発明によれば、低コストで低いアド
レスライン抵抗を実現できる。Further, the present invention is characterized in that the conductive film is formed of a data wiring conductive film, and further that the semiconductor thin film is made of amorphous silicon. According to the present invention, low address line resistance can be realized at low cost.
（実施例）
以下、この発明の実施例につき図面を参照して説明する
。(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図に一実施例の表示装置用基板を示す。第１図にお
いて、１はガラス基板で、この上面にスパッタリング法
により厚さ２０００人のＴａ層２を堆積し、アドレスラ
インおよびゲートをパターニングする。次に、プラズマ
ＣＶＤ （化学気相堆積）法により、厚さ３０００人の
ＳｉＮｘ ３ 、厚さ２５００人のａ−３ｉ層４゜厚さ
３００人のｎ”ａ−３ｉ層５を連続して堆積し、ＴＦＴ
部および交差部の島をパターニングし、ケミカルドライ
エツチング（以下ＣＤＥ）によりエツチングする。次に
、厚さ１５００人のＩＴＯ（Ｉｎｄｉｕｍ Ｔｉｎ ０
ｘｉｄｅ）表示電極６をスパッタリングにより堆積し、
画素電極を形成する。次に、Ｍｏ／ＡΩ層をスパッタリ
ングにより堆積させ、ソース、ドレイン、データライン
１７およびアドレスライン２の積層部を形成する。さら
に、チャネル部のｎ”ａ−３ｉ層５にＣＤＨによりエツ
チングを施して表示用基板が完成する。FIG. 1 shows a display device substrate of one embodiment. In FIG. 1, reference numeral 1 denotes a glass substrate, on the upper surface of which a Ta layer 2 of 2000 nm thick is deposited by sputtering, and address lines and gates are patterned. Next, by plasma CVD (chemical vapor deposition) method, SiNx 3 with a thickness of 3000, an a-3i layer 4 with a thickness of 2500, and an n'' a-3i layer 5 with a thickness of 300 are successively deposited. , TFT
The islands at the parts and intersections are patterned and etched by chemical dry etching (hereinafter referred to as CDE). Next, ITO (Indium Tin 0) with a thickness of 1500
xide) Depositing the display electrode 6 by sputtering,
Form a pixel electrode. Next, a Mo/AΩ layer is deposited by sputtering to form the source, drain, data line 17 and address line 2 stack. Further, the n''a-3i layer 5 in the channel portion is etched by CDH to complete the display substrate.
取上の如くして得られた対角１０インチ（１９２Ｘ１４
４ｍｍ）の液晶デイスプレィのアドレスライン抵抗は１
３．５にΩで、従来の６７、２にΩに比し顕著な低減を
みた。Diagonal 10 inches (192X14
The address line resistance of a 4mm) LCD display is 1.
At 3.5Ω, a remarkable reduction was seen compared to the conventional 67.2Ω.
次に、第２図に本発明の別の実施例を示す。第２図にお
いて、ゲート絶縁膜３は、ＳｉＮｘ層３□とＳｉＯｘ層
３□を積層させて形成されている。また、アドレスライ
ンの抵抗をさらに下げるように交差部において、データ
ラインを１層目のＴａ層２とし、アドレスラインは２層
目の１２層７として形成している。Next, FIG. 2 shows another embodiment of the present invention. In FIG. 2, the gate insulating film 3 is formed by laminating a SiNx layer 3□ and a SiOx layer 3□. Further, in order to further reduce the resistance of the address line, at the intersection, the data line is formed as the first layer of Ta layer 2, and the address line is formed as the second layer of 12 layers 7.
取上の如くすることによって、アドレスラインの抵抗は
４００Ωが得られ、従来の６７．２にΩに比し顕著な低
減である。By doing as described above, the resistance of the address line is 400Ω, which is a remarkable reduction compared to the conventional resistance of 67.2Ω.
なお、ゲート絶縁膜としては、ＳｉＯｘ、 ＳｉＮｘに
限らず、ＴａＯｘやＡＱ、 ０３でも適する。また、半
導体としてはａ−３ｉに限らずポリシリコンでもよい。Note that the gate insulating film is not limited to SiOx and SiNx, but also TaOx, AQ, and 03 are suitable. Furthermore, the semiconductor is not limited to a-3i, but may also be polysilicon.
取上の如く、本発明によれば、コンタクトホールを設け
る従来の技術に比し高価で位置合わせの難かしいコンタ
クトホール用マスクが不要で、かつアドレスライン抵抗
を下げることができる。すなわち、コストを下げてデイ
スプレィの表示特性を向上させることができる顕著な利
点がある。As mentioned above, the present invention eliminates the need for a contact hole mask which is expensive and difficult to align, compared to the conventional technique of providing contact holes, and can reduce address line resistance. That is, there is a significant advantage that the display characteristics of the display can be improved while reducing the cost.
第１図は本発明の一実施例のアクティブマトリックス表
示装置基板を示すａは平面図、ｂはａのＡ−Ａ線断面図
、ＣはａのＢ−Ｂ線断面図、ｄはａのＣ−Ｃ線断面図、
第２図は別の実施例のアクティブマトリックス表示装置
基板を示すａは平面図、ｂはａのＡ−Ａ線断面図、Ｃは
ａのＢ−Ｂ線断面図、ｄはａのＣ−Ｃ線断面図、第３図
は従来例のアクティブマトリックス表示装置基板を示す
ａは平面図、ｂはａのＡ−Ａ線断面図、ＣはａのＢ−Ｂ
線断面図、ｄはａのＣ−Ｃ線断面図、第４図は別の従来
例のアクティブマトリックス表示装置基板を示すａは平
面図、ｂはａのＡ−Ａ線断面図、ＣはａのＢ−Ｂ線断面
図、ｄはａのＣ−Ｃ線断面図である。
１、−−−−−−−−ガラス基板
２、−−−−一−−−アドレス配、Ｗ（１層目金属）３
、−−−−−−−−ゲート絶縁膜
４、−−−−−−−−ａ−５ｉ層
５−一−−−−−−ｎ”ａ−５ｉ層
６−−−−−−−−ＩＴＯ表示電極FIG. 1 shows an active matrix display device substrate according to an embodiment of the present invention; a is a plan view, b is a cross-sectional view taken along line A-A of a, C is a cross-sectional view taken along line B-B of a, and d is a C-line view of a. - C line sectional view,
FIG. 2 shows an active matrix display device substrate according to another embodiment; a is a plan view, b is a cross-sectional view taken along the line A-A of a, C is a cross-sectional view taken along the line B-B of a, and d is a C-C cross-sectional view of a. 3 is a plan view of a conventional active matrix display device substrate, b is a sectional view taken along line A-A of a, and C is B-B of a.
4 is a plan view of another conventional active matrix display device substrate, b is a sectional view taken along line A-A of a, and C is a sectional view taken along line A of a. d is a sectional view taken along line C-C of a. 1, -------Glass substrate 2, ----1---Address arrangement, W (first layer metal) 3
, ---------- Gate insulating film 4, ----------a-5i layer 5-1------n''a-5i layer 6------ ITO display electrode
Claims (2)
、このアドレス配線、またはその延長上に第１の絶縁膜
を介して形成され前記アドレス線をゲート配線として動
作するトランジスタ領域となる複数の半導体薄膜島状パ
ターンと、前記アドレス線に第２の島状絶縁膜を介して
交差する複数のデータ配線と、前記半導体薄膜島状パタ
ーン近傍の絶縁性基板上に形成される複数の画素電極パ
ターンと、前記半導体薄膜島状パターンの一方側の端部
上に形成され前記データ配線に接続されるソース（ドレ
イン）電極と、前記半導体薄膜島状パターンの他方側の
端部上に形成され前記画素電極パターンに接続されたド
レイン（ソース）電極と電極パターンで構成されたアク
ティブマトリックス型の表示装置用基板において前記第
１の絶縁膜が半導体薄膜島状パターンと同一パターンに
より形成され、かつ、前記第１と第２の絶縁膜を除く前
記アドレス配線および前記データ線の少なくとも一方の
露出部分に積層して形成された導電膜を具備したことを
特徴とする表示装置用基板。(1) A plurality of address wirings formed on an insulating substrate, and a plurality of address wirings, or a plurality of transistor regions formed on the address wirings or their extensions via a first insulating film and operating with the address lines as gate wirings. a semiconductor thin film island pattern, a plurality of data lines crossing the address line via a second island insulating film, and a plurality of pixel electrodes formed on an insulating substrate near the semiconductor thin film island pattern. a source (drain) electrode formed on the other end of the semiconductor thin film island pattern and connected to the data wiring; In an active matrix type display device substrate comprising a drain (source) electrode connected to a pixel electrode pattern and an electrode pattern, the first insulating film is formed of the same pattern as the semiconductor thin film island pattern, and A substrate for a display device, comprising a conductive film laminated on an exposed portion of at least one of the address wiring and the data line excluding the first and second insulating films.
を特徴とする請求項１の表示装置用基板。(2) The display device substrate according to claim 1, wherein the conductive film is formed of a data wiring conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63007400A JPH01185521A (en) | 1988-01-19 | 1988-01-19 | Substrate for display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63007400A JPH01185521A (en) | 1988-01-19 | 1988-01-19 | Substrate for display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01185521A true JPH01185521A (en) | 1989-07-25 |
Family
ID=11664839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63007400A Pending JPH01185521A (en) | 1988-01-19 | 1988-01-19 | Substrate for display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01185521A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| JP2011176008A (en) * | 2010-02-23 | 2011-09-08 | Sony Corp | Thin film transistor structure, method of manufacturing the same, and electronic device |
-
1988
- 1988-01-19 JP JP63007400A patent/JPH01185521A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
| JP2011176008A (en) * | 2010-02-23 | 2011-09-08 | Sony Corp | Thin film transistor structure, method of manufacturing the same, and electronic device |
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