JPH01184276A - Method and device for sputtering - Google Patents
Method and device for sputteringInfo
- Publication number
- JPH01184276A JPH01184276A JP830588A JP830588A JPH01184276A JP H01184276 A JPH01184276 A JP H01184276A JP 830588 A JP830588 A JP 830588A JP 830588 A JP830588 A JP 830588A JP H01184276 A JPH01184276 A JP H01184276A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- filter
- sputtering
- power supply
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004544 sputter deposition Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 239000002245 particle Substances 0.000 claims abstract description 10
- 230000007423 decrease Effects 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 6
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 229910052786 argon Inorganic materials 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- -1 argon ion Chemical class 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 210000000078 claw Anatomy 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009313 farming Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はスパッタ成膜にかかわシ、特に多層配線構造を
持つ集積回路における配線用導体膜の好適なスパッタ膜
を形成できるスパッタ方法及びその装置に関するもので
ある。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to sputter film formation, and in particular to a sputtering method and apparatus for forming a sputter film suitable for a conductor film for wiring in an integrated circuit having a multilayer wiring structure. It is related to.
従来技術としては、特開昭６１−１１７２７３号に記載
されたものが知られていた。As a prior art, the one described in Japanese Patent Application Laid-open No. 117273/1983 was known.
上記従来技術においてはフィルタに電気的入力があるの
で常に大きな基板流入電流を確保しようとすると、フィ
ルタが過熱されるという課題があった。In the above-mentioned conventional technology, since there is an electrical input to the filter, there is a problem in that the filter becomes overheated when trying to always ensure a large current flowing into the substrate.
本発明の目的は実効的なフィルタへの電気的入力を低減
しながら、且つ大きなバイアススパッタ効果を確保でき
るようにしたスパッタ方法及びその装置を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to provide a sputtering method and apparatus that can ensure a large bias sputtering effect while effectively reducing the electrical input to the filter.
本発明は、上記目的を達成するために、基板及びフィル
タに付与する電位を共に周期性を有するようにしたので
同期して増減させることが可能となった。即ち本発明は
大きな基板流入電流が必要な時にのみ、フィルタを強く
電気的に励起することにある。そこで基板電極印加電源
のパルス的な増減に同期して、フィルタ電源の出力もパ
ルス的に増減する。このようなパルス的信号を発生する
電源をつくシ、これＫよってフィルタ用の高周波電源も
制御されるようにする。In order to achieve the above object, the present invention makes it possible to increase and decrease the potentials in synchronization because the potentials applied to the substrate and the filter both have periodicity. That is, the present invention is to strongly electrically excite the filter only when a large current flowing into the substrate is required. Therefore, in synchronization with the pulse-like increase and decrease of the power supply applied to the substrate electrode, the output of the filter power supply also increases and decreases in a pulse-like manner. When the power source that generates such a pulsed signal is turned on, the high frequency power source for the filter is also controlled by this.
このように基板及びフィルタに同期させて電位を付与し
たことによシ基板バイアス電力（流入電流）を増加させ
てもフィルタの変形はみうけられず、安定した付き廻シ
性の良好なスパッタ成膜を行うことができる。By applying a potential to the substrate and filter in synchronization in this way, the filter does not deform even when the substrate bias power (inflow current) is increased, resulting in stable sputtering film formation with good adhesion. It can be performed.
第１図は本発明に係るスパッタ方法を実施するスパッタ
装置の一実施例を示したものである。１は特開昭６１−
１１７２７３〜１１７２７５号公報に記載されているよ
うに、周知のプレーナマグネトロンスパッタ電極である
。２はターゲート、３はフィルタ、４は防着シールド板
、５は基板電極、６は基板（ウェハ）、７は基板バイア
ス用直流電源、８は電圧計、９は基板流入電流計である
。FIG. 1 shows an embodiment of a sputtering apparatus for carrying out the sputtering method according to the present invention. 1 is JP-A-61-
This is a well-known planar magnetron sputtering electrode, as described in Japanese Patent Nos. 117273 to 117275. 2 is a target gate, 3 is a filter, 4 is an anti-adhesion shield plate, 5 is a substrate electrode, 6 is a substrate (wafer), 7 is a DC power supply for substrate bias, 8 is a voltmeter, and 9 is a substrate inflow current meter.
１０はブロッキングコンデンサ、１１は通過型電力計、
１２はパルス電源、１３は１Ａ５６ＭＨｚ等の高周波電
源であシ、変調入力としてパルス電源１２の信号を用い
ることができる。10 is a blocking capacitor, 11 is a pass-through wattmeter,
12 is a pulse power source, 13 is a high frequency power source such as 1A56 MHz, and the signal from the pulse power source 12 can be used as a modulation input.
基板電極５には、直流基板バイアス電源７によシ負の電
圧が印加されておシ、その電圧と電流は、それぞれ電圧
計８及び電流計９にて監視される。A negative voltage is applied to the substrate electrode 5 by a DC substrate bias power supply 7, and the voltage and current are monitored by a voltmeter 8 and an ammeter 9, respectively.
直流基板バイアス電源７にはパルス電源１２が接続され
ておル、お互いの電圧が重畳されて、基板電極５に印加
される。これから説明する実験条件では、直流基板バイ
アス電源７の出力は常時−７０Ｖとした。パルス電源１
２の出力は、−１１０Ｖビークであり、両軍源の合成出
力は第２図に示す如・ ３ ・
き波形をしておシ、繰シ返し周波数５０ＫＨｚ、パルス
印加のデユーティ（第２図中のｔ、／１２）はほぼ５０
チ程度で使用する。A pulse power supply 12 is connected to the DC substrate bias power supply 7, and the voltages are superimposed on each other and applied to the substrate electrode 5. Under the experimental conditions described below, the output of the DC substrate bias power supply 7 was always -70V. Pulse power supply 1
The output of 2 is -110V peak, and the combined output of both sources has a waveform as shown in Figure 2.The repetition frequency is 50KHz, and the duty of pulse application (in Figure 2) t, /12) is approximately 50
Use it at around 100 degrees.
基板電極５の上に基板６を固定する。基板６は直径１０
０φ冒のシリコンウェハである。基板６は基板電極５か
らの爪の如き金具によって固定され、アルミ成膜中には
、アルミ膜と電気的接触を確保している。A substrate 6 is fixed onto the substrate electrode 5. The substrate 6 has a diameter of 10
It is a silicon wafer with a diameter of 0φ. The substrate 6 is fixed by a metal fitting such as a claw from the substrate electrode 5 to ensure electrical contact with the aluminum film during aluminum film formation.
フィルタ電源１５は、ＩＡ５６ＭＨｚのものであシ、マ
ツチングボックス（図示せず）を介し印加する。The filter power supply 15 is of IA 56 MHz, and is applied through a matching box (not shown).
フィルタ３への印加電力は通過型電力計１１にて監視す
る。The power applied to the filter 3 is monitored by a pass-through wattmeter 11.
フィルタ３には第３図の模式図に示すごとく井桁状の薄
板（厚さ１ ｍ ）を用いた。井桁の大きさは約９−×
約９ｗｍの正方形の開口を持ち、スパッタ粒子の進行方
向への長さは約１０ｍ１とした。フィルタ全体の直径は
φ１６０鱈である。As shown in the schematic diagram of FIG. 3, the filter 3 was a cross-shaped thin plate (thickness: 1 m). The size of the grid is approximately 9-×
It had a square opening of about 9 wm, and the length in the direction of propagation of sputtered particles was about 10 m1. The diameter of the entire filter is φ160.
基板６は直径１００＋ａ＋のシリコンウェハ１であシ本
発明に係わる成膜方法の付き廻シ性の調査のためには多
層配線構造にある配線層間の接続孔（以下スルーホール
）を模したテスト形状を持つサンプルウェハを用いた。The substrate 6 is a silicon wafer 1 with a diameter of 100+a+.In order to investigate the adhesion of the film forming method according to the present invention, a test shape is used that simulates a connection hole (hereinafter referred to as a "through hole") between wiring layers in a multilayer wiring structure. A sample wafer with a
基板６は基板電極５上に金属性のツメのごとき金具（図
示せず）で固定されＡ１成膜中には基板６上のＡ１膜は
基板電極５と電気的な接触を保つ。The substrate 6 is fixed onto the substrate electrode 5 with a metal fitting (not shown) such as a metal claw, and the A1 film on the substrate 6 maintains electrical contact with the substrate electrode 5 during the formation of the A1 film.
基板６とフィルタ３の基板側端面との距離及びターゲッ
ト２とフィルタ６のスパッタ電極側端面との距離はとも
に約３０１とじた。ターゲット２には直接８インチ（約
φ２００■）のＡｌ−１，５チＳ１をもちいた。The distance between the substrate 6 and the end surface of the filter 3 on the substrate side and the distance between the target 2 and the end surface of the filter 6 on the sputtering electrode side were both approximately 301 cm. As the target 2, an 8-inch (about φ200 mm) Al-1.5-chi S1 was directly used.
スパッタ装置として動作させるＫは真空槽（図示せず）
を適当な真空ポンプによって高真空（１ｏ−’〜１０＝
’Ｆｏｒｒ台）にまで排気する。その後アルゴンガス
を導入し、約Ａ５ｍ’Ｆｏｒｒの圧力とした。K is a vacuum chamber (not shown) operated as a sputtering device.
to a high vacuum (1o-'~10=
'Forr level). Thereafter, argon gas was introduced to create a pressure of about A5 m'Forr.
一方１五５６ＭＨｚの高周波電源１３は整合回路（図示
せず）とブロッキングキャパシタ１０とを介してフィル
タ３に接続されておシ、通過型電力計１１によシフィル
タ３に印加されている電力をモニタすることができる。On the other hand, a high frequency power source 13 of 1556 MHz is connected to the filter 3 via a matching circuit (not shown) and a blocking capacitor 10, and the power applied to the filter 3 is monitored by a pass-through wattmeter 11. can do.
スパッタ電源には負の高圧を印加しく図示せず）スパッ
タ電圧約５００Ｖ、スパッタ電流１０Ａで放電を行なっ
た。このときのスパッタガス圧力（アルゴンガス圧力）
は約１５ ｍ ｔｏｒｒである。A negative high voltage was applied to the sputtering power source (not shown), and discharge was performed at a sputtering voltage of about 500 V and a sputtering current of 10 A. Sputtering gas pressure at this time (argon gas pressure)
is approximately 15 m torr.
最初に基板電極５の電位をパルス的に駆動したときの実
験について説明する。このときフィルタ用の高周波電源
１３は５０ｗの出力に固定した。First, an experiment in which the potential of the substrate electrode 5 was driven in a pulsed manner will be described. At this time, the high frequency power supply 13 for the filter was fixed at an output of 50W.
基板電極５に印加される電圧波形を第２図に示す。基板
直流電源の出力は常時−７０Ｖであｐ、パルス電源の出
力は波高値−１１０ｖである。従って第２図に示す如く
尖頭値は一１８０ｖのパルス列的波形となる。The voltage waveform applied to the substrate electrode 5 is shown in FIG. The output of the substrate DC power supply is always -70V p, and the output of the pulse power supply has a peak value of -110V. Therefore, as shown in FIG. 2, the peak value becomes a pulse train-like waveform of -180V.
パルスの繰シ返し周期は第２図に示す如＜５２秒でｉｂ
、その５２秒のうちｔ４秒だけ基板バイアス電圧は一１
８０ｖとなる。基板バイアス電圧が最大値となっている
時間の比、１．、／１．２をデユーティ７アクタと呼ぶ
ことにする。デユーティ７アクタが０チから１００チへ
と増すにつれ、基板バイアス電圧の最大値が印加されて
いる時間が長くなる。The pulse repetition period is <52 seconds as shown in Figure 2.
, the substrate bias voltage is -1 for t4 seconds out of the 52 seconds.
It becomes 80v. Ratio of time during which the substrate bias voltage is at its maximum value, 1. , /1.2 will be called the duty 7 actor. As the duty 7 actor increases from 0 to 100, the time during which the maximum value of the substrate bias voltage is applied becomes longer.
このデユーティファクタをパラメータとしてスルーホー
ルへの付き廻漫性を評価した結果、一定の一１８０ｖの
基板バイアスではスルーホール中ニボイドが残シ、埋め
込むことができないが、間欠的にこの電圧を加えるので
あれば、０〜２０％のデユーティファクタでもボイドの
発生はなく、３０〜６０％のデユーティでは完全に埋め
込むことができる。デユーティ７アクタを７０９４以上
にしてゆ、ぐと、逆にボイドが発生し、一定の一１８０
Ｖの状態と等価となる。As a result of evaluating the pervasiveness of through holes using this duty factor as a parameter, it was found that with a constant substrate bias of 180 V, nivoids remain in the through holes and cannot be buried, but if this voltage is applied intermittently, If there is, voids will not occur even with a duty factor of 0 to 20%, and complete filling can be achieved with a duty of 30 to 60%. If you increase the duty 7 actor to 7094 or more, voids will occur and the constant 1180
This is equivalent to the state of V.
以上の如く、確実に埋め込むためにやや過剰な基板バイ
アス電圧を印加し、デユーティファクタの制御で巾広く
適正な条件を設定することができる。更にパルス電源１
２の出力はフィルタ用高周波電源１３１Ｃ供給されてお
シ、パルス電源１２の出力が負で大きくなると、高周波
電源１３の出方も増大する。As described above, it is possible to apply a slightly excessive substrate bias voltage to ensure embedding, and to set a wide range of appropriate conditions by controlling the duty factor. Furthermore, pulse power supply 1
The output of the pulse power source 12 is supplied to the filter high frequency power source 131C, and as the output of the pulse power source 12 becomes negative and large, the output of the high frequency power source 13 also increases.
パルス電源１２の繰シ返えし周波数５０ＫＨｚ 。The repetition frequency of the pulse power supply 12 is 50KHz.
デユーティファクタ５０％、スパッタ電力１０ＡＸ５０
０Ｖ、アルゴン圧力＆５ｎＴｏｒｒ 、フィルタ３には
、開口９ Ｘ ９ ｒｒＪ 、深さ１０ｍｍ、フィルタ
内の板厚１瓢で実験を行った。フィルタ用高周波電源１
３の出力を常に１００Ｗとしていた場合にはフィルタ３
の変形が認められたが、上記条件での使用では変形は発
生しなかった。Duty factor 50%, sputtering power 10AX50
Experiments were conducted at 0 V, argon pressure &5 nTorr, and filter 3 had an opening of 9 x 9 rrJ, a depth of 10 mm, and a plate thickness of 1 mm inside the filter. High frequency power supply for filter 1
If the output of filter 3 is always 100W, filter 3
deformation was observed, but no deformation occurred when used under the above conditions.
第４図はフィルタ３に印加する１＆５６ＭＨｚの電力と
基板流入電流との関係を示したもので、１０Ｗでは曲線
Ｃｌ０Ｗ、２０Ｗでは曲線Ｃ２０Ｗ、５０Ｗでは曲線ｃ
ｓｏｗ、 １ｏｏｗでは曲線Ｃ１００Ｗとなる。従って
スルホールにＡｔ膜を埋め込みができるように大きな基
板流入電流（例えば１ｏｏｗ）を与えてもフィルタ３の
変形は発生しない。Figure 4 shows the relationship between the 1 and 56 MHz power applied to the filter 3 and the substrate inflow current, with curve Cl0W for 10W, curve C20W for 20W, and curve c for 50W.
At sow and 1oow, the curve becomes C100W. Therefore, even if a large substrate inflow current (for example, 10OW) is applied so that the At film can be buried in the through holes, the filter 3 will not be deformed.
このように本実施例では、出来るだけＡ／、粒子の透過
率を低下させないように薄い板によシ組み立てられたフ
ィルタ３の筒状の形を利用し、スパッタ粒子の飛行方向
の指向性を与えるとともに、その筒の中でボーカソード
放電を発生させ、基板電極５に負の電圧を印加した時に
、大きな基板流入電流を得、良好な付き廻シ性のスパッ
タ成膜を行う。基板印加電圧波形はパルス状にして基板
６の過熱を防ぐ。この場合ターゲット２の材料（スパッ
タ材料）は、比較的融点の低い金属材料（具体的にはア
ルミ、アルミ合金が適している。）そとで第４図に示す
ように大きな基板流入電流を得るには、フィルタ３にそ
れに比例して大きな電力印加をおこなわなければならな
い。通常の使用状態では数１０１〜２００Ｗ程度である
。しかし基板バイアス直流電圧に同期させてフィルタ３
に印加する負の電位を増減させているので、大きな基板
流入電流が得られるようにしてもフィルタ３が昇温によ
って変形されることはなく、安定してスルホールへの付
き廻ｐ性をよくして成膜することができる。In this way, in this embodiment, the cylindrical shape of the filter 3, which is assembled with a thin plate, is utilized to avoid reducing the transmittance of particles as much as possible, and to improve the directivity of the sputtered particles in the flight direction. At the same time, when a void cathode discharge is generated in the tube and a negative voltage is applied to the substrate electrode 5, a large substrate inflow current is obtained, and a sputtering film with good adhesion is formed. The voltage waveform applied to the substrate is pulsed to prevent the substrate 6 from overheating. In this case, the target 2 material (sputtering material) is a metal material with a relatively low melting point (specifically, aluminum and aluminum alloys are suitable) to obtain a large substrate inflow current as shown in Figure 4. For this reason, a proportionately large amount of power must be applied to the filter 3. Under normal usage conditions, it is approximately several 101 to 200 W. However, the filter 3 is synchronized with the substrate bias DC voltage.
Since the negative potential applied to the filter 3 is increased or decreased, even if a large substrate inflow current is obtained, the filter 3 will not be deformed due to temperature rise, and the filter 3 will stably adhere to the through-holes and improve its stability. The film can be formed by
またブレーナマグネトロンバイアススパッタにおいてフ
ィルタ３に電気的な励起を与えることによシ、系内に新
たにフィルタ３を第３の電極とした第２の放電を発生さ
せる事によって果たすことができる。この時フィルタ材
料のスパッタリングの発生を抑止するためにできるだけ
低い電圧にて放電が発生するように、フィルタ３に筒状
の形状を持たさせ、フィルタ内でのホローカソード放電
を利用する。In addition, this can be achieved by applying electrical excitation to the filter 3 in Brehner magnetron bias sputtering to generate a second discharge in the system using the filter 3 as the third electrode. At this time, in order to suppress the occurrence of sputtering of the filter material, the filter 3 is made to have a cylindrical shape, and hollow cathode discharge within the filter is utilized so that discharge occurs at as low a voltage as possible.
また増大させ得るようＫなった基板流入電流すなわちア
ルゴンイオン電流によってアルミ原子の移動が活性化さ
れるようにイオンによる成膜中のアルミ膜の衝撃を有効
に行うことであるが、本発明に係るスパッタ装置では常
時基板電位を十分に大きな電流密度を得るように印加す
る必要はなく、たとえば間欠的に印加すれば良い。具体
的には間欠的に大きな負の電位になるように基板電極に
電圧を印加してやれば良い。基板の温度が徒に高いとア
ルミのフローはスルーホールの中に有効に入っていかな
い。スルーホールへの付き廻シ性を向上させるにはスル
ーホール周縁にスルーホールを塞ぐごとく成長するオー
バハングを抑制することが大切であり、本発明に係る技
術であればオーバハングが少し成長した時点で瞬間的に
基板バイアスを印加し、オーバハング部分のアルミ膜を
７０−させることで足シる。このような間欠的な基板電
圧の印加による付き廻シ性の改善はフィルタによる指向
性の付与によってもともとオーバハングの成長が遅いと
いうことを前提として、その上で本発明によって初めて
大きな効果を実現することができる。これにより必要以
上のアルゴンイオンの流入が無く、徒に基板温度を上昇
させることがない。Another object of the present invention is to effectively impact the aluminum film during film formation with ions so that the movement of aluminum atoms is activated by the substrate inflow current, that is, the argon ion current, which can be increased. In a sputtering device, it is not necessary to constantly apply a substrate potential to obtain a sufficiently large current density; for example, it may be applied intermittently. Specifically, a voltage may be applied to the substrate electrode intermittently so as to have a large negative potential. If the temperature of the board is unnecessarily high, the aluminum flow will not effectively enter the through hole. In order to improve the adhesion to the through hole, it is important to suppress the overhang that grows around the through hole so as to block the through hole. By applying a substrate bias and setting the aluminum film in the overhang part to 70°, the pressure is reduced. Improving the coverage by intermittent application of substrate voltage is based on the premise that overhang growth is originally slow due to directivity provided by the filter, and the present invention achieves a significant effect for the first time on that premise. Can be done. As a result, argon ions do not flow in more than necessary, and the substrate temperature does not increase unnecessarily.
また基板上に均一なアルゴンイオン電流密度を保つこと
は基板に対するプラズマの発生位置を相対的に移動せし
め、アルゴンイオンの流入を時間平均として基板上で均
一化することによシ達成できる。ウェハの中心と同軸状
に配置した電磁石散のマグネトロンスパッタ電極であ多
発生するプラズマリングの径を変化させうる本のでは、
プラズマリング径が小さい時にはウェハ基板の中心部分
で高いイオン電流密度が得られ、逆にプラズマリング径
が大きい時にはウェハ基板の外周部分で高いイオン電流
密度が得られる。これら２つの電流密度とその時に同時
に得られるそれぞれに対応した成膜速度の比は必ずしも
よく一致しない。即ちイオン電流密度が一様となるよう
にスパッタ電力をプラズマリングの移動に伴って変化さ
せると、今度は平坦な成膜速度分布が得られないという
結果になる。このとき本発明に係る技術ではフィルタの
電位を同時に制御することで、成膜速度分布とイオン電
流密度分布とを適切に設定することができる。Furthermore, maintaining a uniform argon ion current density on the substrate can be achieved by moving the plasma generation position relative to the substrate and making the inflow of argon ions uniform over the substrate on a time average basis. In the book, it is possible to change the diameter of the plasma ring that is often generated in a magnetron sputtering electrode with an electromagnetic scattering placed coaxially with the center of the wafer.
When the plasma ring diameter is small, a high ion current density is obtained at the center of the wafer substrate, and conversely, when the plasma ring diameter is large, a high ion current density is obtained at the outer periphery of the wafer substrate. The ratios of these two current densities and the corresponding film forming speeds obtained simultaneously do not necessarily match well. That is, if the sputtering power is changed along with the movement of the plasma ring so that the ion current density becomes uniform, a flat deposition rate distribution will not be obtained. At this time, with the technology according to the present invention, by simultaneously controlling the potential of the filter, it is possible to appropriately set the deposition rate distribution and the ion current density distribution.
以上説明したように本発明によれば、フィルタでの電力
損失が低減できるので、フィルタの大樹シな水冷を必要
とせず、安定したスルホールへの付き廻シ性をよくした
スパッタ成膜を行うことができる効果を奏する。As explained above, according to the present invention, power loss in the filter can be reduced, so that extensive water cooling of the filter is not required, and sputtering film formation can be performed with stable adhesion to through-holes. It produces the effect that can be achieved.
第１図は本発明の一実施例を示す図、第２図は基板バイ
アス印加電圧波形の一例を示す図、第６図はフィルタの
構造を示す図、第４図はフィルタの励振高周波電力と基
板流入電流との関係を示す図である。
１・・・マグネトロンスパッタ電極
２・・・ターゲット
３・・・フィルタ
５・・・基板電極
６・・・基板
７・・・基板バイアス用直流電源
１０・・・ブロッキングコンデンサ
１２・・・基板パルスバイアス電源
１３・・・高周波電源。
協農ト仝べ一項Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing an example of the substrate bias applied voltage waveform, Fig. 6 is a diagram showing the structure of the filter, and Fig. 4 is a diagram showing the excitation high frequency power of the filter. FIG. 3 is a diagram showing the relationship with substrate inflow current. 1... Magnetron sputtering electrode 2... Target 3... Filter 5... Substrate electrode 6... Substrate 7... DC power supply for substrate bias 10... Blocking capacitor 12... Substrate pulse bias Power supply 13...High frequency power supply. Section 1 of cooperative farming
Claims (1)
タによって飛行方向に指向性を与え、基板に間欠的に基
板バイアスを付与して基板に成膜を行うことを特徴とす
るスパッタ方法。 ２、上記フィルタに間欠的に、更に基板バイアスを同期
させてフィルタ電圧を印加させることを特徴とする請求
項１記載のスパッタ方法。 ３、スパッタ電源を成膜対象である基板に電位を付与す
るための基板電極を、該基板電極に周期性の電位を付与
するための基板電極電源と、上記スパッタ電極から出て
スパッタ粒子が基板に付着するまでの飛行空間に設けら
れ、スパッタ粒子の飛行方向に指向性を付与するフィル
タと、該フィルタに周期性の電位を付与するためのフィ
ルタ電源とを備えたことを特徴とするスパッタ装置。 ４、上記基板電極電源と上記フィルタ電源とが各々出力
を同期して増減すべく構成したことを特徴とする請求項
３記載のスパッタ装置。[Claims] 1. A film is formed on the substrate by imparting directivity in the flight direction to the sputtered particles emitted from the sputtering electrode using a filter and intermittently applying a substrate bias to the substrate. sputtering method. 2. The sputtering method according to claim 1, further comprising applying a filter voltage to the filter intermittently and in synchronization with a substrate bias. 3. A sputtering power source for applying a potential to the substrate on which a film is to be formed; a substrate electrode power source for applying a periodic potential to the substrate electrode; A sputtering apparatus comprising: a filter provided in a flight space until the sputtered particles adhere to the sputtered particles and imparting directivity to the flight direction of the sputtered particles; and a filter power source for imparting a periodic electric potential to the filter. . 4. The sputtering apparatus according to claim 3, wherein the substrate electrode power source and the filter power source are configured to increase and decrease their respective outputs in synchronization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63008305A JP2607582B2 (en) | 1988-01-20 | 1988-01-20 | Method and apparatus for film formation by sputtering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63008305A JP2607582B2 (en) | 1988-01-20 | 1988-01-20 | Method and apparatus for film formation by sputtering |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01184276A true JPH01184276A (en) | 1989-07-21 |
| JP2607582B2 JP2607582B2 (en) | 1997-05-07 |
Family
ID=11689440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63008305A Expired - Fee Related JP2607582B2 (en) | 1988-01-20 | 1988-01-20 | Method and apparatus for film formation by sputtering |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2607582B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5643422A (en) * | 1994-12-29 | 1997-07-01 | Nec Corporation | Reactive sputtering system for depositing titanium nitride without formation of titanium nitride on titanium target and process of depositing titanium nitride layer |
| US5744016A (en) * | 1994-10-20 | 1998-04-28 | Nec Corporation | Sputtering apparatus |
| WO1998020184A1 (en) * | 1996-11-04 | 1998-05-14 | Sola International Holdings Ltd. | Sputter coating apparatus |
| US6348238B1 (en) | 1999-03-12 | 2002-02-19 | Anelva Corporation | Thin film fabrication method and thin film fabrication apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6176668A (en) * | 1984-09-20 | 1986-04-19 | Fujitsu General Ltd | Sputtering device |
| JPS61156804A (en) * | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Formation of thin film |
| JPS61264174A (en) * | 1985-05-20 | 1986-11-22 | Ulvac Corp | Dc bias sputtering method |
-
1988
- 1988-01-20 JP JP63008305A patent/JP2607582B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6176668A (en) * | 1984-09-20 | 1986-04-19 | Fujitsu General Ltd | Sputtering device |
| JPS61156804A (en) * | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Formation of thin film |
| JPS61264174A (en) * | 1985-05-20 | 1986-11-22 | Ulvac Corp | Dc bias sputtering method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744016A (en) * | 1994-10-20 | 1998-04-28 | Nec Corporation | Sputtering apparatus |
| US5643422A (en) * | 1994-12-29 | 1997-07-01 | Nec Corporation | Reactive sputtering system for depositing titanium nitride without formation of titanium nitride on titanium target and process of depositing titanium nitride layer |
| WO1998020184A1 (en) * | 1996-11-04 | 1998-05-14 | Sola International Holdings Ltd. | Sputter coating apparatus |
| US6348238B1 (en) | 1999-03-12 | 2002-02-19 | Anelva Corporation | Thin film fabrication method and thin film fabrication apparatus |
| US6872289B2 (en) | 1999-03-12 | 2005-03-29 | Anelva Corporation | Thin film fabrication method and thin film fabrication apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2607582B2 (en) | 1997-05-07 |
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