JPH01171124U - - Google Patents

Info

Publication number
JPH01171124U
JPH01171124U JP6276588U JP6276588U JPH01171124U JP H01171124 U JPH01171124 U JP H01171124U JP 6276588 U JP6276588 U JP 6276588U JP 6276588 U JP6276588 U JP 6276588U JP H01171124 U JPH01171124 U JP H01171124U
Authority
JP
Japan
Prior art keywords
tuning
tuning voltage
circuit
memory
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6276588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6276588U priority Critical patent/JPH01171124U/ja
Publication of JPH01171124U publication Critical patent/JPH01171124U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Television Receiver Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の第1実施例の回路構成を示
すブロツク図、第2図は第1図のチユーニング電
圧メモリのマツプを示す図、第3図はこの考案の
第2実施例の回路構成を示すブロツク図、第4図
は第3図の主にチユーニング電圧発生回路の詳細
な構成を示すブロツク図、第5図は従来のチユー
ニング回路の構成を示すブロツク図、第6図はバ
ンドの受信チヤンネルとチユーニング電圧の関係
を示す特性図である。 11,31,41…同調電圧カウンタ、12,
32,42…制御回路、13,34,43,46
,47…PWMジエネレータ、14,16,54
,56,57,59,60,62…アナログスイ
ツチ、15,55,58,61…インバータ、1
7,18…可変抵抗、19,36,49,64,
70…ローパスフイルタ(LPF)、20,37
,50,53…アンプ、21,38,51…チユ
ーナ、33,45…チユーニング電圧メモリ、3
5…比較回路、39,52…バンド切換回路、4
4…チヤンネル表示信号作成回路、48…チユー
ニング電圧発生回路、65,71…バツフアアン
プ。
FIG. 1 is a block diagram showing the circuit configuration of a first embodiment of this invention, FIG. 2 is a diagram showing a map of the tuning voltage memory of FIG. 1, and FIG. 3 is a circuit diagram of a second embodiment of this invention. FIG. 4 is a block diagram mainly showing the detailed configuration of the tuning voltage generation circuit in FIG. 3, FIG. 5 is a block diagram showing the configuration of a conventional tuning circuit, and FIG. FIG. 3 is a characteristic diagram showing the relationship between a channel and a tuning voltage. 11, 31, 41...tuned voltage counter, 12,
32, 42...control circuit, 13, 34, 43, 46
, 47...PWM generator, 14, 16, 54
, 56, 57, 59, 60, 62...analog switch, 15, 55, 58, 61...inverter, 1
7, 18...variable resistor, 19, 36, 49, 64,
70...Low pass filter (LPF), 20, 37
, 50, 53... Amplifier, 21, 38, 51... Tuner, 33, 45... Tuning voltage memory, 3
5... Comparison circuit, 39, 52... Band switching circuit, 4
4...Channel display signal generation circuit, 48...Tuning voltage generation circuit, 65, 71...Buffer amplifier.

Claims (1)

【実用新案登録請求の範囲】 (1) 同調電圧カウンタのカウント値に従つて同
調電圧を発生し、同調動作を実行するチユーニン
グ回路において、 受信する周波数帯域の同調電圧の最大値及び最
小値を記憶するメモリと、 このメモリの記憶内容に応じて上記同調電圧カ
ウンタのカウント値を制御する制御手段と を具備したことを特徴とするチユーニング回路
。 (2) 同調電圧カウンタのカウント値に従つて同
調電圧発生回路で同調電圧を発生し、同調動作を
実行するチユーニング回路において、 受信する周波数帯域の同調電圧の最大値及び最
小値を記憶するメモリと、 このメモリの記憶内容に応じて上記同調電圧発
生回路の発生電圧を制御する制御手段と を具備したことを特徴とするチユーニング回路
[Claims for Utility Model Registration] (1) In a tuning circuit that generates a tuning voltage according to the count value of a tuning voltage counter and executes a tuning operation, the maximum and minimum values of the tuning voltage in the frequency band to be received are stored. 1. A tuning circuit comprising: a memory for controlling the tuning voltage counter; and a control means for controlling the count value of the tuning voltage counter according to the content stored in the memory. (2) In a tuning circuit that generates a tuning voltage in a tuning voltage generation circuit according to the count value of a tuning voltage counter and executes a tuning operation, a memory that stores the maximum and minimum values of the tuning voltage in the frequency band to be received; A tuning circuit comprising: a control means for controlling the voltage generated by the tuning voltage generation circuit according to the stored contents of the memory.
JP6276588U 1988-05-12 1988-05-12 Pending JPH01171124U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6276588U JPH01171124U (en) 1988-05-12 1988-05-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6276588U JPH01171124U (en) 1988-05-12 1988-05-12

Publications (1)

Publication Number Publication Date
JPH01171124U true JPH01171124U (en) 1989-12-04

Family

ID=31288324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6276588U Pending JPH01171124U (en) 1988-05-12 1988-05-12

Country Status (1)

Country Link
JP (1) JPH01171124U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577623A (en) * 1980-06-17 1982-01-14 Sanyo Electric Co Ltd Automatic sweeping device
JPS5948133B2 (en) * 1976-02-06 1984-11-24 新日本製鐵株式会社 Wet flue gas desulfurization method using slag

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948133B2 (en) * 1976-02-06 1984-11-24 新日本製鐵株式会社 Wet flue gas desulfurization method using slag
JPS577623A (en) * 1980-06-17 1982-01-14 Sanyo Electric Co Ltd Automatic sweeping device

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