JPH01169961A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01169961A JPH01169961A JP62333668A JP33366887A JPH01169961A JP H01169961 A JPH01169961 A JP H01169961A JP 62333668 A JP62333668 A JP 62333668A JP 33366887 A JP33366887 A JP 33366887A JP H01169961 A JPH01169961 A JP H01169961A
- Authority
- JP
- Japan
- Prior art keywords
- island
- substrate
- region
- breakdown strength
- island region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 31
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体装置の構造に関し、特には誘電体分離（
Ｄｉｅｌｅｃｔｒｉｃ ｌ５ｏｌａｔｉｏｎ以下ＤＩと
略す）構造を用いて高耐圧バイポーラ素子あるいは高耐
圧二重拡散型ＭＯ３Ｔｒ（ＤｏｕｂｌｅＤｉｆｆｕｓｅ
ｄＭＯ８Ｔｒ以下ＤＭＯ３と略す）と低耐圧バイポーラ
素子あるいは低耐圧ＤＭＯ８を同一基板上に形成した半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to the structure of semiconductor devices, and in particular to dielectric separation (
A high breakdown voltage bipolar element or a high breakdown voltage double diffused MO3Tr (Double Diffuse
This invention relates to a semiconductor device in which a low breakdown voltage bipolar element or a low breakdown voltage DMO8 are formed on the same substrate.
〈従来の技術〉
従来り、Ｉ構造を用いて高耐圧素子と低耐圧素子を別々
の島内に形成した半導体装置の一例を第４図に示す。<Prior Art> FIG. 4 shows an example of a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are conventionally formed in separate islands using an I structure.
ここではバイポーラ素子を形成した例について説明する
。Here, an example in which a bipolar element is formed will be described.
同図において、高耐圧素子部Ａと低耐圧素子部Ｂは、い
ずれも分離５ｉ０２１ａ、ｌｂに囲まれた単結晶シリコ
ン領域２ａ 、 ２ｂ内にバイポーラトランジスタを構
成するのに必要な拡散領域が形成され、分離５ｉ０２１
ａ、 ｌｂの外周は基板ポリシリコン３で埋め込まれて
いる。In the same figure, in both the high breakdown voltage element part A and the low breakdown voltage element part B, diffusion regions necessary for constructing a bipolar transistor are formed in single crystal silicon regions 2a and 2b surrounded by isolations 5i021a and lb. , separation 5i021
The outer peripheries of a and lb are filled with substrate polysilicon 3.
上記従来の装置では、Ｄ、Ｉ構造の加工に適用するプロ
セス技術の都合上、夫々の島の深さは同一であるという
制約がある。そのため島の深さは要求される最大のブレ
ークダウン電圧が得られる深さに揃えられていた。In the conventional apparatus described above, there is a restriction that the depth of each island is the same due to the process technology applied to processing the D and I structures. Therefore, the depth of the islands was adjusted to the depth that would provide the required maximum breakdown voltage.
〈発明が解決しようとする問題点〉
この場合低耐圧でも用が果せる素子に対してまでもが高
耐圧特性を持ち、かつ高耐圧部と同じ島の深さになって
いるという特長があり、このことはＮＰＮＴｒではコレ
クターエミッタ間の飽和電圧（ＶｃＥｓａｔ）が高くな
ってしまうこと及び高周波特性を著るしく阻害する原因
になっていた。<Problems to be solved by the invention> In this case, even an element that can be used even with a low withstand voltage has high withstand voltage characteristics, and the island has the same depth as the high withstand voltage part. This has caused the collector-emitter saturation voltage (VcEsat) to become high in the NPNTr and to significantly impede the high frequency characteristics.
この事情は低耐圧の縦型ＤＭＯ８を形成した場合も同様
であった。This situation was the same when a vertical DMO 8 with a low breakdown voltage was formed.
〈問題点を解決するための手段〉
上記問題点を解決するために、本発明では、Ｄ、Ｉ構造
を形成する際、特に低耐圧素子を形成する島領域につい
ては、島領域の底面を、基板表面から浅くなるように形
成して要求される耐圧に適した深さをもつ素子領域を形
成する。<Means for Solving the Problems> In order to solve the above problems, in the present invention, when forming the D and I structures, especially for the island regions where low breakdown voltage elements are formed, the bottom surface of the island regions is The device region is formed so as to be shallow from the substrate surface to have a depth suitable for the required withstand voltage.
く作 用〉
本発明の構造を用いることにより低耐圧ＮＰＮＴｒの場
合は飽和電圧（ＶｃＥｓａｔ）が低く高周波特性の優れ
たものと、また低耐圧ＤＭＯ８の場合はオン抵抗（Ｒｏ
ｎ）が低く電流特性の優れた素子と高耐圧素子を同一り
、Ｉ基板上に形成することができる。By using the structure of the present invention, the saturation voltage (VcEsat) is low and the high frequency characteristics are excellent in the case of the low breakdown voltage NPNTr, and the on-resistance (Ro
An element with low n) and excellent current characteristics and a high breakdown voltage element can be formed on the same I-substrate.
〈実施例〉
第１図に本発明の一実施例として、高耐圧ＮＰＮＴｒＨ
１と低耐圧ＮＰＮＴｒＬ１をポリシリコン層４を基板と
するり、Ｉ基板上に形成した場合を示す。Ｄ、Ｉ構造の
島領域１ｈ、１ｔの初期の深さは高耐圧部Ｈ１に合して
形成するものの、低耐圧ＮＰＮＴｒ Ｌｌを形成した島
領域１ｔでは、島領域の底面が平坦ではなく、エミッタ
直下部の誘電体が逆Ｖ溝状に***して基板表面からの深
さが浅く形成されている。上記エミッタ直下部の深さを
浅くすることによってエミッタ直下の活性領域における
コレクタ抵抗の低減が図れ、高耐圧ＮＰＮ Ｔｒ Ｈ＋
と電気的特性の優れた低耐圧ＮＰＮ Ｔｒ Ｌｌを同一
基板に作製し得る。はぼ平坦な底面をもつ島領域１ｈ及
び逆Ｖ溝状***を形成した底面をもつ島領域１ｔのいず
れの上記領域も、底面及び周壁な被う分離５ｉｎ２２ｈ
、２１に接して島領域の単結晶基板に高濃度に不純物が
導入されたサブコレクタ拡散３ｈ、３ｔが設けられ、該
サブコレクタ拡散３ｈ、３ｔは島領域の壁面に沿って基
板表面に設けられた電極取出し端まで延びて形成される
。<Example> FIG. 1 shows a high voltage NPNTrH as an example of the present invention.
1 and low breakdown voltage NPNTrL1 are formed using a polysilicon layer 4 as a substrate or on an I substrate. Although the initial depth of the island regions 1h and 1t of the D, I structure is formed to match the high breakdown voltage part H1, in the island region 1t where the low breakdown voltage NPNTr Ll is formed, the bottom surface of the island region is not flat and the emitter The dielectric material immediately below is raised in the shape of an inverted V-groove and is formed at a shallow depth from the substrate surface. By reducing the depth directly below the emitter, the collector resistance in the active region directly below the emitter can be reduced, resulting in a high breakdown voltage NPN Tr H+.
A low breakdown voltage NPN Tr Ll with excellent electrical characteristics can be fabricated on the same substrate. Both the island region 1h with a flat bottom surface and the island region 1t with a bottom surface formed with an inverted V-groove ridge have a covering separation of 5 inches 22h between the bottom surface and the peripheral wall.
. It is formed to extend to the electrode extraction end.
上記底部に高不純物濃度層を形成した島領域１ｈ。The island region 1h has a high impurity concentration layer formed at the bottom.
ｌｔ内に夫々ベース、エミッタ等の拡散領域が形成され
て高耐圧素子、低耐圧素子が形成されている。Diffusion regions such as a base and an emitter are formed in the lt to form a high breakdown voltage element and a low breakdown voltage element.
第２図は高耐圧ＤＭＯ８Ｈ２と低耐圧ＤＭＯ８Ｌ２をり
、Ｉ基板に形成した構造を示す。この場合も各島領域の
初期の深さは高耐圧素子に合せて形成し、低耐圧ＤＭＯ
８部Ｌ２ではチャンネルを形成するすべてのゲート電極
Ｇ直下に逆Ｖ溝を設け、電流通路の基板抵抗を低減した
構造である。本構造によって高耐圧ＤＭＯ８と低オン抵
抗で大電流の得られる低耐圧ＤＭＯ８を同一基板に形成
することができる０
本実施例においても前記実施例と同様に島領域の単結晶
底部及び周辺には基板表面に達する高濃度不純物層１３
ｈ、１３ｔが設けられ、底部が平坦な島領域１１ｈ内に
は高耐圧素子としてＤＭＯ８が、底部を***させたｎ型
島領域１１ｔには予め＃＃ｐウェルを形成し、これに通
常のＭＯＳ）ランジスタが形成されて誘電体分離された
半導体装置を構成する。FIG. 2 shows a structure in which a high breakdown voltage DMO8H2 and a low breakdown voltage DMO8L2 are formed on an I substrate. In this case as well, the initial depth of each island region is formed to match the high voltage element, and the low voltage DMO
In the 8th section L2, an inverted V groove is provided directly under all the gate electrodes G forming the channel, and the structure is such that the substrate resistance of the current path is reduced. With this structure, a high breakdown voltage DMO 8 and a low breakdown voltage DMO 8 that can obtain a large current with low on-resistance can be formed on the same substrate. High concentration impurity layer 13 reaching the substrate surface
A DMO8 is provided as a high voltage element in the island region 11h with a flat bottom, and a ##p well is formed in advance in the n-type island region 11t with a raised bottom, and a normal MOS ) A transistor is formed to constitute a dielectrically isolated semiconductor device.
次に上記り、Ｉ構造の半導体装置を製造する工程を第３
図（ａ）〜（Ｃ）を用いて説明する。Next, the step of manufacturing the I-structure semiconductor device described above is performed in the third step.
This will be explained using Figures (a) to (C).
（１００）結晶面をもつｎ型半導体基板３１に対して、
将来隣接素子間を分離させるに必要となる領域３２を異
方性エツチングすると同時に、将来低耐圧素子の活性領
域（ＮＰＮＴｒではエミッタ直下、縦型ＤＭＯ８ではチ
ャンネル直下）となる部分３３を上記分離領域部分３２
よりも浅く、かつ要求される耐圧に適した深さに異方性
エツチングしてＶ溝３５を作製する。For an n-type semiconductor substrate 31 having a (100) crystal plane,
At the same time, the region 32 that will be required to isolate adjacent devices in the future is anisotropically etched, and at the same time, the region 33 that will become the active region of the low voltage device in the future (directly below the emitter in NPNTr, directly below the channel in vertical DMO8) is etched into the isolation region. 32
The V-groove 35 is produced by anisotropic etching to a depth shallower than that and suitable for the required withstand voltage.
上記異方性エツチングはＫＯＨ等の液を用いて行なうが
、基板の結晶方位によってエツチング速度が極端に異な
り、基板表面にエツチング窓を残して耐エツチング性を
もつ例えば５ｉ０２からなる形成されたところでエツチ
ングはほとんど進行しなくなる。即ちエツチング溝３５
の深さはエツチング窓寸法によって幾何学的に決定され
る。従ってエツチング窓の大きさを、所望する特性、例
えば所望するブレークダウン電圧が得ら−ｈるように設
計する。The above-mentioned anisotropic etching is carried out using a liquid such as KOH, but the etching rate is extremely different depending on the crystal orientation of the substrate. will hardly progress. That is, the etching groove 35
The depth of is determined geometrically by the etched window dimensions. Therefore, the size of the etching window is designed to provide the desired characteristics, such as the desired breakdown voltage.
露出したＶ溝表面を含め、ｎ型基板表面にアンチモン或
いはヒ素等のｎ型不純物を高濃度に拡散し、サブコレク
タ或いはサブドレイン層３６を形成する。続いてＶ溝が
形成された基板表面に、誘電体分離のための厚い５ｉ０
２膜３７を第３図（ｂ）の如く形成し、該ＳｉＯ□膜３
７で被われた表面にポリシリコン３８を厚く堆積させる
。上記工程を終えた基板に対してｎ型半導体基板３１を
研磨し、ＭＯ８ＴｒやバイポーラＴｒ等の素子を形成す
るだめの分離された単結晶島領域の表面を露出させる。An n-type impurity such as antimony or arsenic is diffused at a high concentration on the surface of the n-type substrate including the exposed V-groove surface to form a sub-collector or sub-drain layer 36. Next, a thick 5i0 film for dielectric isolation is placed on the surface of the substrate where the V-groove is formed.
2 film 37 is formed as shown in FIG. 3(b), and the SiO□ film 3
Polysilicon 38 is thickly deposited on the surface covered with 7. After completing the above steps, the n-type semiconductor substrate 31 is polished to expose the surface of the isolated single crystal island region on which elements such as MO8Tr and bipolar Tr are to be formed.
露出した島領域に拡散等の工程を施こして第１図或いは
第２図に示した半導体装置を製造する。A process such as diffusion is performed on the exposed island region to manufacture the semiconductor device shown in FIG. 1 or 2.
上記実施例に限られるものではなく、相補型ＭＯ８やＰ
ＮＰ Ｔｒ等との共存も可能であり、Ｐ型基板を用いて
作製した場合のみならず、他の導電型基板を用いた場合
も同様に実施することができ、また相補型ＭＯ８Ｔｒや
ＰＮＰＴｒ等との共存も可能である。Not limited to the above embodiments, complementary MO8 and P
It is possible to coexist with NPTr, etc., and it can be performed not only when fabricated using a P-type substrate, but also when using other conductivity type substrates, and with complementary MO8Tr, PNPTr, etc. coexistence is also possible.
く効 果〉
以上本発明によれば、Ｄ、Ｉ構造の半導体装置において
、島領域に形成する半導体素子の特性に応じた島領域を
形成するだめ、一方の島領域に形成する半導体素子が他
の島領域に形成する半導体素子の犠性になることを防ぐ
ことができ、高耐圧素子、低耐圧素子のいずれもを特性
を損うことなく集積化することができる。Effects> As described above, according to the present invention, in a semiconductor device having a D, I structure, it is necessary to form an island region according to the characteristics of a semiconductor element formed in an island region, so that a semiconductor element formed in one island region is different from another. It is possible to prevent the semiconductor elements formed in the island region from becoming sacrificial, and it is possible to integrate both high-voltage elements and low-voltage elements without deteriorating their characteristics.
第１図は本発明による一実施例を示す半導体装置断面図
、第２図は本発明による他の実施例を示す断面図、第３
図（ａ）〜（ｃ）は第１図実施例の製造工程を説明する
図、第４図はり、Ｉ構造をとる従来の半導体装置の断面
図である。FIG. 1 is a cross-sectional view of a semiconductor device showing one embodiment of the present invention, FIG. 2 is a cross-sectional view of another embodiment of the present invention, and FIG.
Figures (a) to (c) are diagrams for explaining the manufacturing process of the embodiment in Figure 1, and Figure 4 is a sectional view of a conventional semiconductor device having an I structure.
Claims (1)
域内に素子を形成してなる集積回路装置において、 同一島領域内に表面からの深さが異なる島領域底面を設
け、 島領域内に、上記島領域底面に接し且つ基板表面にまで
接続する高不純物濃度層を設けてなることを特徴とする
半導体装置。[Scope of Claims] 1. In an integrated circuit device in which elements are formed in island regions electrically separated by a dielectric isolation method, the bottom surfaces of the island regions have different depths from the surface within the same island region. What is claimed is: 1. A semiconductor device comprising: a highly impurity-concentrated layer provided in the island region and in contact with the bottom surface of the island region and even to the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62333668A JPH01169961A (en) | 1987-12-24 | 1987-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62333668A JPH01169961A (en) | 1987-12-24 | 1987-12-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01169961A true JPH01169961A (en) | 1989-07-05 |
Family
ID=18268632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62333668A Pending JPH01169961A (en) | 1987-12-24 | 1987-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01169961A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327548A (en) * | 1989-06-24 | 1991-02-05 | Matsushita Electric Works Ltd | Insulation layer separating substrate and semiconductor device utilizing this substrate |
| US5014108A (en) * | 1990-05-15 | 1991-05-07 | Harris Corporation | MESFET for dielectrically isolated integrated circuits |
| US5270569A (en) * | 1990-01-24 | 1993-12-14 | Harris Corporation | Method and device in which bottoming of a well in a dielectrically isolated island is assured |
| US5306944A (en) * | 1990-01-24 | 1994-04-26 | Harris Corporation | Semiconductor structure within DI islands having bottom projection for controlling device characteristics |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158468A (en) * | 1980-02-25 | 1981-12-07 | Harris Corp | Method of manufacturing itnegrated circuit |
| JPS5910273A (en) * | 1982-06-30 | 1984-01-19 | Toshiba Corp | Integrated circuit device |
-
1987
- 1987-12-24 JP JP62333668A patent/JPH01169961A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158468A (en) * | 1980-02-25 | 1981-12-07 | Harris Corp | Method of manufacturing itnegrated circuit |
| JPS5910273A (en) * | 1982-06-30 | 1984-01-19 | Toshiba Corp | Integrated circuit device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327548A (en) * | 1989-06-24 | 1991-02-05 | Matsushita Electric Works Ltd | Insulation layer separating substrate and semiconductor device utilizing this substrate |
| US5270569A (en) * | 1990-01-24 | 1993-12-14 | Harris Corporation | Method and device in which bottoming of a well in a dielectrically isolated island is assured |
| US5306944A (en) * | 1990-01-24 | 1994-04-26 | Harris Corporation | Semiconductor structure within DI islands having bottom projection for controlling device characteristics |
| US5438221A (en) * | 1990-01-24 | 1995-08-01 | Harris Corporation | Method and device in which bottoming of a well in a dielectrically isolated island is assured |
| US5014108A (en) * | 1990-05-15 | 1991-05-07 | Harris Corporation | MESFET for dielectrically isolated integrated circuits |
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