JPH01169669A - High-speed numeric value arithmetic device - Google Patents
High-speed numeric value arithmetic deviceInfo
- Publication number
- JPH01169669A JPH01169669A JP32932387A JP32932387A JPH01169669A JP H01169669 A JPH01169669 A JP H01169669A JP 32932387 A JP32932387 A JP 32932387A JP 32932387 A JP32932387 A JP 32932387A JP H01169669 A JPH01169669 A JP H01169669A
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- JP
- Japan
- Prior art keywords
- data
- clock
- multiplier
- memory
- adder
- Prior art date
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- 238000004364 calculation method Methods 0.000 claims description 17
- 238000003860 storage Methods 0.000 claims description 7
- 238000012432 intermediate storage Methods 0.000 claims description 5
- 230000015654 memory Effects 0.000 abstract description 36
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000001186 cumulative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、記憶手段と乗算及び加算演算を行う演算手段
とを備える高速数値演算装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-speed numerical arithmetic device comprising a storage means and an arithmetic means for performing multiplication and addition operations.
（従来の技術）
従来、ベクトル演算方式によって演算を行うようなスー
パーコンピュータでは第４図に示すＪ：うな構成で、演
算器、メモリ等の間に多くのバスを接続して、各バスに
落すデータを制御していた。(Prior art) Conventionally, supercomputers that perform calculations using the vector calculation method have a J: U configuration shown in Figure 4, with many buses connected between calculation units, memories, etc. controlled the data.
第４図において、主メモリ１と副メモリ２と中間データ
や結果のデータを書き込んだり読み出したりするだめの
高速メモリ３を備えていて、それぞれ５本のバス４に乗
算器５と加算器６の出力端子と共に接続されている。又
、乗算器５ど加算器６の入力部Ａ、Ｂ、Ｃ，Ｄは図に示
１５本のバス４にそれぞれスイッチ（図示ｌず）で切り
替え接続されている。この構成では５本のバス４は３２
ビツト構成であるため１６０本の線が張り巡らされ、従
ってスイッチも膨大なものとなっている。又、ベクトル
演算方式計算機中に第５図に示す累積加算演算に用いる
のに便利な積和演算器が用いられている。第５図におい
て、第４図と同じ部分には同一の符号を付しである。こ
の演算器では例えば（１）式のような演算をする。In FIG. 4, a main memory 1, a secondary memory 2, and a high-speed memory 3 for writing and reading intermediate data and result data are provided, and a multiplier 5 and an adder 6 are connected to five buses 4, respectively. Connected together with the output terminal. Furthermore, the input sections A, B, C, and D of the multiplier 5 and the adder 6 are connected to the 15 buses 4 shown in the figure by switches (not shown), respectively. In this configuration, the five buses 4 are 32
Since it is a bit structure, 160 wires are stretched around it, and the number of switches is also enormous. Also, a product-sum calculator, which is convenient for use in cumulative addition calculations, as shown in FIG. 5, is used in the vector calculation type calculator. In FIG. 5, the same parts as in FIG. 4 are given the same reference numerals. This arithmetic unit performs calculations as shown in equation (1), for example.
Ｆｌ ＝Ｌａ −ｂ １
（＝１
乗算器５のＡ＠子にａを、Ｂ端子にｂＩ （ｉ−１，２
，・・・、ｎ）を与える。加算器６の出力Ｅ端子にＦ、
−１が表われ、Ｄ端子に加算データとしてフィードバッ
クされてＦｌが求められる。Fl = La -b 1 (=1 A to the A@ child of the multiplier 5, bI to the B terminal (i-1, 2
,...,n). F to the output E terminal of the adder 6,
-1 appears and is fed back to the D terminal as addition data to obtain Fl.
（発明が解決しようとする問題点）
ところで、このようなスーパーコンピュータでは極めて
多くのバスと、それに伴うスイッチが必要なので、プリ
ン１へ板によるＬＳＩの製作が内弁であった。又、積和
演算形の計算機では前述のように乗算器と加算器とを内
蔵しているにも拘わらず乗算器と加算器とを別個に用い
て乗算及び加算演算を同時に行わせることが出来ず、不
便であり不経済であった。(Problems to be Solved by the Invention) By the way, since such a supercomputer requires an extremely large number of buses and switches associated with them, it has been an internal matter to manufacture an LSI using a board to the printer 1. In addition, even though a product-sum calculation type calculator has a built-in multiplier and an adder as described above, it is not possible to use the multiplier and the adder separately to perform multiplication and addition operations at the same time. However, it was inconvenient and uneconomical.
本発明は上記の問題点に鑑みてなされたもので、その目
的は、各メモリのデータの出し入れをするためのバスの
所要数を節減し、又、乗算と加算の独立性を保証するこ
とのできる演算器を有する高速数値演算装置を実現する
ことにある。The present invention was made in view of the above problems, and its purpose is to reduce the number of buses required for transferring data to and from each memory, and to guarantee independence of multiplication and addition. The object of the present invention is to realize a high-speed numerical arithmetic device having a high-speed arithmetic unit.
（問題点を解決するための手段）
前記の問題点を解決する本発明は、記憶手段と乗算及び
加算演算を行う演算手段とを備える高速数値演算装置に
おいて、前記記憶手段からのデータを一時格納し、制御
信号に基づいて演算手段にデータを供給し演算結果の中
間データ及び最終データの授受を行う中間記憶手段ど、
該中間記憶手段を中心として前記記憶手段と前記各演算
手段とを接続する接続手段と、１クロツクリ−イクルを
２分して１クロックサイクル中に２段階の動作を行わけ
るシーケンス信号を発生して前記接続手段を時分割して
使用させると共にプログラムに従ってシステムを制御す
る制御手段とを具備することを特徴とするものである。(Means for Solving the Problems) The present invention for solving the above-mentioned problems is a high-speed numerical arithmetic device comprising a storage means and an operation means for performing multiplication and addition operations, in which data from the storage means is temporarily stored. intermediate storage means, etc., which supplies data to the calculation means based on the control signal and exchanges intermediate data and final data of the calculation results;
connecting means for connecting the storage means and each of the calculation means with the intermediate storage means as the center; and a sequence signal that divides one clock cycle into two and generates a sequence signal capable of performing two steps of operation in one clock cycle. The apparatus is characterized by comprising a control means for causing the connection means to be used in a time-sharing manner and for controlling the system according to a program.
（作用）
制御手段はシステムクロックに基づきシーケンス信号を
作り、１クロツクザイクルを時分割して１本の信号線を
２段階に用い、演算手段は中間記憶手段を介してデータ
の授受をして累積演算や独立演算を行う。(Function) The control means creates a sequence signal based on the system clock, time-divides one clock cycle and uses one signal line for two stages, and the calculation means sends and receives data via the intermediate storage means. Performs cumulative and independent operations.
（実施例）
＝３−
以下、図面を参照して本発明の実施例を詳細に説明する
。(Example) =3- Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
図において、１１は演算すべきデータを格納している主
メモリ、１２は三角関数や指数関数その他の関数のテー
ブルを格納していて、入力データをそれぞれの関数に変
換するための副メモリ、１３は主メモリ１１及び副メモ
リ１２からのデータを一旦格納し、乗算器１４と、加算
器１５へ演算のためにデータを送り、演算後の中間デー
タを格納して更に演算を継続するために乗算器１４と加
算器１５に中間データを送り、又、最終演算結果のデー
タを受けて主メモリ１１に転送する５ポートのレジタフ
ァイルである。１６は水平マイクロ命令等を格納してい
るマイクロプログラムメモリと、システムクロックによ
りシーケンス信号を発生し、主メモリ１１．副メモリ１
２．レジスタ１３９乗算器１４及び加算器１５のデータ
の授受等のタイミングを制御するシーケンサを内蔵して
おり、前記の各回路は制御回路１６のマイクロプログラ
ムによりシステムクロックの１クロツク毎に制御されて
いる。１７は乗算器１４の演算結果を一旦レジスタフア
イル１３に戻して演算結果を再び乗算器１４に入力さけ
るとによる遅れをなくして、直接乗算器１４の入力端子
に戻すだめのチエイニングバッファ、１８は加算器１４
に対してチエイニングバッファ１７と同様な動作をする
チエイニングバッファである。１つは外部回路２０と制
御回路１６とを接続し、データのやり取りを行う外部イ
ンターフェイス回路である。In the figure, 11 is a main memory that stores data to be calculated, 12 is a sub memory that stores tables of trigonometric functions, exponential functions, and other functions and is used to convert input data into the respective functions, and 13 temporarily stores the data from the main memory 11 and the sub memory 12, sends the data to the multiplier 14 and the adder 15 for calculation, stores the intermediate data after the calculation, and performs multiplication to continue the calculation. This is a 5-port register file that sends intermediate data to the adder 14 and the adder 15, and also receives and transfers the final calculation result data to the main memory 11. 16 is a microprogram memory that stores horizontal microinstructions, etc., and a main memory 11.16 that generates a sequence signal based on a system clock. Secondary memory 1
2. The register 139 has a built-in sequencer for controlling the timing of data exchange between the multiplier 14 and the adder 15, and each of the above-mentioned circuits is controlled by a microprogram of the control circuit 16 every clock of the system clock. Reference numeral 17 denotes a chaining buffer for directly returning the operation result of the multiplier 14 to the input terminal of the multiplier 14, eliminating the delay caused by once returning the operation result to the register file 13 and inputting the operation result to the multiplier 14 again. Adder 14
This is a chaining buffer that operates in the same way as the chaining buffer 17. One is an external interface circuit that connects the external circuit 20 and the control circuit 16 and exchanges data.
次に、上記のように構成された実施例の動作を第２図を
参照して説明する。制御回路１６に内蔵されているマイ
クロプログラムメモリには水平マイクロ命令が格納され
ている、水平マイクロ命令は例えば第３図のような構成
になっている。図において、２１ば主メモリ１１に与え
るデータ及び命令等が格納されてＪ３す、２２は副メモ
リ１２゜２３はレジスタファイル１３．２４は乗算器１
４゜２５は加算器１５にそれぞれ与えるデータや命令等
が格納されている場所である。水平方向に各部に与える
命令が並んでいて、１クロツク毎に同時に読み出し、書
き込み等が出来る構造になっている。この水平マイクロ
命令とシーケンサによってづベーＣの回路が１クロツク
毎に制御されている。Next, the operation of the embodiment configured as described above will be explained with reference to FIG. A horizontal microinstruction is stored in a microprogram memory built into the control circuit 16. The horizontal microinstruction has a configuration as shown in FIG. 3, for example. In the figure, 21 stores data and instructions to be given to the main memory 11, J3, 22 is a sub memory 12, 23 is a register file 13, and 24 is a multiplier 1.
4.degree. 25 is a location where data, instructions, etc. to be given to the adder 15 are stored. The instructions given to each part are lined up horizontally, and the structure is such that reading and writing can be performed simultaneously every clock. Based on this horizontal microinstruction and the sequencer, the circuit of the base C is controlled every clock.
第２図は全回路の動作のタイムチャートである。FIG. 2 is a time chart of the operation of all the circuits.
図において、（イ）は全回路を制御するシステムクロッ
ク、口）はシステムクロックによって制御回路１６内の
シーケンサが出力するシーケンス信号である。（ハ）は
レジスタファイル１３に制御回路１６から与えられる制
御信号で、〈口）のシーケンス信号の１ザイクルを前半
と後半に分（プて、例えば電位等で区分されて与えられ
ている。（ニ）は加算器１５の動作タイミングで、レジ
スタファイル１３からデータを前半に△、４！半にＢが
与えられて、△＋Ｂの演算を行っている。次のサイクル
ではΔ−８１その次のサイクルではＢ−Ａの演算を行っ
ている状況を示している。（ホ）は乗算器１４の動作タ
イミングで、レジスタファイル１３からそれぞれ前半に
Ｃ９後半にＤのデータを与えられてＣＸＤの演算を行っ
ている。くべ）は主メモリ１１の動作タイミングでそれ
ぞれ１クロツクナイクルの前半と後半とで合計２データ
のやり取りを１クロックサイクルで行っている、くト）
は副メモリ１２の動作タイミングで、（へ）と同様な動
作をしている。In the figure, (a) is a system clock that controls all circuits, and (a) is a sequence signal output by the sequencer in the control circuit 16 in response to the system clock. (C) is a control signal given from the control circuit 16 to the register file 13, in which one cycle of the sequence signal of <<1> is divided into the first half and the second half (by, for example, electric potential, etc.). D) is the operation timing of the adder 15, where data from the register file 13 is given △ to the first half and B to the 4! and half, and the operation of △+B is performed.In the next cycle, △-81 is given to the next data. The cycle shows a situation in which the operation of B-A is performed. (E) is the operation timing of the multiplier 14, and data of C9 and D are given in the first half and D in the second half from the register file 13 respectively, and the operation of CXD is performed. A total of two data exchanges are performed in one clock cycle, in the first half and the second half of one clock cycle, respectively, at the operating timing of the main memory 11.
is the operation timing of the sub-memory 12, and the operation is similar to (to).
第１図において、外部回路２０からデータ等を受けた外
部インターフェイス回路１９は制御回路１６に命令デー
タ等を書き込む。In FIG. 1, an external interface circuit 19 receives data etc. from an external circuit 20 and writes command data etc. to a control circuit 16.
制御回路１６はマイクロプログラムメモリに書き込まれ
た命令を各回路に与えて動作を制御する。The control circuit 16 provides instructions written in the microprogram memory to each circuit to control its operation.
先ず、主メモリ１１に演算ずべきデータを書き込み、又
、副メモリ１２のテーブルを使用すべきデータを副メモ
リ１２に送り込む。主メモリ１１及び副メモリ１２はそ
れぞれデータ及び演算命令をレジスタファイル１３に与
える。この時、１クロックサイクルに２データを１クロ
ックサイクルの前後半に分けて与えることができる。従
って、主メモリ１１とレジスタファイル１３とは１本の
線（実際はビット数×１）で繋がれて、２本の線で接続
されているのと同量のデータ又は命令を送り込むことが
できる。レジスタファイル１３は乗算器１４にＣとＤの
データを、加算器１５にＡとＢのデータを１タロツクサ
イクルに与えることができ、２木の線で４本分のデータ
を演算器に与えている。乗算器１４．加算器１５の演算
結果のデータはそれぞれレジスタファイルに戻されるが
、１クロツクの前半を乗算器１４が、後半を加算器１５
が使用して１クロツク内に両データをレジスタファイル
１３に送り込んでいる。累積演算を行う場合、この実施
例の一つの方式として乗算器１４はデータＣとデータＤ
を与えられて３クロツク後に演算結果をレジスタファイ
ル１３に戻しレジスタファイル１３は乗算器１４に１ク
ロツク後に再び戻すため、プログラム製作上混乱を生ず
るのでヂ、［イニングバッファ１７によって直らに乗算
器１４にデータを戻して遅れをないようにしている。チ
エイニングバッファ１７の制御端子にはデータを乗算器
１７に送り込むか否かを決める制御信号が入力されて、
データの行方を定めている。First, data to be calculated is written in the main memory 11, and data to be used in the table in the secondary memory 12 is sent to the secondary memory 12. Main memory 11 and sub memory 12 provide data and operation instructions to register file 13, respectively. At this time, two pieces of data can be divided into the first and second halves of one clock cycle and given in one clock cycle. Therefore, the main memory 11 and the register file 13 can be connected by one line (actually, the number of bits x 1), and the same amount of data or instructions can be sent as if they were connected by two lines. The register file 13 can provide C and D data to the multiplier 14 and A and B data to the adder 15 in one tarok cycle, and can provide data for four lines to the arithmetic unit using two tree lines. ing. Multiplier 14. The data of the calculation results of the adder 15 are each returned to the register file.
is used to send both data to the register file 13 within one clock. When performing an accumulation operation, the multiplier 14 uses data C and data D as one method in this embodiment.
is given and the result is returned to the register file 13 three clocks later, and the register file 13 returns it to the multiplier 14 one clock later, which causes confusion in program production. We are trying to get the data back so there are no delays. A control signal for determining whether or not to send data to the multiplier 17 is input to the control terminal of the chaining buffer 17.
It determines where the data will go.
チエイニングバッファ１８も加算器１５に対して同様に
働いている。図において、各回路を結ぶ線で実線と破線
のあるものは、１本の線で実線が１クロツクの前半、破
線が後半を用いて信号の授受を行っていることを示して
いる。結局、第１図の回路では主メモリ１１．副メモリ
１２．レジスタファイル１３９乗算器１４及び加算器１
５を結ぶ線が通常の場合１０本必要であるが、本実施例
では５本で間に合っている。Chaining buffer 18 also operates in the same way for adder 15. In the figure, lines connecting circuits with solid lines and broken lines indicate that the solid line uses the first half of one clock, and the broken line uses the second half to send and receive signals. After all, in the circuit of FIG. 1, the main memory 11. Secondary memory 12. Register file 139 Multiplier 14 and Adder 1
Normally, 10 lines are required to connect 5, but in this embodiment, 5 lines suffice.
以上説明したように本実施例によれば、１クロツクの前
後半にそれぞれ信号の授受を行ったので、信号を伝達す
る信号線は２倍の信号の授受が可能になり、結局、信号
線を１／２にすることができるようになり、又、スイッ
チが不必要となって回路構成が簡１１になった。As explained above, according to this embodiment, signals are sent and received in the first and second half of one clock, so the signal line that transmits signals can send and receive twice as many signals. The circuit configuration can now be reduced to 1/2, and the circuit configuration can be simplified by eliminating the need for a switch.
又、加算器と乗算器は積和演粋器としての動作の他のそ
れぞれ単独の加算器と乗算器として同時に使用すること
が可能になった。Moreover, the adder and the multiplier can be used simultaneously as a separate adder and a multiplier, in addition to operating as a product-sum operator.
又、レジスタファイルを用いることににり全中間データ
をレジスタファイル内に記憶でき、同時に同じデータを
複数ボートに読み出せるのでソフトウエア設計の自由度
が増した。Furthermore, by using a register file, all intermediate data can be stored in the register file, and the same data can be read out to multiple ports at the same time, increasing the degree of freedom in software design.
尚、本発明は本実施例に限定されるものではなく、次の
ような変形が考えられる。Note that the present invention is not limited to this embodiment, and the following modifications are possible.
■関数換算用のテーブルとしての副メモリを備えていな
いもの。■Those that do not have secondary memory as a table for function conversion.
■副メモリに１回アクセスするもの。■Things that access secondary memory once.
■主メモリに１回アクセスするもの。■Things that access main memory once.
■チエイニングバッファを備えていないもの。■Things that are not equipped with a chaining buffer.
（発明の効果）
以上詳細に説明したように、本発明によれば、各メモリ
と演算器を接続するための信号線及びバスを節減し、又
、スイッチが不要になり、乗算器と加算器の独立性が保
証されるようになり、実用上の効果は大きい。(Effects of the Invention) As described in detail above, according to the present invention, the number of signal lines and buses for connecting each memory and arithmetic unit can be reduced, switches are no longer required, and multipliers and adders can be connected to each other. independence is now guaranteed, which has a great practical effect.
第１図は本発明の一実施例のブロック図、第２図は第１
図の実施例のタイムチャート、第３図は水平マイクロ命
令の構成の説明図、第４図は従来の計算機のブロック図
、第５図は積和演鋒器の構成図である。
１１・・・主メモリ １２・・・副メモリ１
３・・・レジスタファイル １４・・・乗算器１５・・
・加算器 １６・・・制御回路１９・・・外
部インターフェイス回路
特許出願人 横河メディカルシステム株式会社第３図
第５図
第４ 図FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the configuration of a horizontal microinstruction, FIG. 4 is a block diagram of a conventional computer, and FIG. 5 is a configuration diagram of a sum-of-product operator. 11...Main memory 12...Sub memory 1
3... Register file 14... Multiplier 15...
・Adder 16... Control circuit 19... External interface circuit Patent applicant Yokogawa Medical Systems Co., Ltd. Figure 3 Figure 5 Figure 4
Claims (1)
る高速数値演算装置において、前記記憶手段からのデー
タを一時格納し、制御信号に基づいて演算手段にデータ
を供給し演算結果の中間データ及び最終データの授受を
行う中間記憶手段と、該中間記憶手段を中心として前記
記憶手段と前記各演算手段とを接続する接続手段と、１
クロックサイクルを２分して１クロックサイクル中に２
段階の動作を行わせるシーケンス信号を発生して前記接
続手段を時分割して使用させると共にプログラムに従つ
てシステムを制御する制御手段とを具備することを特徴
とする高速数値演算装置。In a high-speed numerical arithmetic device comprising a storage means and an arithmetic means for performing multiplication and addition operations, data from the storage means is temporarily stored, data is supplied to the arithmetic means based on a control signal, and intermediate data and final data of the arithmetic results are stored. intermediate storage means for transmitting and receiving data; connection means for connecting the storage means and each calculation means around the intermediate storage means;
Divide the clock cycle into two and create 2 in 1 clock cycle.
1. A high-speed numerical arithmetic device, characterized in that it comprises a control means for generating a sequence signal for performing a stepwise operation, for using the connection means in a time-sharing manner, and for controlling the system according to a program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62329323A JP2583774B2 (en) | 1987-12-25 | 1987-12-25 | High-speed numerical operation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62329323A JP2583774B2 (en) | 1987-12-25 | 1987-12-25 | High-speed numerical operation device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01169669A true JPH01169669A (en) | 1989-07-04 |
| JP2583774B2 JP2583774B2 (en) | 1997-02-19 |
Family
ID=18220172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62329323A Expired - Fee Related JP2583774B2 (en) | 1987-12-25 | 1987-12-25 | High-speed numerical operation device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2583774B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03138759A (en) * | 1989-10-23 | 1991-06-13 | Internatl Business Mach Corp <Ibm> | Signal processor |
| WO1993001541A1 (en) * | 1991-07-01 | 1993-01-21 | Fujitsu Limited | Apparatus for sum-of-product operation |
| JP2001216152A (en) * | 2000-01-28 | 2001-08-10 | Rooran:Kk | Logical integrated circuit and computer readable recording medium in which source of its cpu core is recorded |
| JP2007295128A (en) * | 2006-04-21 | 2007-11-08 | Daihen Corp | Logic integrated circuit and source of circuit for operation thereof, and computer readable recording medium for recording the same |
| US20220158508A1 (en) * | 2019-02-20 | 2022-05-19 | Nidec Corporation | Stator core, rotor core, and motor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58181165A (en) * | 1982-04-16 | 1983-10-22 | Hitachi Ltd | Vector operating processor |
| JPS61249161A (en) * | 1985-04-26 | 1986-11-06 | Nec Corp | Bus control system |
-
1987
- 1987-12-25 JP JP62329323A patent/JP2583774B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58181165A (en) * | 1982-04-16 | 1983-10-22 | Hitachi Ltd | Vector operating processor |
| JPS61249161A (en) * | 1985-04-26 | 1986-11-06 | Nec Corp | Bus control system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03138759A (en) * | 1989-10-23 | 1991-06-13 | Internatl Business Mach Corp <Ibm> | Signal processor |
| WO1993001541A1 (en) * | 1991-07-01 | 1993-01-21 | Fujitsu Limited | Apparatus for sum-of-product operation |
| JP2001216152A (en) * | 2000-01-28 | 2001-08-10 | Rooran:Kk | Logical integrated circuit and computer readable recording medium in which source of its cpu core is recorded |
| JP2007295128A (en) * | 2006-04-21 | 2007-11-08 | Daihen Corp | Logic integrated circuit and source of circuit for operation thereof, and computer readable recording medium for recording the same |
| US20220158508A1 (en) * | 2019-02-20 | 2022-05-19 | Nidec Corporation | Stator core, rotor core, and motor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2583774B2 (en) | 1997-02-19 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |