JPH01162345A - Alignment for fine semiconductor chip - Google Patents
Alignment for fine semiconductor chipInfo
- Publication number
- JPH01162345A JPH01162345A JP32197587A JP32197587A JPH01162345A JP H01162345 A JPH01162345 A JP H01162345A JP 32197587 A JP32197587 A JP 32197587A JP 32197587 A JP32197587 A JP 32197587A JP H01162345 A JPH01162345 A JP H01162345A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- alignment
- chip
- absorption layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000031700 light absorption Effects 0.000 claims description 20
- 230000003287 optical effect Effects 0.000 abstract description 5
- 238000010521 absorption reaction Methods 0.000 abstract description 4
- 230000010748 Photoabsorption Effects 0.000 abstract 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000011093 chipboard Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
微小半導体チップの位置合わせ方法の改良に関し、
容易に実施し得る位置合わせマークの形成により、微小
半導体チップの接続パッドと、接続基板の接続パッドと
を、高精度で接続することが可能な微小半導体チップの
位置合わせ方法の提供を目的とし、
微小半導体チップと接続基板とを位置合わせする方法で
あって、前記接続基板上に位置合わせマークを形成し、
前記微小半導体チップのチップ基板を透過する波長の入
射光を、前記微小半導体チップの接続パッドを形成して
いない面の裏面から照射し、前記裏面より、前記位置合
わせマークによる反射光と、微小半導体チップの光吸収
層の影像とのを確認し、位置合ゎせを行うよう構成する
。[Detailed Description of the Invention] [Summary] Regarding the improvement of the alignment method of micro semiconductor chips, the connection pads of the micro semiconductor chip and the connection pads of the connection board can be aligned by forming alignment marks that can be easily implemented. The purpose of the present invention is to provide a method for aligning micro semiconductor chips that can be connected with high precision, and the method includes the steps of: forming alignment marks on the connection substrate;
Incident light having a wavelength that transmits through the chip substrate of the micro semiconductor chip is irradiated from the back surface of the surface of the micro semiconductor chip on which connection pads are not formed, and from the back surface, the light reflected by the alignment mark and the micro semiconductor The configuration is such that the image of the light absorption layer of the chip is checked and the position is aligned.
本発明は、半導体チップの位置合わせ方法に係り、特に
微小半導体チップの位置合わせ方法の改良に関するもの
である。The present invention relates to a method for aligning semiconductor chips, and particularly to an improvement in a method for aligning micro semiconductor chips.
半導体チップを接続基板に高精度で位置合わせする方法
として種々の方法が行われているが、従来は半導体チッ
プのサイズが数ｌ程度と大きいので、容易に位置合わせ
することが可能であった。Various methods have been used to align a semiconductor chip with a connection substrate with high precision, but conventionally, since the size of a semiconductor chip is large, about several liters, alignment has been possible easily.
しかしながら近年になって、光半導体装置の半導体チッ
プのように数百μｍ程度の微小半導体チップを、数μｍ
以下の精度で位置合わせすることが必要になってきた。However, in recent years, micro semiconductor chips of about several hundred micrometers, such as semiconductor chips for optical semiconductor devices, have been
It has become necessary to align with the following accuracy.
以上のような状況から数百μｍ程度の微小半導体チップ
を数μｍ以下の精度で位置合わせすることが可能な微小
半導体チップの位置合わせ方法が要望されている。Under the above circumstances, there is a need for a method for aligning micro semiconductor chips that can align micro semiconductor chips with a precision of several micrometers or less.
従来の半導体チップの位置合わせ方法は、半導体チップ
のサイズが数ｌ程度であるため、第４図に示すように、
接続基板２２上にリソグラフィー技術により位置合わせ
マーク２３を形成し、この位置合わせマーク２３とチッ
プ基板２１ａの外形とを用いて位置合わせする方法が行
われている。In the conventional semiconductor chip alignment method, since the size of the semiconductor chip is about several liters, as shown in FIG.
A method is used in which an alignment mark 23 is formed on the connection substrate 22 by lithography technology, and alignment is performed using the alignment mark 23 and the outer shape of the chip substrate 21a.
この場合は、半導体チップのサイズが大きいので、半導
体チップの外形切断精度が多少悪くても、接続パッド間
のズレが許容可能な範囲内におさまっていた。In this case, since the size of the semiconductor chip is large, even if the accuracy of cutting the outline of the semiconductor chip is somewhat poor, the misalignment between the connection pads is within an allowable range.
以上説明の従来の半導体チップの位置合わせ方法で問題
となるのは、位置合わせマークと半導体チップの外形と
を用いて位置合わせすることである。The problem with the conventional semiconductor chip alignment method described above is that alignment is performed using alignment marks and the outer shape of the semiconductor chip.
即ち、外形サイズが数百μｍ〜１龍程度の半導体チップ
の場合には、半導体チップの外形切断精度が悪いと、位
置合わせマークと半導体チップの外形とを用いて位置合
わせすると、接続パッド間のズレが許容可能な範囲内に
おさまらなくなるのである。In other words, in the case of a semiconductor chip with an external size of several hundred μm to about 100 μm, if the accuracy of cutting the external shape of the semiconductor chip is poor, when aligning using the alignment mark and the external shape of the semiconductor chip, the connection pads may be The deviation will no longer be within an acceptable range.
本発明は以上のような状況から、容易に実施し得る位置
合わせマークの形成により、微小半導体チップの接続パ
ッドと、接続基板の接続バ・ノドとを、高精度で接続す
ることが可能な微小半導体チップの位置合わせ方法の提
供を目的としたものである。In view of the above-mentioned circumstances, the present invention has been devised to form a microscopic device that can connect the connecting pad of a microscopic semiconductor chip and the connecting bar/nod of a connecting board with high precision by forming alignment marks that can be easily implemented. The purpose is to provide a method for aligning semiconductor chips.
上記問題点は、微小半導体チップと接続基板とを位置合
わせする方法であって、前記接続基板上に位置合わせマ
ークを形成し、前記微小半導体チップのチップ基板を透
過する波長の入射光を、前記微小半導体チップの接続パ
ッドを形成していない面の裏面から照射し、前記裏面よ
り、前記位置合わせマークによる反射光と、微小半導体
チ１．プの光吸収層の影像とのを確認し、位置合わせを
行う本発明による微小半導体チ・ノブの位置合わせ方法
によって解決される。The above-mentioned problem is a method of aligning a micro semiconductor chip and a connection board, in which an alignment mark is formed on the connection board, and incident light of a wavelength that passes through the chip board of the micro semiconductor chip is directed to the The light is irradiated from the back side of the surface on which connection pads are not formed on the micro semiconductor chip, and from the back surface, the light reflected by the alignment mark and the light reflected by the micro semiconductor chip 1. This problem is solved by the method of aligning a micro semiconductor chip knob according to the present invention, which performs alignment by checking the image of the optical absorption layer of the tip.
即ち本発明においては、接続基板上に位置合わせマーク
を形成し、この接続基板に搭載する微小半導体チップの
チップ基板を透過する波長の入射光を、この微小半導体
チップの接続パッドを形成していない面から照射すると
、この入射光は光吸収層が形成されている部分では吸収
されて全く反射せず・光吸収層が形成されていない部分
で番よ透一４＝
過し、その下に形成した位置合わせマークで反射するの
で、この位置合わせマークの形状を認識することが可能
である。That is, in the present invention, alignment marks are formed on the connection board, and incident light of a wavelength that transmits through the chip substrate of the micro semiconductor chip mounted on the connection board is transmitted to the connection pad of the micro semiconductor chip. When irradiated from the surface, this incident light is absorbed in the area where the light absorption layer is formed and is not reflected at all.It passes through the area where the light absorption layer is not formed, and the light is formed below it. The shape of the alignment mark can be recognized because it is reflected by the alignment mark.
この位置合わせマークの形状の反射光と光吸収層の影像
とを位置合わせすることにより、微小半導体チップの接
続パッドと、接続基板の接続ツク・ノドとを、高精度で
接続することが可能となる。By aligning the reflected light in the shape of this alignment mark with the image of the light absorption layer, it is possible to connect the connection pads of the micro semiconductor chip and the connection holes of the connection board with high precision. Become.
以下第１図〜第３図について本発明の一実施例を説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
微小半導体チップ１は第１図（ａｌ及び第２図（ｂ）に
示すように、２００μｍ Ｘ ２００μｍ×厚さ約１０
０μｍのインジュウム燐（ＩｎＰはりなるチ・ノブ基板
１ａの表面に、直径１０μＭ×厚さ１．５μｍのインジ
ュウム゛力゛リウム・砒素（ＩｎＧａＡｓ）よりなる光
吸収層１ｂと・４個の４０μｍ角×厚さ１．５μｍのイ
ンジュウム°ガリウム・砒素（ＩｎＧａＡｓ）よりなる
光吸収層１ｂ’が形成され、この光吸収層１ｂ、 ｌｂ
’の表面にインジュウム燐（ＩｎＰ）よりなる厚さ１μ
ｍの透明層１ｃ＋ ｌｃ’が形成され、更にその上に接
続パッドｌｃｌ、 １ｔＪ’が形成されている。As shown in FIG. 1 (al) and FIG. 2 (b), the micro semiconductor chip 1 has a size of 200 μm x 200 μm x thickness of approximately 10
On the surface of the 0 μm indium phosphorus (InP) chip substrate 1a, there is a light absorption layer 1b made of indium phosphorus (InGaAs) with a diameter of 10 μM and a thickness of 1.5 μm. A light absorption layer 1b' made of indium gallium arsenide (InGaAs) with a thickness of 1.5 μm is formed, and the light absorption layers 1b, lb
1μ thick made of indium phosphorus (InP) on the surface of
m transparent layers 1c+lc' are formed, and connection pads lcl, 1tJ' are further formed thereon.
一方、接続基板２の表面には上記の接続パッド１ｄに接
続される接続パッド２ａ及び接続パッド１ｄ’に接続さ
れる接続パッド２ａ１ が形成されている。On the other hand, on the surface of the connection board 2, a connection pad 2a connected to the connection pad 1d and a connection pad 2a1 connected to the connection pad 1d' are formed.
図示のようにチップ基板１ａを透過する波長１．３μｍ
の入射光４を照射すると、チップ基板１ａのみの部分を
透過した入射光４は、接続基板２上に金属を蒸着して形
成した環状の位置合わせマーク３で反射し、この環状の
反射光５は図示のように反射する。As shown in the figure, the wavelength transmitted through the chip substrate 1a is 1.3 μm.
When the incident light 4 of is reflected as shown.
一方、光吸収層１ｂの部分に照射された入射光４はこの
光吸収層１ｂで吸収されるので、第１図（ｂｌに示すよ
うな黒丸となって見える。On the other hand, since the incident light 4 irradiated onto the light absorption layer 1b is absorbed by the light absorption layer 1b, it appears as a black circle as shown in FIG. 1 (bl).
チップ基板１ａの位置を微調整して、上記の環状の反射
光の真中に上記の黒丸がくるようにすると、微小半導体
チップ１の接続パッド１ｄの中心と接続基板２の接続パ
ッド２ａの中心とを正確に合致させることが可能となる
。If the position of the chip substrate 1a is finely adjusted so that the black circle is placed in the center of the annular reflected light, the center of the connection pad 1d of the micro semiconductor chip 1 and the center of the connection pad 2a of the connection substrate 2 will be aligned. It is possible to match accurately.
しかしながら、光吸収層１ｂに比べて接続パッド２ａの
直径が非常に大なる場合は、必然的に位置合わせマーク
３の内径も大きくなり、この内径と光吸収層１ｂの外径
との間に大きな差が生じる場合には、位置合わせが困難
になり、位置合わせ精度が低下する。However, if the diameter of the connection pad 2a becomes much larger than that of the light absorption layer 1b, the inner diameter of the alignment mark 3 will inevitably also become larger, and there will be a large gap between this inner diameter and the outer diameter of the light absorption layer 1b. If a difference occurs, alignment becomes difficult and alignment accuracy decreases.
このような場合に適用できる他の実施例について第２図
により説明する。Another embodiment applicable to such a case will be described with reference to FIG. 2.
この場合は位置合わせに光吸収層１１ｂを用いないで、
第２図（ａ）及び（ｂｌに示すように、接続パッド１１
ｄ゛の間の光吸収層１１ｂの一部を円形に除去し、この
位置に対応する接続基板１２上に位置合わせマーク１３
を金属を蒸着して形成する。In this case, without using the light absorption layer 11b for alignment,
As shown in FIGS. 2(a) and (bl), the connection pad 11
A part of the light absorption layer 11b between d' is removed in a circular shape, and an alignment mark 13 is placed on the connection board 12 corresponding to this position.
is formed by vapor depositing metal.
図示のようにチップ基板１１ａを透過する波長１．３μ
ｍの入射光１４を照射すると、チップ基板１１ａのみの
部分を透過した入射光１４は、接続基板１２上の金属を
蒸着して形成した位置合わせマーク１３で反射し、この
円形の反射光１５は図示のように反射する。As shown in the figure, the wavelength transmitted through the chip substrate 11a is 1.3μ.
When the incident light 14 of m is irradiated, the incident light 14 that has passed through only the chip substrate 11a is reflected by the alignment mark 13 formed by vapor-depositing metal on the connection board 12, and this circular reflected light 15 is Reflect as shown.
一方、光吸収層１１ｂ゛の部分に照射された入射光１４
はこの光吸収層１１ｂ゛で吸収されるので、第２図（Ｃ
）に示すような斜線で示すような黒地の中の円形の窓の
中の接続基板１２の表面からの反射光の中に、輝いてい
る位置合わせマーク１３を見ることができる。On the other hand, the incident light 14 irradiated onto the light absorption layer 11b'
is absorbed by this light absorption layer 11b', so as shown in Fig. 2 (C
) The shining alignment mark 13 can be seen in the reflected light from the surface of the connection board 12 in the circular window in the black background as shown by diagonal lines.
チップ基板１１ａの位置を微調整して、上記の窓の真中
に上記の輝いている位置合わせマーク１３がくるように
すると、微小半導体チップ１１の接続パッドｌｉｄの中
心と、接続基板１２の接続パッド１２ａの中心とを正確
に合致させることが可能となる。By finely adjusting the position of the chip substrate 11a so that the shining alignment mark 13 is placed in the center of the window, the center of the connection pad lid of the micro semiconductor chip 11 and the connection pad of the connection substrate 12 are aligned. It becomes possible to accurately match the center of 12a.
この場合は黒地の中の円形の窓の中の接続基板１２の表
面からの反射光の中に、輝いている位置合わせマーク１
３を位置合わせするので、コントラストが少々不足ぎみ
である。In this case, the alignment mark 1 is shining in the reflected light from the surface of the connection board 12 inside the circular window in the black background.
3, so the contrast is a little lacking.
なお、この点を改良するために、一実施例と他の実施例
の長所を組み合わせ、他の実施例で形成した位置合わせ
のための光吸収層１１ｂ゛の円形の除去部分の中央に、
一実施例で用いた光吸収層１ｂに相当するものを残し、
これに対応する環状の位置合わせマークを接続基板の表
面に形成すれば、一実施例と他の実施例の欠点を除去し
た位置合わせを行うことが可能となる。In order to improve this point, the advantages of one embodiment and the other embodiments are combined, and in the center of the circular removed portion of the light absorption layer 11b for alignment formed in the other embodiment,
Leaving what corresponds to the light absorption layer 1b used in one example,
By forming a corresponding annular positioning mark on the surface of the connection board, it becomes possible to perform positioning that eliminates the drawbacks of one embodiment and the other embodiments.
このように接続パッドの中心を合致させた微小半導体チ
ップ１接続基板２とを、接続パッドの各々の表面に形成
しおいた金錫合金を加熱溶融すると一体化し、第３図に
示すような状態に組み立てることが可能となる。The micro semiconductor chip 1 and the connection substrate 2 with the centers of the connection pads aligned in this way are integrated by heating and melting the gold-tin alloy formed on the surface of each connection pad, resulting in the state shown in Figure 3. It is possible to assemble the
以上の説明から明らかなように本発明によれば極めて簡
単な構造の位置合わせマークを接続基板上に形成するこ
とにより、微小半導体チップの接続バンドと、接続基板
の接続パッドと、を高精度で位置合わせすることが可能
となる利点があり、著しい品質向上の効果が期待でき工
業的には極めて有用なものである。As is clear from the above description, according to the present invention, by forming alignment marks with an extremely simple structure on the connection board, the connection band of the micro semiconductor chip and the connection pad of the connection board can be aligned with high precision. It has the advantage of being able to be aligned, and can be expected to significantly improve quality, making it extremely useful industrially.
第１図は本発明による一実施例を示す図、第２図は本発
明による他の実施例を示す図、第３図は本発明による一
実施例の微小半導体チツブと接続基板との組立状態を示
す側
断面図、
第４図は従来の半導体チップの位置合わせ方法を示す図
、である。
図において、
１．１１は微小半導体チップ、
ｌａ、 ｌｌａはチップ基板、
Ｉｂ、 ｌｌｂは光吸収層、
ｌｂ’ 、 Ｉｌｂ’は光吸収層、
ｌｃ、 ｌｌｃは透明層、
ｌｃ’、Ｉｌｃ’は透明層、
１ｄ、ｌｉｄは接続パッド、
１ｄ’ 、 ｌｉｄ’は接続パッド、
２．１２接続基板、
２ａ、１２ａは接続パッド、
３．１３は位置合わせマーク、
４．１４は入射光、
シー 二
八 へ
へ も１
区 ミ
け わ 需
キ ＩＫ 升臭 図
碍 う
く５０ 珪砧く 扉宇；
プＩＣＩＩ！ｌ 枢 ｇ ｒｍ −１ｄｏ
排
：Ｌ−ＩＪ
５二
０ ｍき
！
シー
電 重 さFIG. 1 is a diagram showing an embodiment according to the present invention, FIG. 2 is a diagram showing another embodiment according to the present invention, and FIG. 3 is an assembled state of a micro semiconductor chip and a connecting board according to an embodiment according to the present invention. FIG. 4 is a side sectional view showing a conventional semiconductor chip alignment method. In the figure, 1.11 is a micro semiconductor chip, la and lla are chip substrates, Ib and llb are light absorption layers, lb' and Ilb' are light absorption layers, lc and llc are transparent layers, lc' and Ilc' are transparent layer, 1d and lid are connection pads, 1d' and lid' are connection pads, 2.12 connection board, 2a and 12a are connection pads, 3.13 is alignment mark, 4.14 is incident light, to 1
Ward Mike Wa Demand Ki IK Masuo Diagram
碍 Uku 50 Keikinuku Toayu;
Pu ICII! l central g rm -1do
Exhaust: L-IJ 520 m
! Sea electric weight
Claims (1)
わせする方法であって、前記接続基板（２）上に位置合
わせマーク（３）を形成し、前記微小半導体チップ（１
）のチップ基板（１ａ）を透過する波長の入射光（４）
を、前記微小半導体チップ（１）の接続パッド（１ｄ）
を形成していない面の裏面から照射し、前記裏面より、
前記位置合わせマーク（３）による反射光（５）と、微
小半導体チップ（１）の光吸収層（１ｂ）の影像とを確
認し、位置合わせを行うことを特徴とする微小半導体チ
ップの位置合わせ方法。A method of aligning a micro semiconductor chip (1) and a connection board (2), comprising forming an alignment mark (3) on the connection board (2), and aligning the micro semiconductor chip (1).
) Incident light (4) with a wavelength that passes through the chip substrate (1a)
, the connection pad (1d) of the micro semiconductor chip (1)
Irradiate from the back side of the side where no
Alignment of a micro semiconductor chip, characterized in that alignment is performed by checking the reflected light (5) by the alignment mark (3) and the image of the light absorption layer (1b) of the micro semiconductor chip (1). Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32197587A JPH0642501B2 (en) | 1987-12-18 | 1987-12-18 | Positioning method for small semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32197587A JPH0642501B2 (en) | 1987-12-18 | 1987-12-18 | Positioning method for small semiconductor chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01162345A true JPH01162345A (en) | 1989-06-26 |
| JPH0642501B2 JPH0642501B2 (en) | 1994-06-01 |
Family
ID=18138519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32197587A Expired - Lifetime JPH0642501B2 (en) | 1987-12-18 | 1987-12-18 | Positioning method for small semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642501B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05198634A (en) * | 1992-01-20 | 1993-08-06 | Nec Corp | Test method for semiconductor device and test jig |
| JP2002039738A (en) * | 2000-05-18 | 2002-02-06 | Advantest Corp | Position shift detecting method and position determining method, and position shift detecting device and position determining device for probe |
| US7292519B2 (en) | 1999-08-19 | 2007-11-06 | Hitachi, Ltd. | Optical head with lasers and mirrors in a recess formed in a substrate |
-
1987
- 1987-12-18 JP JP32197587A patent/JPH0642501B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05198634A (en) * | 1992-01-20 | 1993-08-06 | Nec Corp | Test method for semiconductor device and test jig |
| US7292519B2 (en) | 1999-08-19 | 2007-11-06 | Hitachi, Ltd. | Optical head with lasers and mirrors in a recess formed in a substrate |
| JP2002039738A (en) * | 2000-05-18 | 2002-02-06 | Advantest Corp | Position shift detecting method and position determining method, and position shift detecting device and position determining device for probe |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0642501B2 (en) | 1994-06-01 |
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