JPH01143517A - Filter circuit - Google Patents

Filter circuit

Info

Publication number
JPH01143517A
JPH01143517A JP30223187A JP30223187A JPH01143517A JP H01143517 A JPH01143517 A JP H01143517A JP 30223187 A JP30223187 A JP 30223187A JP 30223187 A JP30223187 A JP 30223187A JP H01143517 A JPH01143517 A JP H01143517A
Authority
JP
Japan
Prior art keywords
filter
reception
filter circuit
clock
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30223187A
Other languages
Japanese (ja)
Inventor
Yukikazu Hirose
廣瀬 之和
Masatoshi Yago
家合 政敏
Junji Nakatsuka
淳二 中塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP30223187A priority Critical patent/JPH01143517A/en
Publication of JPH01143517A publication Critical patent/JPH01143517A/en
Pending legal-status Critical Current

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  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To obtain a filter circuit in response to the operation in the multi- mode without increase in the number of circuits by providing an oscillator varying a clock frequency depending on various transmission/reception modes and supplying its output to a switched capacitor filter circuit. CONSTITUTION:A transmission BPF 61, a reception LPF 62 and a reception HPF 63 constitute a switched capacitor circuit 6, which is operated by clocks of frequencies f1-f3 from a clock oscillator 9. The cut-off frequency fCH of the reception HPF 63 is proportional to the clock frequency f3 from the oscillator 9. Moreover, the cut-off frequency fCL of the reception LPF 62 is proportional to the clock frequency f2 from the oscillator 9. Thus, the clock frequencies f2, f3 are varied so as to make the cut-off frequencies fCH, fCL of each filter variable thereby setting optionally the bands fCH-fCL of the filter circuit. Thus, the filter circuit in response to the various transmission/reception modes is easily obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、データ伝送システムで使用される変復調装置
(以下、モデムと称す)に適用のフィルタ回路に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a filter circuit applied to a modem (hereinafter referred to as a modem) used in a data transmission system.

従来の技術 従来の一般的なモデムに内蔵のフィルタ回路について、
第4図に示されたブロック図を参照して説明する。モデ
ム200は、データ端末装置からのディジタル信号をア
ナログ信号に変換して、2線−4線変換部300を通し
て、電話回線側へ送出する。逆に、相手から電話回線を
通して受信したアナログ信号をディジタル信号に変換し
てデータ端末装置へ送出する。モデム200は、その内
部構成が変調器201、変調器201のディジタル信号
をアナログ信号に変換するD/A変換器202、信号経
路を切り換えるスイッチ203゜204、受信したアナ
ログ信号をディジタル信号に変換するA/D変換器20
5、受信した信号を元のデータに戻す復調器206、送
受信モードに応じてスイッチ203,204を切り換え
るコントローラ210、基準クロック発振器220、送
信/受信のアナログ信号のための低群フィルタ230、
高群フィルタ240より成り立っている。
Conventional technology Regarding the filter circuit built into conventional general modems,
This will be explained with reference to the block diagram shown in FIG. The modem 200 converts the digital signal from the data terminal device into an analog signal and sends it to the telephone line side through the 2-wire to 4-wire converter 300. Conversely, the analog signal received from the other party through the telephone line is converted into a digital signal and sent to the data terminal device. The modem 200 has an internal configuration including a modulator 201, a D/A converter 202 that converts the digital signal of the modulator 201 into an analog signal, switches 203 and 204 that change the signal path, and converts the received analog signal into a digital signal. A/D converter 20
5. A demodulator 206 that returns the received signal to the original data, a controller 210 that switches the switches 203 and 204 according to the transmission/reception mode, a reference clock oscillator 220, a low group filter 230 for transmitting/receiving analog signals,
It consists of a high group filter 240.

2線式全二重モデムにおいて、搬送波周波数feは例え
ば、1200BPS全二重モデムを例にとると、 低群側    fc=1200Hz 高群側    fc=2400Hz である。
In a two-wire full duplex modem, for example, taking a 1200 BPS full duplex modem as an example, the carrier frequencies fe are as follows: fc = 1200 Hz on the low group side fc = 2400 Hz on the high group side.

モデム200が起呼側である場合、コントローラ210
は、送信フィルタとして低群フィルタ230、受信フィ
ルタとして高群フィルタ240となるようにスイッチ2
03,204を設定する。つまり、スイッチ203は、
D/A変換器202の出力を低群フィルタ230へ入力
し、2線−4線変換部300の出力を高群フィルタ24
0へ入力する。低群フィルタ230は、D/A変換器2
02からのアナログ信号に含まれる高周波成分を除去す
る。高群フィルタ240は、電話回線上のノイズ及び送
信した信号の回り込み成分を除去し、相手からの所望の
信号のみを取り出す。低群フィルタ230.高群フィル
タ240は、スイッチトキャパシタで構成されており、
クロック発振器220からの一定周波数のクロックによ
り動作している。モデム200が応答側である場合は、
コントローラ210は、送信フィルタとして高群フィル
°り240.受信フィルタとして低群フィルタ230と
なるようにスイッチ203゜204を設定する。つまり
、スイッチ203は、D/A変換器202の出力を高群
フィルタ240へ入力し、2線−4線変換部3ooの出
力を低群フィルタ230へ入力するよう設定し、スイッ
チ204は、高群フィルタ240の出力を2線−4線変
換部300へ入力し、低群フィルタ230の出力をA/
D変換器205へ入力するように設定される。
If modem 200 is the calling party, controller 210
The switch 2 is set so that the low group filter 230 is used as the transmitting filter and the high group filter 240 is used as the receiving filter.
Set 03,204. In other words, the switch 203 is
The output of the D/A converter 202 is input to the low group filter 230, and the output of the 2-wire to 4-wire converter 300 is input to the high group filter 24.
Enter 0. The low group filter 230 is the D/A converter 2
Remove high frequency components contained in the analog signal from 02. The high group filter 240 removes noise on the telephone line and wraparound components of the transmitted signal, and extracts only the desired signal from the other party. Low group filter 230. The high group filter 240 is composed of a switched capacitor,
It operates using a constant frequency clock from a clock oscillator 220. If modem 200 is the answering side,
The controller 210 includes a high group filter 240 . as a transmit filter. The switches 203 and 204 are set so that the low group filter 230 is used as the reception filter. That is, the switch 203 is set to input the output of the D/A converter 202 to the high group filter 240, and the output of the 2-wire to 4-wire converter 3oo is input to the low group filter 230. The output of the group filter 240 is input to the 2-wire to 4-wire converter 300, and the output of the low group filter 230 is input to the A/4 line converter 300.
It is set to be input to the D converter 205.

発明が解決しようとする問題点 しかしながら、上記の従来の構成では、低群フィルタ2
30.高群フィルタ240は、クロック発振器220か
らの一定周波数のクロックで動作しているので、フィル
タ回路の帯域は一定のままである。従って、種々の送受
信モードに応じたフィルタ回路の帯域を必要とするモデ
ムでは、種々のフィルタ回路を備えねばならないという
問題点を有していた。
Problems to be Solved by the Invention However, in the above conventional configuration, the low group filter 2
30. Since the high group filter 240 operates with a constant frequency clock from the clock oscillator 220, the band of the filter circuit remains constant. Therefore, a modem that requires filter circuit bands corresponding to various transmission/reception modes has the problem of having to be equipped with various filter circuits.

本発明は、上記従来の問題点を解決するもので、回路数
の増加なしに多モード応動のできるフィルタ回路を提供
することを目的とする。
The present invention solves the above-mentioned conventional problems, and aims to provide a filter circuit that can respond to multiple modes without increasing the number of circuits.

問題点を解決するための手段 この目的のために、本発明のフィルタ回路は、種々の送
受信モードにより、クロック周波数を可変する発振器を
有し、スイッチトキャパシタ回路へ供給する構成を有し
ている。
Means for Solving the Problems For this purpose, the filter circuit of the present invention has an oscillator whose clock frequency is varied according to various transmission/reception modes, and is configured to supply the oscillator to a switched capacitor circuit.

作用 この構成によって、スイッチトキャパシタフィルタ回路
のクロック周波数を可変にし、スイッチトキャパシタフ
ィルタ回路の帯域を可変にでき、種々の送受信モードに
応じたフィルタ回路をそれぞれ構成する必要がなく、フ
ィルタ回路の削減が実現できる。
Effect: With this configuration, the clock frequency of the switched capacitor filter circuit can be made variable, and the band of the switched capacitor filter circuit can be made variable. There is no need to configure filter circuits for each of the various transmission and reception modes, and the number of filter circuits can be reduced. can.

実施例 本発明の実施例について以下に説明する。Example Examples of the present invention will be described below.

第1図は、本発明の実施例におけるフィルタ回路を含ん
だモデムのブロック図を示すものである。このモデム1
は、内部構成として、変調器4、D/A変換器5.フィ
ルタ回路6.A/D変換器7.復調器8.クロック発振
器9.コントローラ10より成り、クロック発振器9に
は、その分周比を変えるための送受信モード設定端子3
をそなえている。フィルタ回路6は、送信バンドパスフ
ィルタ61.受信ローパスフィルタ62.受信バイパス
フィルタ63より構成されている。
FIG. 1 shows a block diagram of a modem including a filter circuit according to an embodiment of the present invention. This modem 1
The internal configuration includes a modulator 4, a D/A converter 5. Filter circuit 6. A/D converter7. Demodulator 8. Clock oscillator9. It consists of a controller 10, and a clock oscillator 9 has a transmission/reception mode setting terminal 3 for changing its frequency division ratio.
It is equipped with The filter circuit 6 includes a transmission bandpass filter 61 . Reception low-pass filter 62. It is composed of a reception bypass filter 63.

このように構成された、モデムのフィルタ回路について
、以下その動作を説明する。変調器4゜D/A変換器5
.A/D変換器7.復調器8は従来例の動作と同じもの
である。
The operation of the modem filter circuit configured in this manner will be described below. Modulator 4゜D/A converter 5
.. A/D converter7. The demodulator 8 operates in the same manner as in the conventional example.

送信バンドパスフィルタ61.受信ローパスフィルタ6
2.受信バイパスフィルタ63は、スイッチトキャパシ
タで構成されており、クロック発振器9からの周波数f
l、f2.f3のクロックにより動作している。送信バ
ンドパスフィルタ61のゲイン特性を第3図に示す。受
信ローパスフィルタ62.受信バイパスフィルタ63の
ゲイン特性を第2図に示す。受信バイパスフィルタ63
のカットオフ周波数fC)Iは、クロック発振器9から
のクロック周波数f3に比例する。
Transmission bandpass filter 61. Reception low pass filter 6
2. The reception bypass filter 63 is composed of a switched capacitor, and receives the frequency f from the clock oscillator 9.
l, f2. It is operated by the f3 clock. FIG. 3 shows the gain characteristics of the transmission bandpass filter 61. Reception low-pass filter 62. FIG. 2 shows the gain characteristics of the reception bypass filter 63. Reception bypass filter 63
The cutoff frequency fC)I of is proportional to the clock frequency f3 from the clock oscillator 9.

fcH=af3     ただし 0<α<1また、受
信ローパスフィルタのカットオフ周波数fcLはクロッ
ク発振器9からのクロック周波数f2に比例する。
fcH=af3 where 0<α<1 Furthermore, the cutoff frequency fcL of the receiving low-pass filter is proportional to the clock frequency f2 from the clock oscillator 9.

fCL=βf2    ただし oくβ〈1クロック周
波数f2+ f3を可変にすることにより、フィルタの
カットオフ周波数fcH* fCLも可変になり、フィ
ルタ回路の帯域fc、−fcLが、任意に設定できる。
fCL=βf2 However, β<1 By making the clock frequency f2+f3 variable, the cutoff frequency fcH*fCL of the filter also becomes variable, and the bands fc and -fcL of the filter circuit can be set arbitrarily.

下の第1表に、ユーザ規格1. IF、 IIIごとに
、モード設定端子3の各A、B、Cの値と、モデムの送
受信モードと、フィルタ回路の帯域を示す。
Table 1 below shows user specifications 1. For each IF and III, the values of A, B, and C of the mode setting terminal 3, the transmission/reception mode of the modem, and the band of the filter circuit are shown.

発明の効果 以上述べてきたように、本発明のスイッチトキャパシタ
フィルタ回路によれば、モード設定端子で設定されるモ
ードに応じて、クロック発振器の分周比を可変にしたこ
とにより、受信ローパスフィルタおよび、受信バイパス
フィルタのクロック周波数を可変にでき、フィルタ回路
の帯域を任意に設定できる。したがって、これにより、
種々の送受信モードに応じたフィルタ回路を容易に実現
できる。
Effects of the Invention As described above, according to the switched capacitor filter circuit of the present invention, the division ratio of the clock oscillator is made variable according to the mode set by the mode setting terminal, so that the receiving low-pass filter and , the clock frequency of the reception bypass filter can be made variable, and the band of the filter circuit can be set arbitrarily. Therefore, this:
Filter circuits suitable for various transmission/reception modes can be easily realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例適用モデムのブロック図、第
2図は同モデム中の受信フィルタのゲイン特性図、第3
図は同モデム中の送信フィルタのゲイン特性図、第4図
は従来のモデムのブロック図である。 1・・・・・・モデム、3・・・・・・モード設定端子
、9・・・・・・クロック発振器、61・・・・・・送
信バンドパスフィルタ、62・・・・・・受信ローパス
フィルタ、63・・・・・・受信バイパスフィルタ。 代理人の氏名 弁理士 中尾敏男 ほか1名へ    
      ′トマ・)で 第3図
FIG. 1 is a block diagram of a modem to which an embodiment of the present invention is applied, FIG. 2 is a gain characteristic diagram of a receiving filter in the modem, and FIG.
The figure is a gain characteristic diagram of a transmission filter in the same modem, and FIG. 4 is a block diagram of a conventional modem. 1...Modem, 3...Mode setting terminal, 9...Clock oscillator, 61...Transmission band pass filter, 62...Reception Low-pass filter, 63... Reception bypass filter. Name of agent: Patent attorney Toshio Nakao and one other person
Figure 3

Claims (1)

【特許請求の範囲】[Claims] スイッチトキャパシタ回路で構成されたフィルタ回路の
帯域を動作モードに応じて、そのクロック周波数を可変
にするクロック発振器を備えたことを特徴とするフィル
タ回路。
1. A filter circuit comprising a clock oscillator that changes the clock frequency of the filter circuit configured with a switched capacitor circuit according to its operating mode.
JP30223187A 1987-11-30 1987-11-30 Filter circuit Pending JPH01143517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30223187A JPH01143517A (en) 1987-11-30 1987-11-30 Filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30223187A JPH01143517A (en) 1987-11-30 1987-11-30 Filter circuit

Publications (1)

Publication Number Publication Date
JPH01143517A true JPH01143517A (en) 1989-06-06

Family

ID=17906528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30223187A Pending JPH01143517A (en) 1987-11-30 1987-11-30 Filter circuit

Country Status (1)

Country Link
JP (1) JPH01143517A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736896A (en) * 1994-10-21 1998-04-07 Nippondenso Co., Ltd. Signal processing circuit
US10009039B1 (en) 2017-08-18 2018-06-26 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
US10069483B1 (en) * 2017-08-18 2018-09-04 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
US10141946B1 (en) 2017-08-18 2018-11-27 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
CN111226395A (en) * 2017-08-18 2020-06-02 思睿逻辑国际半导体有限公司 Multi-path analog system with multi-mode high-pass filter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767312A (en) * 1980-10-14 1982-04-23 Takayoshi Hirata Band pass filter following frequency
JPS59175209A (en) * 1983-03-25 1984-10-04 Hitachi Ltd Signal transmitting circuit
JPS62209913A (en) * 1986-03-10 1987-09-16 Hitachi Ltd Switched capacitor filter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767312A (en) * 1980-10-14 1982-04-23 Takayoshi Hirata Band pass filter following frequency
JPS59175209A (en) * 1983-03-25 1984-10-04 Hitachi Ltd Signal transmitting circuit
JPS62209913A (en) * 1986-03-10 1987-09-16 Hitachi Ltd Switched capacitor filter

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736896A (en) * 1994-10-21 1998-04-07 Nippondenso Co., Ltd. Signal processing circuit
US10009039B1 (en) 2017-08-18 2018-06-26 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
US10069483B1 (en) * 2017-08-18 2018-09-04 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
US10141946B1 (en) 2017-08-18 2018-11-27 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
US10566989B2 (en) 2017-08-18 2020-02-18 Cirrus Logic, Inc. Multi-path analog system with multi-mode high-pass filter
CN111226395A (en) * 2017-08-18 2020-06-02 思睿逻辑国际半导体有限公司 Multi-path analog system with multi-mode high-pass filter
CN111226395B (en) * 2017-08-18 2021-07-06 思睿逻辑国际半导体有限公司 Multi-path analog system with multi-mode high-pass filter

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