JPH01137683U - - Google Patents

Info

Publication number
JPH01137683U
JPH01137683U JP3438688U JP3438688U JPH01137683U JP H01137683 U JPH01137683 U JP H01137683U JP 3438688 U JP3438688 U JP 3438688U JP 3438688 U JP3438688 U JP 3438688U JP H01137683 U JPH01137683 U JP H01137683U
Authority
JP
Japan
Prior art keywords
gate pulse
burst
burst gate
pulse
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3438688U
Other languages
Japanese (ja)
Other versions
JPH0543587Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3438688U priority Critical patent/JPH0543587Y2/ja
Publication of JPH01137683U publication Critical patent/JPH01137683U/ja
Application granted granted Critical
Publication of JPH0543587Y2 publication Critical patent/JPH0543587Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案のバーストゲートパルス発生
回路の実施例を示すブロツク図、第2図ないし第
5図は第1図に示したバーストゲートパルス発生
回路の動作を示す図、第6図は従来のバーストゲ
ートパルス発生回路を示すブロツク図、第7図は
第6図に示したバーストゲートパルス発生回路の
動作を示す図である。 12,14…単安定マルチバイブレータ(パル
ス発生手段)、16…位相制御回路(位相制御手
段)。
FIG. 1 is a block diagram showing an embodiment of the burst gate pulse generation circuit of this invention, FIGS. 2 to 5 are diagrams showing the operation of the burst gate pulse generation circuit shown in FIG. 1, and FIG. 6 is a conventional circuit. 7 is a block diagram showing the burst gate pulse generating circuit shown in FIG. 6. FIG. 7 is a diagram showing the operation of the burst gate pulse generating circuit shown in FIG. 12, 14... Monostable multivibrator (pulse generation means), 16... Phase control circuit (phase control means).

Claims (1)

【実用新案登録請求の範囲】 水平同期信号を基準にしてバーストゲートパル
スを発生するパルス発生手段と、 一定レベル以上のバースト信号を有するクロマ
信号の全波整流により得られるバーストパルスと
前記バーストゲートパルスとの位相のずれに応じ
て前記バーストゲートパルスの位相を制御する位
相制御手段とを備えたバーストゲートパルス発生
回路。
[Claims for Utility Model Registration] Pulse generating means for generating a burst gate pulse based on a horizontal synchronization signal, a burst pulse obtained by full-wave rectification of a chroma signal having a burst signal of a certain level or higher, and the burst gate pulse. and a phase control means for controlling the phase of the burst gate pulse according to a phase shift between the burst gate pulse and the burst gate pulse.
JP3438688U 1988-03-15 1988-03-15 Expired - Lifetime JPH0543587Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3438688U JPH0543587Y2 (en) 1988-03-15 1988-03-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3438688U JPH0543587Y2 (en) 1988-03-15 1988-03-15

Publications (2)

Publication Number Publication Date
JPH01137683U true JPH01137683U (en) 1989-09-20
JPH0543587Y2 JPH0543587Y2 (en) 1993-11-02

Family

ID=31261097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3438688U Expired - Lifetime JPH0543587Y2 (en) 1988-03-15 1988-03-15

Country Status (1)

Country Link
JP (1) JPH0543587Y2 (en)

Also Published As

Publication number Publication date
JPH0543587Y2 (en) 1993-11-02

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