JPH01135080A - Superconducting transistor - Google Patents
Superconducting transistorInfo
- Publication number
- JPH01135080A JPH01135080A JP62292027A JP29202787A JPH01135080A JP H01135080 A JPH01135080 A JP H01135080A JP 62292027 A JP62292027 A JP 62292027A JP 29202787 A JP29202787 A JP 29202787A JP H01135080 A JPH01135080 A JP H01135080A
- Authority
- JP
- Japan
- Prior art keywords
- superconductor
- superconducting
- protective film
- control electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002887 superconductor Substances 0.000 claims abstract description 47
- 230000001681 protective effect Effects 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 7
- -1 and Si Substances 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 229910000846 In alloy Inorganic materials 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、超電導体と半導体を組合せて使用する超電導
デバイスに係り、特に高速動作と高集積化に好適な電界
効果型の超電導トランジスタに係る。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a superconducting device using a combination of a superconductor and a semiconductor, and particularly to a field-effect superconducting transistor suitable for high-speed operation and high integration. .
（従来の技術）
従来、集積化に好適な電界効果型超電導トランジスタに
ついては特開昭６１−１７１１８０号公報に開示されて
いる。(Prior Art) Conventionally, a field-effect superconducting transistor suitable for integration has been disclosed in Japanese Patent Application Laid-Open No. 171180/1983.
（発明が解決しようとする問題点〕
上記従来技術においては、制御電極の構造及び材料につ
いては配慮がなされておらず、従ってこれら従来技術を
用いた場合においては、超電導の制御電極を再現性良く
形成することは困難であり。(Problems to be solved by the invention) In the above-mentioned conventional techniques, no consideration has been given to the structure and material of the control electrode. It is difficult to form.
また半導体のチャネル部分に接した２つの超電導電極と
制御電極との距離を再現性良く形成することも困難であ
った。このため従来技術においては集積回路中に含まれ
る複数の超電導トランジスタの特性ばらつきを小さくし
、安定に動作する超電導トランジスタ集積回路を得るこ
とが困望であった。また従来技術における超電導トラン
ジスタにおいては、制御電極を、１層の金属あるいは半
導体等の導体で形成していたためにただ１つの入力信号
のみを使用しており、機能が限られていた。It was also difficult to form the distance between the two superconducting electrodes in contact with the channel portion of the semiconductor and the control electrode with good reproducibility. Therefore, in the prior art, it has been difficult to reduce the variation in characteristics of a plurality of superconducting transistors included in an integrated circuit and to obtain a superconducting transistor integrated circuit that operates stably. In addition, in conventional superconducting transistors, the control electrode is formed of a single layer of conductor such as metal or semiconductor, so only one input signal is used, and the function is limited.
本発明の目的は、上記従来技術の持つ問題点を解決し、
製造が容易で特性のばらつきが小さいために集積化に好
適であって、なおかつ２つ以上の電圧信号による入力を
可能とし、１個のデバイスで論理機能を実現できるよう
な超電導トランジスタの構造と材料とを提供することに
ある。The purpose of the present invention is to solve the problems of the above-mentioned prior art,
The structure and materials of a superconducting transistor that is easy to manufacture and has small variations in characteristics, making it suitable for integration, and that also allows input of two or more voltage signals and realizes logic functions in a single device. The aim is to provide the following.
［問題点を解決す゛るための手段〕
上記目的は、制御電極として半導体表面に形成した絶縁
膜、あるいは半導体の上に設けた第１の超電導体と、該
第１の超電導体上に設けた保護膜及び第２の超電導体と
を少なくとも含んで構成するとともに、半導体中の電流
が流れる向きに平行な方向において、前記の第１の超電
導体の幅が前記の保護膜の幅に比べて小さくすることに
より、達成される。この場合、最良の実施形態として、
前記第１の超電導体の材料にＮｂ、あるいはＮｂＮ等の
Ｎｂ化合物、Ｍｏ、あるいはＭｏＮ等のＭＯ化合物、さ
らには酸化物超電導体を用い、さらに前記第１の超電導
体と保護膜との厚さの差の２分の１は、注入したイオン
の注入方向に対して垂直な方向のイオンの飛程（イオン
レンジ）あるいは横方向の拡散長に比べて小さな値に選
ぶことが望ましい。[Means for solving the problem] The above purpose is to provide an insulating film formed on the surface of a semiconductor as a control electrode, or a first superconductor provided on the semiconductor, and a protection provided on the first superconductor. The first superconductor is configured to include at least a film and a second superconductor, and the width of the first superconductor is smaller than the width of the protective film in a direction parallel to the direction in which current flows in the semiconductor. This is achieved by: In this case, as a best embodiment,
Nb or an Nb compound such as NbN, Mo or an MO compound such as MoN, or an oxide superconductor is used as the material of the first superconductor, and the thickness of the first superconductor and the protective film is It is desirable that one-half of the difference be selected to be a smaller value than the ion range of the implanted ions in the direction perpendicular to the direction of implantation or the diffusion length in the lateral direction.
本発明においては、超電導体上に保護膜を設けているた
め、半導体への不純物の拡散あるいはイオン注入を行っ
た場合であっても、これら不純物やイオンが超電導体に
達して超電導特性が劣化することかなく、従って超電導
の制御電極を実現することが可能となる。また超電導体
の幅が前記の保護膜よりも小さいので、注入したイオン
が超電導体中に散乱されることがない、また、このよう
な制御電極上に超電導体を蒸着することによって、ソー
ス及びドレインの２つの超電導電極を、半導体中にイオ
ン注入法あるいは拡散法によって形成した半導体中の高
不純物濃度部分と空間的な位置の精度を高くして形成す
ることができる。In the present invention, since a protective film is provided on the superconductor, even if impurities are diffused into the semiconductor or ions are implanted, these impurities and ions will reach the superconductor and deteriorate the superconducting properties. Therefore, it becomes possible to realize a superconducting control electrode without any problems. In addition, since the width of the superconductor is smaller than the above-mentioned protective film, the implanted ions are not scattered into the superconductor, and by depositing the superconductor on such a control electrode, the source and drain The two superconducting electrodes can be formed with high accuracy in spatial position with a high impurity concentration portion in the semiconductor formed by ion implantation or diffusion.
さらに、制御電極に超電導体と保護膜とを少なくとも使
用し、しかも超電導体の幅を保護膜の幅よりも小さくシ
、その差の半分が、注入したイオンの注入方向に対して
垂直な方向のイオンレンジあるいは横方向の拡散長に比
べて小さな値に選ばれていれば、半導体中の高不純物濃
度部分は制御電極の超電導体部分の直下にある半導体中
にまで延在するので、低温においても制御電極端部にお
いて、電子又は正孔等のキャリア濃度が小さくなり、超
電導電流が小さくなってしまうという問題が生じること
もない、また従来法にくらべて、微細な形状を有する超
電導電極や制御電極の形成が、−回の電子線描画等に技
術によるパターンの形成によって実現できるので、工程
が簡略化され、製造の費用を軽減するとともに製造上の
歩留りを高くできる。このため高集積度の回路を容易に
実現できる。Furthermore, at least a superconductor and a protective film are used in the control electrode, and the width of the superconductor is smaller than the width of the protective film, so that half of the difference is in the direction perpendicular to the direction of implanted ions. If the value is chosen to be small compared to the ion range or lateral diffusion length, the high impurity concentration part in the semiconductor will extend into the semiconductor directly below the superconductor part of the control electrode, so even at low temperatures. At the end of the control electrode, the concentration of carriers such as electrons or holes becomes small, which eliminates the problem of a small superconducting current, and compared to conventional methods, the superconducting electrode and control electrode have a finer shape. can be realized by forming a pattern using techniques such as electron beam lithography, which simplifies the process, reduces manufacturing costs, and increases manufacturing yield. Therefore, a highly integrated circuit can be easily realized.
さらに本発明によれば、１つの超電導トランジスタが複
数の入力用電極から構成された制御電極を持つために、
２つ以上の電圧入力信号を同時に超電導トランジスタに
印加し、超電導トランジスタを制御することができる。Furthermore, according to the present invention, since one superconducting transistor has a control electrode composed of a plurality of input electrodes,
Two or more voltage input signals can be simultaneously applied to a superconducting transistor to control the superconducting transistor.
具体的には制御電極を構成している第１の超電導体の電
位が一定電位であれば、第２の超電導体への入力電圧が
どんな値であろうと、出力信号は第１の超電導体の電位
によって決まる。一方、第１の超電導体の電位が電気的
にフローティングである場合には、出力信号は第２の超
電導体の電位によって決まる。従ってアンドあるいはオ
アといった論理機能を実現できるので、回路を小型化し
、集積度を高めることができる。Specifically, if the potential of the first superconductor constituting the control electrode is a constant potential, no matter what the input voltage to the second superconductor is, the output signal will be the same as that of the first superconductor. Determined by electric potential. On the other hand, if the potential of the first superconductor is electrically floating, the output signal is determined by the potential of the second superconductor. Therefore, logical functions such as AND or OR can be realized, so the circuit can be miniaturized and the degree of integration can be increased.
また、超電導体の材料として、超電導コヒーレンス長さ
が５０ｎｍあるいはそれ以下の材料を使用することによ
って、０．１μｍ以下の幅あるいは厚さを有する制御電
極の超電導状態での使用が可能となる。このため、具体
的にはＮｂ、Ｍｏ、あるいはこれらの化合物、酸化物超
電導体を用いることにより本発明の目的を達成すること
ができるのである。Furthermore, by using a material with a superconducting coherence length of 50 nm or less as the superconductor material, it becomes possible to use a control electrode having a width or thickness of 0.1 μm or less in a superconducting state. Therefore, specifically, the object of the present invention can be achieved by using Nb, Mo, a compound thereof, or an oxide superconductor.
以下、本発明を実施例を用いて詳細に説明する。 Hereinafter, the present invention will be explained in detail using examples.
第１図を用いて本発明の第１の実施例を説明する。（１
００）方位のｐ型Ｓｉ単結晶より成る基板１の表面を純
酸素中で熱酸化して厚さ約３０ｎｍの５ｉ０２より成る
絶縁膜２を形成する。A first embodiment of the present invention will be described using FIG. (1
The surface of a substrate 1 made of a p-type Si single crystal with a 00) orientation is thermally oxidized in pure oxygen to form an insulating film 2 made of 5i02 with a thickness of about 30 nm.
続いてマグネトロンスパッタリング法を用いて厚さ約１
１００ｎのＮｂＮより成る薄膜を形成する。Then, using magnetron sputtering method, the thickness of about 1
A thin film of 100n of NbN is formed.
これは第１の超電導体３に相当する０次に電子線レジス
トと電子線露光を用いて前記レジスト上に幅約０．１μ
ｍの開口を設け、このうえに電子ビーム蒸着によりＳｉ
を蒸着し、次にレジストを除去する。残った厚さ約２０
０ｎｍのＳｉより成る保護膜４をマスクとしてＮｂＮよ
り成る第１の超電導体３を加工する。加工にはＣＦ４ガ
スと５ＶｏＱ％の０２を用いガス有１０Ｐａの条件の反
応性イオンエツチングを用いる。この際には酸素を含ん
でいるため絶縁膜２もエツチングされる。This is done using a zero-order electron beam resist corresponding to the first superconductor 3 and electron beam exposure to form a layer with a width of about 0.1 μm on the resist.
m opening is provided, and Si is deposited on top by electron beam evaporation.
is deposited and then the resist is removed. The remaining thickness is about 20
A first superconductor 3 made of NbN is processed using a protective film 4 made of Si with a thickness of 0 nm as a mask. For processing, reactive ion etching is performed using CF4 gas and 5 VoQ% 02 under gas conditions of 10 Pa. At this time, the insulating film 2 is also etched because it contains oxygen.
次にＡｓイオンを加速電圧３０ＫｅＶでｌ Ｘ １０
ｉｌ！ｃｍ−”のドーズ量で注入したのち、９００℃で
２０分の真空中での加熱を施し高不純物濃度部５を形成
する。最後にＮｂ又はＰｂ−５ｖｔ％Ｉｎ合金を蒸着し
、一対の超電導電極６と第２の超電導体７とを形成し、
第１図に示す構造の超電導トランジスタを得る。Next, As ions were accelerated at an acceleration voltage of 30 KeV to
Il! After implantation at a dose of 1.5 cm-", the high impurity concentration region 5 is formed by heating at 900° C. for 20 minutes in a vacuum. Finally, Nb or Pb-5vt%In alloy is vapor-deposited to form a pair of superconducting forming an electrode 6 and a second superconductor 7;
A superconducting transistor having the structure shown in FIG. 1 is obtained.
第２図を用いて本発明の第２の実施例を説明する。（１
００）方位のｐ型Ｓｉ単結晶より成る基板１の表面を純
酸素中で熱酸化して厚さ約３０ｎｍの５ｉ０２より成る
絶縁膜２を形成する。A second embodiment of the present invention will be described using FIG. (1
The surface of a substrate 1 made of a p-type Si single crystal with a 00) orientation is thermally oxidized in pure oxygen to form an insulating film 2 made of 5i02 with a thickness of about 30 nm.
続いてマグネトロンスパッタリング法を用いて厚さ約１
１００ｎのＮｂＮより成る薄膜を形成する。Then, using magnetron sputtering method, the thickness of about 1
A thin film of 100n of NbN is formed.
これは第１の超電導体３に相当する０次に電子線レジス
トと電子線露光を用いて前記レジスト上に幅約０．１μ
ｍの開口を設け、このうえに電子ビーム蒸着によりＳｉ
を蒸着し、次にレジストを除去する。残った厚さ約２０
０ｎｍのＳｔより成る保護膜４をマスクとしてＮｂＮよ
り成る第１の超電導体３を加工する。加工にはＣＦ４ガ
スを用いガス圧力ＩＰａの条件の反応性イオンエツチン
グを用いる。この際には保護膜４の直下の絶縁膜２はエ
ツチングされずに残る。次にＡｓイオンを加速電圧３０
ＫｅＶでＩ Ｘ １０ ”ｃ■−”のドーズ量で注入し
たのち、９００℃で２０分の真空中での加熱を施し高不
純物濃度部５を形成する。最後にＮｂ又はＰｂ−５ｗｔ
％Ｉｎ合金を蒸着し、第２図に示す構造の超電導トラン
ジスタを得る。This is done using a zero-order electron beam resist corresponding to the first superconductor 3 and electron beam exposure to form a layer with a width of about 0.1 μm on the resist.
m opening is provided, and Si is deposited on top by electron beam evaporation.
is deposited and then the resist is removed. The remaining thickness is about 20
A first superconductor 3 made of NbN is processed using a protective film 4 made of 0 nm of St as a mask. The processing uses reactive ion etching using CF4 gas at a gas pressure of IPa. At this time, the insulating film 2 directly under the protective film 4 remains without being etched. Next, As ions are accelerated at a voltage of 30
After implanting with KeV at a dose of I x 10 "c -", heating is performed in a vacuum at 900° C. for 20 minutes to form a high impurity concentration region 5 . Finally, Nb or Pb-5wt
%In alloy is deposited to obtain a superconducting transistor having the structure shown in FIG.
次に第３図を用いて本発明の第３の実施例を説明する。Next, a third embodiment of the present invention will be described using FIG.
作製方法は第２の実施例と同様で良いが超電導体３をエ
ツチングによって加工するときのガス圧力を２０Ｐａ以
上に選ぶことにより、図に示した形状の制御電極を得る
ことができる。The manufacturing method may be the same as in the second embodiment, but by selecting a gas pressure of 20 Pa or more when etching the superconductor 3, a control electrode having the shape shown in the figure can be obtained.
次にＡｓイオンを加速電圧３０ＫｅＶでｌ Ｘ １０
”ｃ＋ｓ−”のドーズ量で注入シタノチ、９００℃で２
０分の真空中での加熱を施し高不純物濃度部５を形成す
る。最後にＮｂ又はｐｂ−５ｖｔ％Ｉｎ合金を蒸着し、
第３図に示す構造の超電導トランジスタを得る。Next, As ions were accelerated at an acceleration voltage of 30 KeV to
Implantation at a dose of "c+s-" at 900℃
The high impurity concentration portion 5 is formed by heating in a vacuum for 0 minutes. Finally, Nb or pb-5vt%In alloy is deposited,
A superconducting transistor having the structure shown in FIG. 3 is obtained.
次に第４図を用いて本発明の第４の実施例を説明する。Next, a fourth embodiment of the present invention will be described using FIG. 4.
ここでは製造方法は第２の実施例と同様で良いが、基板
１中の高不純物濃度部５の一部分をエツチングによって
除いたのち、最後にＮｂ又はＰｂ−５ｖｔ％Ｉｎ合金を
蒸着し、第４図に示す構造の超電導トランジスタを得る
。Here, the manufacturing method may be the same as that of the second embodiment, but after removing a part of the high impurity concentration area 5 in the substrate 1 by etching, Nb or Pb-5vt%In alloy is finally deposited, and the fourth A superconducting transistor having the structure shown in the figure is obtained.
以上の実施例においては基板１にｐ型のＳｉを用いたが
これに限られるものではなく、ｎ型のＳ ｔｏ ＧａＡ
ｓ、ＩｎＡｓ、ＩｎＳｂ、ＧａＳｂ等を用いても良いこ
とは言うまでもない、また超電導体の材料としてＮｂＮ
に換えてＮｂ、ＭｏＮ、等の材料や酸化物、化合物の超
電導材料を用いても良いことは言うまでもない、また保
護膜の材料としてＳｉに換えてＳｉＯ２，Ｓｉ３Ｎ、、
ＭｇＯ。In the above embodiments, p-type Si is used for the substrate 1, but the substrate 1 is not limited to this, and n-type S to GaA is used.
It goes without saying that NbN, InAs, InSb, GaSb, etc. may be used as superconductor materials.
Needless to say, superconducting materials such as Nb, MoN, oxides, and compounds may be used instead of Si. Also, SiO2, Si3N, etc. may be used instead of Si as the material for the protective film.
MgO.
ＡＱ 、０３を用いても、本発明の目的を達成すること
ができる。The purpose of the present invention can also be achieved using AQ,03.
以上述べた様に本発明によれば、製造が容易で特性のば
らつきが小さく、論理機能を実現することができるので
集積化に好適な超電導トランジスタを実現できる利点が
ある。As described above, according to the present invention, there is an advantage that a superconducting transistor suitable for integration can be realized because it is easy to manufacture, has small variations in characteristics, and can realize a logical function.
第１図は本発明の第１の実施例による超電導トランジス
タの一部分を示す断面図、第２図は本発明の第２の実施
例による超電導トランジスタの一部分を示す断面図、第
３図は本発明の第３の実施例による超電導トランジスタ
の一部分を示す断面図、第４図は本発明の第４の実施例
による超電導トランジスタの一部分を示す断面図である
。
１・・・基板、２・・・絶縁膜、３・・・第１の超電導
体、４・・・保護膜、５・・・高不純物濃度部、６・・
・超電導電極、７・・・第２の超電導体。FIG. 1 is a sectional view showing a part of a superconducting transistor according to a first embodiment of the invention, FIG. 2 is a sectional view showing a part of a superconducting transistor according to a second embodiment of the invention, and FIG. 3 is a sectional view showing a part of a superconducting transistor according to a second embodiment of the invention. FIG. 4 is a sectional view showing a portion of a superconducting transistor according to a fourth embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Insulating film, 3... First superconductor, 4... Protective film, 5... High impurity concentration part, 6...
- Superconducting electrode, 7... second superconductor.
Claims (1)
導体上に絶縁膜と制御電極とを有し、前記超電導体間を
流れる超電導電流の値を、前記制御電極に段加した電圧
によって制御する超電導トランジスタにおいて、前記制
御電極は前記半導体上に設けられた第１の超電導体と保
護膜と第２の超電導体との積層構造を少なくとも含み、
かつ半導体中を電流が流れる方向に関して前記第１の超
電導体の幅は前記保護膜の幅よりも狭く選ばれており、
かつ前記の制御電極を構成する第１の超電導体の直下の
半導体中に延在する高不純物濃度部を含んで構成される
ことを特徴とする超電導トランジスタ。 ２、特許請求の範囲第１項において、前記制御電極を構
成する第１の超電導体は、Ｎｂ、あるいはＮｂＮ等のＮ
ｂ化合物、Ｍｏ、あるいは ＭｏＮ等のＭｏ化合物、さらには酸化物超電導体である
ことを特徴とする超電導トランジスタ。 ３、特許請求の範囲第１項又は第２項において、前記保
護膜は、Ｓｉ、ＳｉＯ＿２、Ｓｉ＿３Ｎ＿４、ＭｇＯ、
Ａｌ＿２Ｏ＿３の材料の群から選ばれた少なくとも１つ
であることを特徴とする超電導トランジスタ。[Claims] 1. Two superconductors are provided facing each other on a semiconductor, and an insulating film and a control electrode are provided on the semiconductor, and the value of the superconducting current flowing between the superconductors is determined by the control electrode. In a superconducting transistor controlled by a voltage applied in stages, the control electrode includes at least a laminated structure of a first superconductor provided on the semiconductor, a protective film, and a second superconductor,
and the width of the first superconductor is selected to be narrower than the width of the protective film with respect to the direction in which current flows in the semiconductor,
A superconducting transistor characterized in that it is configured to include a high impurity concentration region extending in the semiconductor immediately below the first superconductor constituting the control electrode. 2. In claim 1, the first superconductor constituting the control electrode is Nb or N such as NbN.
A superconducting transistor characterized in that it is a compound, Mo, a Mo compound such as MoN, or an oxide superconductor. 3. In claim 1 or 2, the protective film includes Si, SiO_2, Si_3N_4, MgO,
A superconducting transistor characterized by being made of at least one material selected from the group of materials Al_2O_3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292027A JPH01135080A (en) | 1987-11-20 | 1987-11-20 | Superconducting transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292027A JPH01135080A (en) | 1987-11-20 | 1987-11-20 | Superconducting transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01135080A true JPH01135080A (en) | 1989-05-26 |
Family
ID=17776584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62292027A Pending JPH01135080A (en) | 1987-11-20 | 1987-11-20 | Superconducting transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01135080A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6774463B1 (en) * | 1990-02-01 | 2004-08-10 | International Business Machines Corporation | Superconductor gate semiconductor channel field effect transistor |
| JP2022525617A (en) * | 2019-03-22 | 2022-05-18 | アプライド マテリアルズ インコーポレイテッド | Methods and equipment for depositing multi-layer devices with superconducting membranes |
| US11739418B2 (en) | 2019-03-22 | 2023-08-29 | Applied Materials, Inc. | Method and apparatus for deposition of metal nitrides |
-
1987
- 1987-11-20 JP JP62292027A patent/JPH01135080A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6774463B1 (en) * | 1990-02-01 | 2004-08-10 | International Business Machines Corporation | Superconductor gate semiconductor channel field effect transistor |
| JP2022525617A (en) * | 2019-03-22 | 2022-05-18 | アプライド マテリアルズ インコーポレイテッド | Methods and equipment for depositing multi-layer devices with superconducting membranes |
| US11739418B2 (en) | 2019-03-22 | 2023-08-29 | Applied Materials, Inc. | Method and apparatus for deposition of metal nitrides |
| US11778926B2 (en) | 2019-03-22 | 2023-10-03 | Applied Materials, Inc. | Method and apparatus for deposition of multilayer device with superconductive film |
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